JPH01292455A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To form a semiconductor auxiliary storage device using an inexpensive semiconductor memory by converting an address having a defective bit in a main memory into an address in a spare memory. CONSTITUTION:A memory cartridge 1 is connected to an adaptor 2 through a connector 4. The cartridge 1 is constituted of a main memory 11, a control circuit (1) 16, a spare memory 14, an address converter 15 for converting an address having a defective bit in the main memory 11 into an address of the spare memory 14, and a memory 17 for an ECC circuit. The adaptor 2 is constituted of an external terminal 5, a control circuit (2), an ECC circuit, and an external interface 23. An external address signal is simultaneously inputted to the main memory 11 and the address converter 15, and when the signal coincides with a defective address stored in the converter 15, the main memory 11 is switched to the spare memory 14. The memory 17 stores a redundancy word for correcting an error to correct the error in the ECC circuit 22.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device, and particularly to a semiconductor auxiliary storage device suitable for an external storage device such as a computer.

[Conventional technology]

Conventional relatively small-capacity external storage devices are listed in the Hitachi Maxell Co., Ltd. product catalog (published at the Domestic Data Show on September 16, 1985), for example (1) Maxell MEMO.
RY CARTRIDE, company technical information, example (2) IC disk compatible with semiconductor file memory system SC8I
It is written in the IC disk driver. The cartridge of example (1) consists of logic such as memory, backup control, backup power supply, I/O buffer and write protection, and data conversion processor, and has a parallel I/O interface or serial interface (
R8232C) was built-in. On the other hand, in one case (2), I
The C disk (memory cartridge) consists of memory, backup control and batteries, and the IC disk driver (
adapter) is the bus driver, to PU.

It consisted of an SC8I interface, etc. All of these devices were constructed with good memory chips, and there were no memory chips with partial defective bits, no defect relief circuits, and no spare memory.
It is a semiconductor auxiliary storage device with a small capacity of bytes, and reliability measures such as semiconductor memory soft errors (radiation or temporary information reversal during signal transmission) and failures during user use were not considered.

On the other hand, in semiconductor auxiliary storage devices using semiconductor memory, the defective addresses of each memory are stored in the control circuit of the system, as shown in the Japanese Patent Patent Publication No. 47-6534, and the defective addresses are used to avoid them. P.G.M.
(Partially Good Memory) /
There is an MGM (Mostly Good Memory) method, but this method has disadvantages in that the control unit is complicated and expensive.

[ILM to be Solved by the Invention] In the above-mentioned conventional technology, semiconductor auxiliary storage devices can easily increase the capacity from several /O to several /O0M bytes as memory becomes highly integrated; In comparison, the unit cost per bit of semiconductor memory is more than an order of magnitude higher.

Furthermore, due to the increase in the number of memory chips due to the increase in capacity, it is also possible that the soft error rate due to radiation etc. will decrease. on the other hand.

The information in semiconductor auxiliary storage devices is backed up by batteries for a long period of time, so SRA, which has low standby current consumption, is the best semiconductor memory to make non-volatile.
M (Static Random Access M
However, SRAM has a high bit unit cost, which increases the cost of the memory element in the system. In addition, DRAM (Dynamic Random A
(ccess Memory) has a standby current consumption of SRA.
There is a problem that there are two to three orders of magnitude more than M. Furthermore, pseudo SRAM is an element with standby current consumption between the two.
(DRAM is equipped with a self-refresh circuit to reduce the power consumption of the entire circuit), but this is similar to SRAM.
There were problems such as about one order of magnitude more than .

An object of the present invention is to solve the above-mentioned problems and provide a highly reliable, nonvolatile, and low-cost semiconductor auxiliary memory device.

[Means to solve the problem]

The above objectives are: (1) to reduce costs;
(2) Reduce the refresh current of DRAM and pseudo SRAM to a low current to repair defective refresh bits; (3) Improve reliability. This can be achieved by, for example, applying an error correction circuit for

[Effect]

The defective bit relief circuit stores the defective bit address of the memory (including the retention defective bit of SRAM and the refresh defective bit of DRAM and pseudo SRAM), and activates the spare memory when the external address matches the defective bit address. and switch the main memory and spare memory input/output signals. As a result, the semiconductor auxiliary memory device reads and writes normal bits.

The error correction (FCC) circuit includes a data word consisting of data bits in the main memory and spare memory and a redundancy word consisting of redundant bits for error correction on the memory cartridge side, and error correction logic and control on the adapter side. Equipped with a circuit. This increases the reliability of the semiconductor auxiliary storage device and reduces the area occupied by the error correction circuit in the memory cartridge.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to two drawings.

FIG. 1 is a block diagram of a semiconductor auxiliary storage device showing a first embodiment of the present invention. 3 is the input/output (I/O) signal, various control signals, power supply Vcc2 and ground Vss terminals; 4 is the terminal 3 of the adapter 2;
5 is a female connector for mechanically connecting the 2 and 3. Reference numeral 5 indicates connection terminals for various signals, power supply, etc. with external devices. Further, 11 is a main memory consisting of a large number of semiconductor memories having defective bits;
Reference numeral 4 indicates a spare memory for relief, 12 indicates a backup control circuit, and 13 indicates a backup power supply. on the other hand,
Reference numeral 15 denotes an address conversion circuit which stores a new address of the spare memory 14 corresponding to the address of the defective bit and matching information (flag) indicating the presence or absence of the defective bit. 16 is a cartridge control circuit for write protection and detection of insertion of cartridge 1, which is composed of a logic circuit; 17 is a memory for redundant words of an error correction (FCC) circuit mainly for countermeasures against soft errors caused by radiation, etc.; 18 is an input/output circuit. In addition, 19 indicates an input/output (I/O) signal switching and interface circuit, while 21 of the adapter 2 is an interface circuit with the cartridge 1, and 20 mainly controls an external interface circuit 23. , generation of various commands consisting of a microprocessor, ROM, etc.

The control circuit of the device is shown. Further, 22 is an error correction circuit and its control circuit.

Next, the blocks of the present invention will be explained in terms of function and operation. Information on memory cartridge 1 is stored in backup control 1.
2. It is maintained for a long period of time by a backup power source 13, and can be attached to and detached from the adapter 2, making it portable. Also, the power supply (Veal) of the memory cartridge 1 is connected to the adapter 2.
Adapter 2 power supply (Vc
c2). Further, when the power is cut off, the power supply unit 1 operates to switch to the backup power supply 13 (Va) of the memory cartridge 1. As a result, the memory cartridge 1 has the ability to make the information non-volatile.

The address information of defective bits in the address conversion circuit is stored in a battery-backed SRAM or non-volatile memory, such as an EP ROM (ELE
critically Program+wable R
eadOnly Memory), EEPROM
(Electrically Erasable
Programa+able Read 0nly
Memory), fuse ROM, etc., so it will not be lost.

The defect relief circuit shown in the figure uses an external spare memory for relief, and the spare memory 14. Address conversion circuit 15. It is composed of an input/output (I/O) signal switching circuit 19, and the like. Here, the external address signal is input to the main memory 1 and the address conversion circuit 15 at the same time, and when it matches the defective address stored in the address conversion circuit, the I/O signal switching circuit 19 selects the spare address stored in the address conversion circuit 15. Based on the new memory address and the matching information (flag) written in the conversion circuit, the input/output (I/O) signal is switched from the main memory to the spare memory. As a result, the semiconductor auxiliary memory device reads and writes normal bits.

Note that as the main memory, either a memory with a defective bit or a non-defective memory can be used several times.

Similarly, any memory can be used as the spare memory, and in this case, the new address written to the address conversion circuit is stored while avoiding the defective bit address of the spare memory. Therefore, according to the present invention, a semiconductor auxiliary memory device can be realized by assembling memories in a wafer state without distinguishing between good and defective products, or by assembling a plurality of memory blocks as an aggregate. In addition, since the semiconductor auxiliary storage device of the present invention writes defective addresses to the address conversion circuit 15 composed of EEPROM, EPROM, fuse ROM, and battery-backed SRAM using software, even when the device is in operation after completion, , defects can be repaired easily.

Therefore, the defect relief circuit can be effectively applied to permanent hard error relief that occurs in the market, which is difficult to do with conventional devices.

Next, the error correction (FCC) circuit will be explained. The main memory 11 and spare memory 14 in the figure are actual data areas subject to error correction, and are generally referred to as data words. Further, a redundant memory area added for error correction is called a redundant word. In the present invention, the purpose of error correction is achieved by providing a redundant word memory for error correction in the memory cartridge 1 and an error correction logic and control circuit 22 in the adapter 2, as shown in FIG. On the other hand, with such a two-part arrangement of the error correction circuit, the error correction circuit installed in the cartridge 1 can be limited to the memory for redundant words, and the size of the memory cartridge 1 can be reduced by the error correction logic and the control circuit 2.
The area occupied by 2.

Can be reduced.

Furthermore, this circuit is more effective when used in large capacity devices than in small capacity semiconductor auxiliary storage devices. The reason for this is 1. For example, in a single-bit error correction FCC code,
This is because the redundancy word requires 5 bits for a 16-bit data word, but even if the data word becomes four times as large as 64 bits, the redundancy word becomes 7 bits, an increase of 2 bits at most.

Note that since the memory cartridge 1 always contains a redundant word of information bits for error correction, it goes without saying that the error correction function can be applied to other adapters having the same structure.

The purpose of the error correction circuit shown in this embodiment is to achieve high reliability against soft errors in a semiconductor auxiliary storage device by installing it, and one of the implementation methods is to use a redundant word memory, error correction logic, The circuit was divided and arranged. This allows the memory cartridge 1 to be miniaturized.The error correction circuit described above is not limited to resolving soft errors, but can also remediate a small number of defective bits that cause permanent errors, making it an even more reliable semiconductor aid. Can configure storage devices.

The main blocks of the semiconductor auxiliary memory device have been described above. In this embodiment, the cartridge 1 includes a male terminal,
Adapter 2 has a female connector, but the power supply V
The purpose is to electrically connect cc, ground Vss, and signal lines, and the effect is the same even if the embodiments of the connection parts, for example, male terminals and female connectors, are reversed.

Other embodiments of the semiconductor auxiliary memory device described above are shown in FIGS. 2 to 5. Figure 2 shows an example in which error correction circuits such as error correction memory and error correction logic are removed from Figure 1.
FIG. 3 is an example in which defect relief circuits such as a spare memory and an address conversion circuit are removed from FIG. 1.

FIG. 4 shows the control circuit 16 of the memory cartridge 1 shown in FIG.
This is an example in which a microprocessor (MPU) and a ROM are used. By providing a program in the memory cartridge 1 itself, this becomes effective in controlling the cartridge 1 itself and managing information on the cartridge 1 when used with another adapter.

FIG. 5 shows another embodiment of the backup control circuit 12 and power supply 13 of the cartridge 1 shown in FIG. 1. In FIG. Here, the backup power supply 43 is dedicated to the main memory, the spare memory 14, and the redundant word.

Further, the backup power supply 44 is used exclusively when an SRAM is used in the address conversion circuit 15 that stores the address of a defective bit. As a result, when the backup power supply 43 of the main memory and spare memory is replaced, the replacement can be done without destroying information.

Furthermore, if an SRAM is used in the address conversion circuit 15, there is a possibility that the stored defective address information will be destroyed due to a soft error. In general, soft errors in semiconductor memories tend to become stronger as the backup power supply voltage is increased, as the 'a product charge amount of memory cell information becomes larger. Therefore, by making the voltage of the backup power supply 42 used for the address conversion circuit 15 higher than the backup power supply 41 of the main memory and the spare memory, high reliability of defective address information against soft errors can be achieved.

Note that as the voltage of the backup power source increases, the standby current consumption of the memory also increases. However, the memory used in the address conversion circuit using SRAM is a few chips at most, and the standby current consumption of this circuit during backup is insignificant compared to the current consumption when holding information in semiconductor auxiliary storage devices, which have increased in capacity. It's the amount.

On the other hand, since the amount of this main memory reaches several/O to several/O00 chips, soft errors are countered by an error correction circuit as shown in this example, and the backup power supply voltage for retaining information in the device is kept as low as possible. You can also set this to reduce standby current consumption.

As described above, by providing two types of backup power sources for the cartridge 1, one for the main memory, one for the spare memory, and one for the address conversion circuit, a more flexible semiconductor auxiliary storage device can be constructed. Note that a large capacity capacitor other than a battery may be used as the power supply for the address conversion circuit. In that case, when replacing the backup power supply 41 of the main memory and spare memory, current supply from the capacitor other than the address conversion circuit will not occur. It goes without saying that if a non-volatile memory such as an EEFROM is used in the same circuit, backup of the address conversion circuit is no longer necessary.

6 and 7 show a method for starting the standby information retention operation when using the pseudo SRAM in the interface circuits 19 and 21 of FIG. It has a circuit that can reduce standby current consumption. Therefore, when powering off the device or separating cartridge 1 and adapter 2, it is sufficient to activate this circuit for retaining information. In the figure, /O0 is the inverter circuit, and 3 is the refresh signal terminal on the cartridge 1 side. ,
4 is the refresh signal terminal (connector) on the adapter 2 side
, Vccl is the power supply of the cartridge 1, R is a pull-up resistor, REFI is a refresh signal on the adapter 2 side (high voltage active), and REF2 is a refresh signal on the cartridge 1 side (low voltage active). In the figure, when the power to the semiconductor auxiliary storage device is cut off and when the cartridge 1 is removed from the adapter 2, the input terminal REFI of the inverter /O0 becomes a high voltage, and the output REF2 becomes a low voltage. As a result, the pseudo SRAM shifts to self-refresh operation.

Further, FIG. 7 shows an embodiment in which the connection between the cartridge 1 and the adapter 2 in FIG. 6 is replaced with an optical connection. /O1 is a signal conversion circuit from optical signal to TTL signal, /O2 is TT
A signal conversion circuit from an L signal to an optical signal, /O3 indicates a shutter for mechanical light shielding, and this embodiment is the same as above.
Due to the separation of cartridge 1 and adapter 2, the optical signal is blocked by the shutter/O3, causing light intensity attenuation, and REF2
becomes a low voltage and shifts to self-refresh operation. Furthermore, when the power is cut off, the amount of light attenuates and the same thing happens.

In addition, in the above, it is easy to apply the optical signal connection method to all input/output signals and control signal line connections of the device. In that case, mechanical wear and tear on the connecting portion can be eliminated and the life of the connecting portion can be dramatically extended. In this case, it is better to use mechanical connections for the power supply Vcc2 and the ground Vss, and use a mixture of optical connections and mechanical connections in terms of power supply.

As described above, the self-refresh operation of the 1wi-like SRAM can be activated by a combination of activation by separating the cartridge 1 and adapter 2 and activation by power cutoff. The circuit and signal logic used here describe one circuit configuration for starting the self-refresh operation, and are not specific to the circuit.
Needless to say, it can be used when the RAM is on standby, that is, when activating a retention operation.

Figure 8 shows the backup power supply 13 of the pseudo SRAM in Figure 1.
An example in which a small battery is used will be described below.

In the figure, r is the internal resistance of the backup power supply 13, and C is 13
A capacitor connected in parallel with , V c c 1 represents the power supply voltage, respectively. When backing up the pseudo SRAM, it is periodically used as a self-refresh operation power supply for a short period of time,
A large current of ~ several/O0mA flows. However, the backup power supply 13 has an internal resistance r of several Ω, and its short-term current supply capability is as low as several mA. Therefore, the power supply voltage V c c
1 causes a voltage drop, so this problem can be solved by connecting a large capacity capacitor C in parallel with the battery as shown in the figure. For example, the capacitor is sufficiently charged during the self-refresh operation period of 8 to 16 m5 of the pseudo SRAM, and becomes a source of a large current during refresh. As a result, the power supply voltage v due to the internal resistance r
It is possible to prevent a decrease in CC1 and prevent errors such as erroneous writing. Note that this embodiment can also be applied to a DRAM in which a large current flows for a short period of time due to a refresh operation.

FIG. 9 shows another embodiment of the method of attaching the adapter 2 and cartridge 1 of the semiconductor auxiliary storage device of FIG. 1.
In addition to the block shown in Fig. 1, the shape of the adapter 2 has been changed, and 45 is a male device guide bin for the cartridge 1 and adapter 2, and 46 is a female mounting guide bin (or a mounting guide bin). As shown in the figure, the adapter 2 in Fig. 1 covers the cartridge 1, but in this embodiment, it is held by male and female mounting guide bins shown in 45 and 46. Change the format to

The accuracy of the connection between the terminals 3 and the connector 4 is improved and the mechanical strength is strengthened. By this method, the adapter 2 is made smaller than the shape shown in FIG.

Note that this embodiment uses cartridge 1 and adapter 2 of the same device.
This describes a method for integrating the adapter 2 and the cartridge 1 using male and female guide bins, and as an application thereof, a mechanism for mechanically locking the adapter 2 and the cartridge 1 is also easy. In this case, the semiconductor auxiliary storage device can be made even stronger mechanically.

The semiconductor auxiliary storage device composed of the memory cartridge 1 and the adapter 2 has been described above.

The semiconductor memory used in the present invention includes a main memory 11, a spare memory 14, and an error correction memory 17, including an SRA with a static memory cell configuration, a DRAM and a pseudo SRAM with a dynamic memory cell configuration, and electrical writing and electrical erasing. EEFROM, EPROM that is written electrically and erased using ultraviolet light, etc. can be used. In addition to the above-mentioned memory, the memory used for the address conversion circuit may be either a fuse ROM or a battery-backed SRAM. Furthermore, the spare memory and main memory may be a combination of any of the above memories.For example, if the main memory is configured with pseudo SRAM and the spare memory is configured with SRAM, the complex refresh circuit when adding the relief circuit can be simplified. It has the advantage of being scalable.

In addition, since the backup power supply 12 of the present invention can use a primary or rechargeable secondary battery, low power consumption types such as SRAM use a primary battery, and DRAM, pseudo SR
For types such as AM that consume a lot of power, it is better to use a secondary battery.

In addition, retention defective bits of SRAM and DRAM
, Refresh defective bits in pseudo SRAM are mainly caused by leakage of accumulated charge in the diffusion layer portion, and the location of the defective address can be easily detected by high temperature accelerated testing. Therefore, memory testing does not become complicated due to the rescue.

On the other hand, a semiconductor auxiliary storage device may have a memory cartridge 1 and an adapter 2 integrated, but in this case, a defect relief circuit lowers the price and power consumption, and an error correction (FCC) circuit improves reliability. 1st prize is achieved.

〔Effect of the invention〕

According to the present invention, the following effects can be expected.

(1) Since an inexpensive semiconductor memory having defective bits can be used in the main memory and spare memory, the semiconductor auxiliary storage device can be set at a low price. (2) High reliability of the device can be achieved by the error correction circuit.

The above is effective in reducing the cost and increasing the reliability of the semiconductor auxiliary memory device.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a semiconductor auxiliary memory device showing a first embodiment of the present invention, FIGS. 2 to 5 are block diagrams of semiconductor auxiliary memory devices according to other embodiments of the present invention, and FIG. and FIG. 7 is a diagram showing a method of starting the standby information holding operation when using the pseudo SRAM in the interface circuit of FIG. 1. FIG. 8 is a diagram showing an embodiment in which a small battery is used as a backup power source for the pseudo SRAM shown in FIG. It is a figure showing an example.

Claims (1)

[Claims] 1. A main memory consisting of one or more memory chips, a spare memory consisting of one or more memory chips, and converting the address of a defective bit in the main memory to a new address. A semiconductor memory device comprising at least an address conversion circuit, an I/O switching circuit that switches input/output signals (I/O) between a main memory and a spare memory, and an information backup circuit using a battery. 2. The defective bit of the main memory is DRAM, pseudo SRA
2. The semiconductor memory device according to claim 1, wherein the semiconductor memory device includes M refresh defective bits or SRAM retention defective bits. 3. A semiconductor memory device according to claims 1 and 2, wherein the spare memory also has a defective bit. 4. Claim 1, characterized in that the device has a structure consisting of a cartridge and an adapter for driving the cartridge.
The semiconductor storage device described in 1. 5. In the semiconductor storage device according to claim 4, the cartridge is provided with a memory section constituting a redundant word of the error correction circuit, and the adapter is provided with an error correction logic and its control circuit. Characteristic semiconductor memory device. 6. The semiconductor storage device according to claim 4, wherein the cartridge includes a microprocessor, an electrically written and electrically erased EEPROM, an electrically written and ultraviolet ray erased EPROM, a fuse ROM, or a battery-backed SRAM. A semiconductor storage device comprising any of the following.