JPH01289278A - Semiconductor integrated circuit - Google Patents
Semiconductor integrated circuitInfo
- Publication number
- JPH01289278A JPH01289278A JP63120909A JP12090988A JPH01289278A JP H01289278 A JPH01289278 A JP H01289278A JP 63120909 A JP63120909 A JP 63120909A JP 12090988 A JP12090988 A JP 12090988A JP H01289278 A JPH01289278 A JP H01289278A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor integrated
- integrated circuit
- package
- circuit chips
- chips
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 61
- 230000006870 function Effects 0.000 claims description 3
- 238000000034 method Methods 0.000 abstract description 3
- 238000004806 packaging method and process Methods 0.000 description 6
- 230000000694 effects Effects 0.000 description 4
- 230000010354 integration Effects 0.000 description 3
- 238000007789 sealing Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 2
- 238000001465 metallisation Methods 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 238000010586 diagram Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Landscapes
- Lead Frames For Integrated Circuits (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、半導体集積回路に関し、更に詳しくは、半
導体集積回路チップの面積当りの素子数の上限に対して
、実装密度を高めた半導体集積回路に関するものである
。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor integrated circuit, and more specifically, to a semiconductor integrated circuit with a higher packaging density than the upper limit of the number of elements per area of a semiconductor integrated circuit chip. It is related to circuits.
第３図は従来の半導体集積回路の一部＃ｌ砕ｆ＋硯図、
第４図は第３図に示すＸ＠ｘを含む垂直面における断面
図である。Figure 3 shows part of a conventional semiconductor integrated circuit.
FIG. 4 is a sectional view taken along a vertical plane including X@x shown in FIG.
図において、（１）は樹脂モールド、（２）はリード、
（３）は半導体集積回路チップ、（４）はワイヤ、（５
）はＡｖのメタライズである。In the figure, (1) is a resin mold, (2) is a lead,
(3) is a semiconductor integrated circuit chip, (4) is a wire, (5
) is the metallization of Av.
次に半導体集積回路チップ（３）の配置について説明す
る。第３因に示すように従来はパッケージ内に半導体集
積回路チップ（３）は１個であ夛、これがワイヤ（４）
によシリード（２）に接続され、樹脂モールド（１）で
封止されている。このために、半導体集積回路チップ（
３）の１個当りの集積度がその半導体集積回路の集積度
を決定する。Next, the arrangement of the semiconductor integrated circuit chip (3) will be explained. As shown in the third factor, conventionally there was only one semiconductor integrated circuit chip (3) in the package, and this was the wire (4).
It is connected to the serial lead (2) and sealed with a resin mold (1). For this purpose, semiconductor integrated circuit chips (
3) The degree of integration per unit determines the degree of integration of the semiconductor integrated circuit.
従来の半導体集積回路チップ配置は以上のようになって
いるので、この実装方法では、限られた半導体集積回路
チップの面積を最大限に利用して、微細化、高集積化で
対応しているプロセス技術にも限界がある。これは、１
個の半導体集積回路チップ上で構成される電子回路規模
に限界を与えることになっている。すなわち、大規模な
電子回路を半導体集積回路チップで英埃するためには、
その限界があるために複数個に分けなければならなくな
シ、電子回路が大きくなればなるほど半導体集積回路チ
ップ数が増加する。このために、従来の半導体集積回路
は、それぞれの半導体集積回路テップを別々のパッケー
ジに封止したため、実装する面積はその個数分以上が必
要であるなどの問題点があった。Since the conventional semiconductor integrated circuit chip layout is as described above, this mounting method makes maximum use of the limited area of the semiconductor integrated circuit chip and supports miniaturization and high integration. Process technology also has its limits. This is 1
This puts a limit on the scale of electronic circuits that can be constructed on a single semiconductor integrated circuit chip. In other words, in order to build large-scale electronic circuits using semiconductor integrated circuit chips,
Due to this limitation, it is necessary to divide it into multiple pieces, and as the electronic circuit becomes larger, the number of semiconductor integrated circuit chips increases. For this reason, in conventional semiconductor integrated circuits, each semiconductor integrated circuit chip is sealed in a separate package, resulting in problems such as the need for a mounting area equal to or larger than the number of semiconductor integrated circuit chips.
この発明は上記のような問題点を解消するためになされ
たもので、高密度実装できるとともに、用途別半導体集
積回路チップの組み合せによシ多品種少量生産に対応で
きる高密度実装の半導体集積回路を得ることを目的とす
る。This invention was made in order to solve the above-mentioned problems, and provides a high-density packaging semiconductor integrated circuit that can be mounted in a high density and is compatible with high-mix, low-volume production by combining application-specific semiconductor integrated circuit chips. The purpose is to obtain.
ＣＩＩＫ題を解決するための手段〕
この発明に係る半導体集積回路は、半導体集積回路チッ
プ上にそれと同機能若しくは異機能の半導体集積回路チ
ップを複数段に接触若しくは非接触で積み重ねて、上記
半導体集積回路チップの端子間とパッケージのリード間
とを接続して、同一パッケージに封止したものである。Means for Solving the CIIK Problem] A semiconductor integrated circuit according to the present invention is produced by stacking semiconductor integrated circuit chips having the same or different functions on a semiconductor integrated circuit chip in a plurality of stages in contact or non-contact. The terminals of the circuit chip and the leads of the package are connected and sealed in the same package.
この発明における半導体集積回路は、半導体集積回路チ
ップを複数段積み重ねて、上記半導体集積回路チップの
端子間とパッケージのリードとを接続して、同一パッケ
ージに封止することによ久実装密度が高められる。The semiconductor integrated circuit of the present invention has a high packaging density for a long time by stacking semiconductor integrated circuit chips in multiple stages, connecting the terminals of the semiconductor integrated circuit chips to the leads of the package, and sealing them in the same package. It will be done.
以下、この発明の一実施例について説明する０第１図は
半導体集積回路の一部破砕斜視図、第２図は第１図に示
すＹ−Ｙを含む＠直面における断面図である０図におい
て、（１） 、 （２） 、 （４） 、 （５）は第
３図及び第４図の従来例に示したものと同等であるので
説明を省略する。（３ａ）、（３ｂ）は半導体集積回路
チップ、（６）は半導体集積回路チップ（３ａ）、（３
ｂ）の端子間を接続するためのワイヤである。Hereinafter, one embodiment of the present invention will be described. FIG. 1 is a partially exploded perspective view of a semiconductor integrated circuit, and FIG. 2 is a cross-sectional view taken along the plane Y-Y shown in FIG. 1. , (1), (2), (4), and (5) are the same as those shown in the conventional example of FIGS. 3 and 4, so their explanation will be omitted. (3a), (3b) are semiconductor integrated circuit chips, (6) are semiconductor integrated circuit chips (3a), (3
This is a wire for connecting the terminals of (b).
次に半導体集積回路チップ（３ａ）、（３ｂ）として読
み書き可能な記憶回路チップｃ以下ＲＡＭという）を使
用して実装密度を高めた半導体集積回路の一例について
作用を説明する。ＲＡＭの中には単位記憶素子（以下ビ
ットという）がアシ、そのビットごとに情報が蓄えられ
ている。読み書きしたいビットに対してそのビットを指
し示す回路Ｃ以下デコーダという）を追加して、すべて
のビットに対してそれぞれを指し示すようにする。ここ
で、ＲＡＭのビット改が２５６ビツトあるとすると、デ
コーダがそれぞれを指し示す指標（以下アドレスという
）も２５６個必要である。半導体集積回路チップ（３ａ
）、（３ｂ）のうち１個（例えｔｆ（３ａ））のデコー
ダが１番地から２５６番地のアドレスを指し示すように
して、もう一方の半導体集積回路チップ（例えは（３ｂ
））のデコーダをアドレス２５７番地から５１２番地ま
で指し示すことができるようにする。Next, the operation of an example of a semiconductor integrated circuit with increased packaging density using read/write memory circuit chips (hereinafter referred to as RAM) as semiconductor integrated circuit chips (3a) and (3b) will be described. Inside the RAM, unit memory elements (hereinafter referred to as bits) are arranged, and information is stored for each bit. A circuit C (hereinafter referred to as a decoder) that points to the bit that you want to read or write is added to point to all the bits. Here, assuming that the RAM has 256 bits, 256 indicators (hereinafter referred to as addresses) for pointing the decoder to each are also required. Semiconductor integrated circuit chip (3a
), (3b) (for example, tf(3a)) points to an address from address 1 to 256, and the other semiconductor integrated circuit chip (for example, (3b)
)) decoder can be pointed from address 257 to address 512.
更に、半導体集積回路チップ（３ａ）、（３ｂ） ＠子
間を接続し、また、半導体集積回路チップ（３ａ）、（
３ｂ）端子間とパッケージのリード（２）間を接続して
同一パッケージに封止することによｆｉ、５１２ビツト
のＲＡＭができ死ことになる。Further, the semiconductor integrated circuit chips (3a) and (3b) are connected together, and the semiconductor integrated circuit chips (3a) and (3b) are connected together.
3b) By connecting the terminals and the leads (2) of the package and sealing them in the same package, a 512-bit RAM can be created.
上記のようにすることで、従来複数個のパッケージが必
要であった半導体集積回路が、１つのパッケージで従来
の複数個のパッケージの半導体集積回路と同等若しくは
それ以上の機能、めるいは容量を有する半導体集積回路
となる。すなわち、少くともそのパッケージの個数分必
要であった実装面積が、１つのパッケージが占める面積
だけでよいことになる。By doing the above, semiconductor integrated circuits that conventionally required multiple packages can now have the same or higher functionality, capacity, or capacity in a single package as semiconductor integrated circuits in multiple packages. It becomes a semiconductor integrated circuit with In other words, the mounting area required for at least the number of packages is reduced to the area occupied by one package.
なお、上記実施例では半導体集積回路チップをＲＡＭと
したものを示したが、それが読み出し専用記憶回路であ
ってもよく、また、これら半導体集積回路チップのうち
、いくつかを中央演算処理回路としてもよ（、ＲＡＭと
組み合せることで主記憶を備えた処理回路にもなる。こ
のように半導体集積回路チップは異機能の組み合せでも
よく、上記実施例と同様の効果を奏する。In the above embodiment, the semiconductor integrated circuit chips are shown as RAMs, but they may also be read-only memory circuits, and some of these semiconductor integrated circuit chips may be used as central processing circuits. By combining it with a RAM, it can also become a processing circuit with a main memory.In this way, the semiconductor integrated circuit chips may be combined with different functions, and the same effects as in the above embodiments can be achieved.
以上のように、この発明によれば、従来半導体集積回路
チップ１個だけ封止していたものを、複数個を互いに接
続して同一パッケージに封止したので、実装密度を高め
、さらに従来のプリント基板上での半導体集積回路チッ
プ間の配線に比較し配線が短くなったことで特性のよい
半導体集積回路が得られる効果がある。As described above, according to the present invention, instead of conventionally sealing only one semiconductor integrated circuit chip, multiple semiconductor integrated circuit chips are connected to each other and sealed in the same package, increasing the packaging density and further improving the packaging density. Since the wiring is shorter than the wiring between semiconductor integrated circuit chips on a printed circuit board, there is an effect that a semiconductor integrated circuit with good characteristics can be obtained.
第１図はこの発明の一実施例による半導体集積回路の一
部破砕斜視図、第２図は第１図のＹ−Ｙを含む垂直面に
おける断面図、第３図は従来の半導体集積回路の一部破
砕斜視図、第４図は第３図のＸ−Ｘを含む垂直面におけ
る断面図である０図において、（１）は樹脂モールド、
（２）はリード、（３ａ）、（３ｂ）は半導体集積回路
チップ、（１、（６）はワイヤ、（５）はメタライズで
ある０
なお、図中同一符号は同−又は相当部分を示す。FIG. 1 is a partially exploded perspective view of a semiconductor integrated circuit according to an embodiment of the present invention, FIG. 2 is a cross-sectional view along the vertical plane including Y-Y in FIG. 1, and FIG. 3 is a diagram of a conventional semiconductor integrated circuit. In FIG. 0, which is a partially fragmented perspective view and FIG.
(2) is a lead, (3a) and (3b) are semiconductor integrated circuit chips, (1 and (6) are wires, and (5) is metallization.0 Note that the same reference numerals in the figures indicate the same or equivalent parts. .
Claims (1)
の半導体集積回路チップを、複数段に接触若しくは非接
触で積み重ねて、上記半導体集積回路チップの端子間及
び半導体集積回路チップの端子と、これら半導体集積回
路チップを収納するパッケージのリードとを接続して、
同一パッケージに封止したことを特徴とする半導体集積
回路。Semiconductor integrated circuit chips with the same or different functions are stacked on top of the semiconductor integrated circuit chip in multiple stages in contact or non-contact, and between the terminals of the semiconductor integrated circuit chip and between the terminals of the semiconductor integrated circuit chip and these semiconductors. Connect the leads of the package that houses the integrated circuit chip,
A semiconductor integrated circuit characterized by being sealed in the same package.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63120909A JPH01289278A (en) | 1988-05-17 | 1988-05-17 | Semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63120909A JPH01289278A (en) | 1988-05-17 | 1988-05-17 | Semiconductor integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01289278A true JPH01289278A (en) | 1989-11-21 |
Family
ID=14797999
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63120909A Pending JPH01289278A (en) | 1988-05-17 | 1988-05-17 | Semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01289278A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5821618A (en) * | 1994-08-12 | 1998-10-13 | Siemens Aktiengesellschaft | Semiconductor component with insulating housing |
| WO2002084737A3 (en) * | 2001-04-10 | 2003-07-03 | Microchip Tech Inc | Arrangement and method of arrangement of stacked dice in an integrated electronic device |
-
1988
- 1988-05-17 JP JP63120909A patent/JPH01289278A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5821618A (en) * | 1994-08-12 | 1998-10-13 | Siemens Aktiengesellschaft | Semiconductor component with insulating housing |
| WO2002084737A3 (en) * | 2001-04-10 | 2003-07-03 | Microchip Tech Inc | Arrangement and method of arrangement of stacked dice in an integrated electronic device |
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