JPH01288134A - Changeover system for master equipment and sub-master equipment of loop lan - Google Patents

Changeover system for master equipment and sub-master equipment of loop lan

Info

Publication number
JPH01288134A
JPH01288134A JP63117093A JP11709388A JPH01288134A JP H01288134 A JPH01288134 A JP H01288134A JP 63117093 A JP63117093 A JP 63117093A JP 11709388 A JP11709388 A JP 11709388A JP H01288134 A JPH01288134 A JP H01288134A
Authority
JP
Japan
Prior art keywords
master equipment
sub
external clock
master
master device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63117093A
Other languages
Japanese (ja)
Inventor
Tadashi Kihara
正 木原
Riyuushirou Nunomura
布村 隆史朗
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP63117093A priority Critical patent/JPH01288134A/en
Publication of JPH01288134A publication Critical patent/JPH01288134A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To attain changeover from a master equipment to a sub-master equipment even in the interruption of an external clock by sending changeover information of the master equipment and the sub-master equipment in addition to the information representing the reception state of an external clock newly as well as the state of the master equipment as the changeover information of the master equipment and the sub-master equipment. CONSTITUTION:The sub-master equipment 2 inserts '1' to an external clock frame during the reception of an external clock and inserts '0' when a reception clock is interrupted. Thus, if the external clock to its own station is interrupted, the master equipment 1 discriminates the state of the sub-master equipment 2 by the external clock reception frame and remains the bit of a master function sub-master function switching control frame to '0' in the presence of the external clock of the sub-master equipment 2 thereby switching the function between the master equipment 1 and the sub-master equipment 2 and is operated by the clock of the master equipment 1 while independent synchronization is applied to the loop even if the external clock supply to the sub-master equipment 2 is interrupted simultaneously.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明はループ形LANのマスタ装置、サブマスタ装置
切替に関し、特に外部クロックを受信することのできる
ループ形LANのマスタ装置。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to switching between a loop-type LAN master device and a sub-master device, and particularly to a loop-type LAN master device capable of receiving an external clock.

サブマスタ装置切替方式に関する。This invention relates to a submaster device switching method.

〔従来の技術〕[Conventional technology]

従来、マスタ装置及びサブマスタ装置を有し。 Conventionally, it has a master device and a sub-master device.

外部クロックを受信することのできるループ形LANで
は、マスタ局からサブマスタ局への切替はマスタ装置の
障害時のみに行われている。
In a loop type LAN capable of receiving an external clock, switching from a master station to a submaster station is performed only when a failure occurs in the master device.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述した従来のループ形LANのマスタ装置。 The above-mentioned conventional loop type LAN master device.

サブマスタ装置の切替では、マスタ装置の障害時のみ切
替動作が行われるから、 LANシステムが外部クロッ
ク受信によって動作時に、マスタ装置への外部クロック
が断になった場合、マスタ装置の障害でない限り、マス
タ装置からサブマスタ装置への切替動作が行われず、そ
の結果。
When switching sub-master devices, the switching operation is performed only when the master device fails, so if the external clock to the master device is cut off while the LAN system is operating by receiving an external clock, the master device will be switched off unless there is a failure in the master device. As a result, the switching operation from the device to the submaster device is not performed.

外部網との受信が行なえなくなるという問題点がある。There is a problem in that reception with external networks is no longer possible.

〔課題を解決するための手段〕[Means to solve the problem]

本発明によれば、外部クロック受信機能を有し、マスタ
装置及びサブマスタ装置を備えるル−プ形光LANにお
いて、該マスタ装置及びサブマスタ装置の外部クロック
受信状態を監視・伝送する第1の手段と、前記マスタ装
置への外部クロック断の際に同期/監視系を前記マスタ
装置から前記サブマスタ装置へ切替える第2の手段とを
有することを特徴とするループ形LANのマスタ装置・
サブマスタ装置の切替方式が得られる。
According to the present invention, in a loop optical LAN having an external clock receiving function and including a master device and a submaster device, first means for monitoring and transmitting the external clock reception state of the master device and the submaster device; , a second means for switching a synchronization/monitoring system from the master device to the sub-master device when an external clock to the master device is cut off.
A submaster device switching method is obtained.

〔作用〕[Effect]

本発明のループ形LANマスタ装置・サブマスタ装置切
替方式はマスタ装置及びサブマスタ装置の切替情報とし
て、マスタ装置の状態だけでなく新たに外部クロックの
受信状態を示す情報を加えて伝送することにより、外部
クロックの断によっても、マスタ装置からサブマスタ装
置への切替が行われる。
The loop-type LAN master device/submaster device switching method of the present invention adds and transmits not only the state of the master device but also information indicating the receiving state of the external clock as switching information of the master device and submaster device. Switching from the master device to the sub-master device also occurs due to clock interruption.

〔実施例〕〔Example〕

次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第1図は本発明が適用されたループ形LANシステムの
全体構成図である。第1図を参照して。
FIG. 1 is an overall configuration diagram of a loop type LAN system to which the present invention is applied. Referring to FIG.

1はループ内の同期制御を司どると共にディジタル同期
網との接続のための外部クロック受信機能を有するマス
タ装置、2はマスタ装置1の障害等によりマスタ装置1
の機能を代行するサブマスタ装置であり、マスタ装置1
及びサブマスタ装置2はそれぞれループ内に1台ずつ設
置される。3は各種インタフェース盤を収容することが
可能な端局装置でループ内に複数台設置され、各種端末
機器(図示せず)を接続することができる。10は少な
くとも2芯の光ファイバを内蔵した光フアイバケーブル
であり各端局装置前3を接続する。20はディジタル同
期網とLANを接続する為にディジタル網からのクロッ
クをループに供給するための装置であり、jf、た30
゜及び40はそのクロックをループに与える為のクロッ
ク供給ケーブルである。
1 is a master device that manages synchronization control within the loop and has an external clock reception function for connection with a digital synchronous network; 2 is a master device that controls the synchronization control within the loop; and 2, the master device 1
It is a submaster device that performs the functions of master device 1.
One sub-master device 2 and one sub-master device 2 are installed in each loop. Reference numeral 3 denotes a terminal station device capable of accommodating various interface boards. A plurality of terminal station devices are installed in a loop, and various terminal devices (not shown) can be connected thereto. Reference numeral 10 denotes an optical fiber cable containing at least two optical fibers, and connects the front terminals 3 of each terminal station. 20 is a device for supplying a clock from the digital network to the loop in order to connect the digital synchronous network and the LAN;
and 40 are clock supply cables for supplying the clock to the loop.

第2図はループ内を伝送するデータフレームフォーマッ
トである。】000は全体のデータ伝送フレームであり
+  1000aのマスタ機能サブマスタ機能切替え制
御フレーム(MSW)、 1000bの外部りOツク7
 v −ム(EXT CLOCK ) 、 1000c
のデータフレーム(DATA)、  1000dの制御
及び同期フレーム(SV−8YN)により構成される。
FIG. 2 shows the data frame format transmitted within the loop. ] 000 is the entire data transmission frame + 1000a master function submaster function switching control frame (MSW), 1000b external Otsuk7
v-mu (EXT CLOCK), 1000c
It consists of a data frame (DATA) of 1000d and a control and synchronization frame (SV-8YN) of 1000d.

外部クロックの受信によりループ形LANが動作する場
合、マスタ装置1.サブマスタ装置2は外部のディジタ
ル同期網よりクロック供給装置2を介して同期用クロッ
クを受信し、そのクロックにマスタ装置1のクロックが
従属同期しループは動作する。
When a loop type LAN operates by receiving an external clock, the master device 1. The sub-master device 2 receives a synchronization clock from an external digital synchronization network via the clock supply device 2, and the clock of the master device 1 is slave-synchronized to the clock, and the loop operates.

また、ループ内のマスタ装置・サブマスタ装置の切替は
データフレームフォーマツl−(1000)の中のマス
タ機能サブマスタ機能切替制御フレームにマスタ装置1
が11”を挿入し、サブマスタ装置2でそれをO″に変
換することによシ行なわれ、サブマスタ装置2はこの切
替制御フレームを監視し、自局に到着した時この切替制
御フレームが”1”であれば”0”に変換し、”0″で
あればサブマスタ機能を動作させることでマスタ装置1
からサブマスタ装置2への切替が行われる。さらにサブ
マスタ装置2では自局が外部クロックを受信中は外部ク
ロックフレーム(1000b)に91′を挿入し、受信
クロックが断になった場合”O′を挿入する。こうする
ことによりマスタ ゛装置1では現在サブマスタ装置2
がクロックを受信中か否かを知ることができる。
In addition, switching between the master device and submaster device in the loop is performed using the master function submaster function switching control frame in the data frame format l-(1000).
This is done by inserting 11" and converting it to O" in submaster device 2. Submaster device 2 monitors this switching control frame, and when it arrives at its own station, this switching control frame is "1". If it is "0", it is converted to "0", and if it is "0", the submaster function is activated to control master device 1.
Switching from the submaster device 2 to the submaster device 2 is performed. Furthermore, submaster device 2 inserts 91' into the external clock frame (1000b) while its own station is receiving the external clock, and inserts "O" when the receiving clock is cut off.By doing this, master device 1 Now submaster device 2
It is possible to know whether or not the device is receiving the clock.

ところで従来、マスタ装置への外部クロックが断になっ
た場合、ループは独立同期になシ。
By the way, conventionally, if the external clock to the master device is cut off, the loop cannot be independently synchronized.

外部ディジタル同期網との接続ができなくなってしまっ
たのに対し2本発明では、外部クロック受信フレームに
よりマスタ装置1は自局への外部クロックが断となった
場合、サブマスタ装置2の状態を判断し、サブマスタ装
置2の外部クロックがあれば、マスタ機能サブマスタ機
能切替制御フレームのビットを”0″のままとし。
In the present invention, the master device 1 determines the status of the submaster device 2 when the external clock to its own station is cut off based on the external clock reception frame. However, if there is an external clock for the submaster device 2, leave the bit in the master function submaster function switching control frame as "0".

マスタ装置1.サブマスタ装置2間の機能を切替えるこ
とができ、またサブマスタ装置2への外部クロック供給
も同時に断となった場合にはループは独立同期としてマ
スタ装置1のクロックにて動作することができるように
なる。
Master device 1. The functions between the submaster devices 2 can be switched, and if the external clock supply to the submaster device 2 is also cut off at the same time, the loop can operate with the clock of the master device 1 as an independent synchronization. .

このようにマスタ装置1はサブマスタ装置2のクロック
受信状態を知ることにより自局障害時のみでなく、外部
クロックの有無でも、マスタ装置、サブマスタ装置の切
替が可能となる。
In this way, by knowing the clock reception state of the submaster device 2, the master device 1 can switch between the master device and the submaster device not only when there is a failure in its own station, but also whether there is an external clock or not.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明では、サブマスタ装置からマ
スタ装置に対して外部クロックの受信状態を伝送するこ
とによりマスタ装置への外部クロック断によシサプマス
タ装置への切替が行われる。その結果、サブマスタ装置
によシ外部網との同期がとれ、外部クロック供給装置か
らマスタ装置へのクロック供給が断となった場合にも外
部網との通信が可能となるという効果がある。
As described above, in the present invention, the submaster device transmits the reception state of the external clock to the master device, so that switching to the submaster device is performed when the external clock is disconnected from the master device. As a result, the submaster device can synchronize with the external network, and even if the clock supply from the external clock supply device to the master device is cut off, communication with the external network is possible.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例を示す概念図、第2図はルー
プ形LAN内の伝送フレームフォーマットを示す図であ
る。 1・・・マスタ装置、2・・・サブマスタ装置、3・・
・端局装置、10・・・光フアイバケーブル、20・・
・クロック供給装置、30・・・外部クロック供給ケー
ブル。 40・・・外部クロック供給ケーブル、  1000・
・・データ伝送フレーム、  1000a・・・マスタ
機能・サブマスタ機能切替制御フレーム(MSW) 、
  1000b・・・外部クロックフレーム(EXT 
CLOCK) 、  1000 c・・・データフレー
ム(DATA) 、  1000d・・・制御及び同期
フレーム(SV−8YN)。 第2図 too。
FIG. 1 is a conceptual diagram showing an embodiment of the present invention, and FIG. 2 is a diagram showing a transmission frame format within a loop type LAN. 1...Master device, 2...Submaster device, 3...
・Terminal equipment, 10... Optical fiber cable, 20...
- Clock supply device, 30...external clock supply cable. 40...External clock supply cable, 1000...
...Data transmission frame, 1000a...Master function/submaster function switching control frame (MSW),
1000b...External clock frame (EXT
CLOCK), 1000c...Data frame (DATA), 1000d...Control and synchronization frame (SV-8YN). Figure 2 too.

Claims (1)

【特許請求の範囲】[Claims] 1外部クロック受信機能を有し、マスタ装置及びサブマ
スタ装置を備えるループ形光LANにおいて、該マスタ
装置及びサブマスタ装置の外部クロック受信状態を監視
・伝送する第1の手段と、前記マスタ装置への外部クロ
ック断の際に同期/監視系を前記マスタ装置から前記サ
ブマスタ装置へ切替える第2の手段とを有することを特
徴とするループ形LANのマスタ装置・サブマスタ装置
切替方式。
1. In a loop optical LAN having an external clock receiving function and including a master device and a submaster device, a first means for monitoring and transmitting the external clock reception state of the master device and the submaster device, and a first means for monitoring and transmitting the external clock reception state of the master device and the submaster device, and second means for switching a synchronization/monitoring system from the master device to the submaster device when a clock is cut off.
JP63117093A 1988-05-16 1988-05-16 Changeover system for master equipment and sub-master equipment of loop lan Pending JPH01288134A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63117093A JPH01288134A (en) 1988-05-16 1988-05-16 Changeover system for master equipment and sub-master equipment of loop lan

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63117093A JPH01288134A (en) 1988-05-16 1988-05-16 Changeover system for master equipment and sub-master equipment of loop lan

Publications (1)

Publication Number Publication Date
JPH01288134A true JPH01288134A (en) 1989-11-20

Family

ID=14703221

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63117093A Pending JPH01288134A (en) 1988-05-16 1988-05-16 Changeover system for master equipment and sub-master equipment of loop lan

Country Status (1)

Country Link
JP (1) JPH01288134A (en)

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