JPH01286654A - Automatic gain control circuit - Google Patents

Automatic gain control circuit

Info

Publication number
JPH01286654A
JPH01286654A JP63116203A JP11620388A JPH01286654A JP H01286654 A JPH01286654 A JP H01286654A JP 63116203 A JP63116203 A JP 63116203A JP 11620388 A JP11620388 A JP 11620388A JP H01286654 A JPH01286654 A JP H01286654A
Authority
JP
Japan
Prior art keywords
output
signal
clock
data signal
amplifier
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP63116203A
Other languages
Japanese (ja)
Other versions
JPH0636503B2 (en
Inventor
Fujio Hayashida
林田 冨次雄
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP63116203A priority Critical patent/JPH0636503B2/en
Publication of JPH01286654A publication Critical patent/JPH01286654A/en
Publication of JPH0636503B2 publication Critical patent/JPH0636503B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Control Of Amplification And Gain Control (AREA)
  • Dc Digital Transmission (AREA)
  • Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)
  • Optical Communication System (AREA)

Abstract

PURPOSE:To facilitate the detection of a clock shut-off by unifying the sum of the peak value detecting output of a data signal and the detecting output of a low frequency component outside a data signal band. CONSTITUTION:For the output of an amplifier 2, the peak detection of a pulse waveform is executed by a detector 3, the low frequency component outside the band of a data signal out of signals to exist at the output of the amplifier 2 is removed by an LPF4, detected by a detector 5 and sent to an adder 16. The adder 16 adds the output of respective detectors 3 and 5, sends it to an LPF6 and the smoothed signal is sent to a comparator 8. The comparator 8 compares and amplifies the output of a reference voltage source 7 and the output of the LPF6 and controls a bias generating circuit 9. When the light signal input to an APD1 is shut-off, the noise or a micro prasma noise due to the dark current of the APD1 is inputted to the amplifier 2, the clock signal level of the noise at the output side is made smaller and the decision of the clock shut-off can be stably executed by a clock shut-off detector 12.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 1.0のパルス列よりなるデータ信号で強度変調された
光信号を復調・増幅、識別再生する光受信器に利用する
。特に、この光受信器の自動利得制御回路に関する。
DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention is used in an optical receiver that demodulates, amplifies, and identifies and reproduces an optical signal intensity-modulated with a data signal consisting of a 1.0 pulse train. In particular, it relates to an automatic gain control circuit for this optical receiver.

〔概要〕〔overview〕

本発明は、パルス信号で強度変調された光信号を復調・
増幅、識別再生する光受信器の自動利得制御回路におい
て、 データ信号のピーク値検波出力とデータ信号帯域外の低
周波成分の検波出力との和を一定にすることにより、 クロック断検出を容易にすることができるようにしたも
のである。
The present invention demodulates and modulates an optical signal intensity-modulated with a pulse signal.
In the automatic gain control circuit of an optical receiver that performs amplification, identification and regeneration, clock loss detection is easily detected by keeping the sum of the peak value detection output of the data signal and the detection output of the low frequency component outside the data signal band constant. It has been made possible to do so.

〔従来の技術〕[Conventional technology]

従来例は、第2図に示すように、アバランシェフォトダ
イオード(以下、APDという。)1と、増幅器2と、
検波器3と、低域ろ波器6と、基準電圧源7と、比較器
8と、バイアス発生回路9と、識別器10と、クロック
抽出器11と、クロック断検出器12と、禁止回路13
と、データ信号出力端子14と、クロック信号出力端子
15とを備える。APDlに入力されたパルス変調され
た光信号はAPDlを経由するときにバイアス発生回路
9の出力電圧で決定される増倍率に比例した電流に変換
され、増幅器2へ送られる。増幅器2はAPDIの出力
電流を検波ができるレベルにまで増幅し、検波器3へ送
出する。検波器3は増幅器2の出力であるデータ信号の
ピーク検波を行い、低域ろ波器6へ送出する。低域ろ波
器6は検波器3の出力を平滑化し、比較器8へ送出する
。比較器8は基準電圧源7の出力と低域ろ波器6の出力
とを比較増幅し、誤差出力をバイアス発生回路9へ送出
する。バイアス発生回路9は、その出力電圧が比較器8
の出力によって制御され、APDlにバイアスを供給す
る。APDI、増幅器2、検波器3、低域ろ波器6、基
準電圧R7、比較器8およびバイアス発生回路9でなる
ループは負帰還をなすように構成され、APDIに人力
される光信号のレベルの変化あるいは外部温度変化によ
るAPDIの特性変化にもかかわらず、増幅器2の出力
のパルス振幅を一定に保つ手段であり、自動利得制御回
路(以下、AGC回路という。)と呼ばれる。増幅器2
の出力は分岐されてクロック抽出回路11に導かれる。
As shown in FIG. 2, the conventional example includes an avalanche photodiode (hereinafter referred to as APD) 1, an amplifier 2,
Detector 3, low-pass filter 6, reference voltage source 7, comparator 8, bias generation circuit 9, discriminator 10, clock extractor 11, clock disconnection detector 12, and inhibition circuit 13
, a data signal output terminal 14 , and a clock signal output terminal 15 . The pulse-modulated optical signal input to APDl is converted into a current proportional to the multiplication factor determined by the output voltage of bias generation circuit 9 while passing through APDl, and is sent to amplifier 2. Amplifier 2 amplifies the output current of APDI to a level that allows detection, and sends it to detector 3. The detector 3 performs peak detection on the data signal output from the amplifier 2 and sends it to the low-pass filter 6 . A low-pass filter 6 smoothes the output of the detector 3 and sends it to a comparator 8. Comparator 8 compares and amplifies the output of reference voltage source 7 and the output of low-pass filter 6, and sends an error output to bias generation circuit 9. The bias generation circuit 9 has an output voltage of the comparator 8.
It supplies bias to APDl. A loop consisting of the APDI, amplifier 2, detector 3, low-pass filter 6, reference voltage R7, comparator 8, and bias generation circuit 9 is configured to provide negative feedback, and the level of the optical signal input to the APDI is This is a means for keeping the pulse amplitude of the output of the amplifier 2 constant despite changes in the characteristics of APDI due to changes in the external temperature or changes in external temperature, and is called an automatic gain control circuit (hereinafter referred to as an AGC circuit). amplifier 2
The output is branched and guided to the clock extraction circuit 11.

クロック抽出回路11は増幅器2の出力からデータ信号
のクロック信号成分を抽出し、識別器10ヘクロック信
号を送出する。識別器10は増幅器2の出力信号をクロ
ック抽出器11から供給されるクロック信号に基づき識
別する。識別器10の出力の識別再生されたデータ信号
は禁止回路13を経由してデータ信号出力端子14へ出
力される。同様にクロック抽出器11の出力も禁止回路
13を経由してクロック信号出力端子15へ出力される
。クロック断検出回路12はクロック抽出器11の分岐
された出力の一部が入力され、クロックレベルの断検出
を行い、断になった場合にクロック禁止回路13に信号
を送出して禁止回路13で識別器10およびクロック抽
出器11から送出されたデータ信号およびクロック信号
を禁止し、データ信号出力端子14とクロック信号出力
端子15とに無意味な信号が送出されることを防止する
The clock extraction circuit 11 extracts the clock signal component of the data signal from the output of the amplifier 2, and sends the clock signal to the discriminator 10. The discriminator 10 discriminates the output signal of the amplifier 2 based on the clock signal supplied from the clock extractor 11. The reproduced data signal output from the discriminator 10 is outputted to the data signal output terminal 14 via the inhibit circuit 13. Similarly, the output of the clock extractor 11 is also output to the clock signal output terminal 15 via the inhibition circuit 13. The clock interruption detection circuit 12 receives a part of the branched output of the clock extractor 11, detects the interruption of the clock level, and sends a signal to the clock prohibition circuit 13 when the clock level is disconnected. The data signal and clock signal sent from the discriminator 10 and the clock extractor 11 are inhibited to prevent meaningless signals from being sent to the data signal output terminal 14 and the clock signal output terminal 15.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

このような従来の光受信器のAGC回路は、APDIへ
の光信号入力が断もしくは極めて小さくなったときでも
低域ろ波器6の出力レベルが基準電圧源7の電圧に等し
くなるように動作するので、APDIの暗電流による雑
音成分あるいはAPDlがブレークダウン時に発生する
マイクロプラズマ雑音成分などを増幅して得られる増幅
器2の出力すなわち雑音レベルが大きくなり、増幅器2
の出力からクロック成分を抽出するクロック抽出器11
の出力にも増幅器2の出力の雑音のうちクロック周波数
の成分に応じたクロック成分が発生し、クロック断検出
器12でのクロック断検出ひいては禁止回路13での無
意味なデータ信号あるいはクロック信号の禁止が安定に
行えない欠点があった。
The AGC circuit of such a conventional optical receiver operates so that the output level of the low-pass filter 6 is equal to the voltage of the reference voltage source 7 even when the optical signal input to the APDI is cut off or becomes extremely small. Therefore, the output of the amplifier 2 obtained by amplifying the noise component due to the dark current of APDI or the microplasma noise component generated when APD1 breaks down, that is, the noise level, increases, and the noise level of the amplifier 2 increases.
A clock extractor 11 that extracts a clock component from the output of
Also, a clock component corresponding to the clock frequency component of the output noise of the amplifier 2 is generated in the output of the amplifier 2, and the clock disconnection detector 12 detects a clock disconnection, and the inhibition circuit 13 detects a meaningless data signal or a clock signal. There was a drawback that prohibition could not be performed stably.

本発明はこのような欠点を除去するもので、雑音レベル
による影響を抑制することができる自動利得制御回路を
提供することを目的とする。
The present invention aims to eliminate such drawbacks and provides an automatic gain control circuit that can suppress the influence of noise levels.

〔問題点を解決するための手段〕[Means for solving problems]

本発明は、パルス列であるデータ信号で強度変調された
光信号を電気信号に変換する光電気変換手段およびこの
光電気変換手段で生成された電気信号を復調増幅する復
調増幅手段を有する光受信器に接続され、この復調増幅
手段で生成された電気信号に含まれるデータ信号を検波
するデータ信号検波手段と、この検波手段の出力のレベ
ルと基準電圧のレベルとを比較して自回路の利得制御信
号に相当の信号を生成する比較器と、この比較器の出力
に基づき上記光電気変換手段の出力レベルを所定範囲内
のレベルに保つバイアス発生回路とを備えた自動利得制
御回路において、上記復調増幅手段で生成された電気信
号に含まれるデータ信号の占有する帯域外の成分を検波
する雑音検波手段と、上記データ信号検波手段が生成す
る信号とこの雑音検波手段が生成する信号との和の信号
を生成し上記比較器の入力とする加算器とを備えたこと
を特徴とする。
The present invention provides an optical receiver having opto-electric conversion means for converting an optical signal intensity-modulated with a data signal, which is a pulse train, into an electrical signal, and demodulation amplification means for demodulating and amplifying the electrical signal generated by the opto-electric conversion means. A data signal detection means is connected to the demodulation and amplification means to detect the data signal included in the electrical signal generated by the demodulation and amplification means, and the gain control of the own circuit is performed by comparing the level of the output of this detection means and the level of the reference voltage. In the automatic gain control circuit, the automatic gain control circuit includes a comparator that generates a signal equivalent to the signal, and a bias generation circuit that maintains the output level of the photoelectric conversion means within a predetermined range based on the output of the comparator. noise detection means for detecting components outside the band occupied by the data signal included in the electrical signal generated by the amplification means; and a sum of the signal generated by the data signal detection means and the signal generated by the noise detection means. The present invention is characterized by comprising an adder that generates a signal and inputs the signal to the comparator.

〔作用〕[Effect]

光信号を復調増幅して得られた電気信号のうちデータ信
号のピーク値とデータ信号の占有する帯域外の低周波成
分とのそれぞれを検波して得られた値との和をとる。こ
の和出力を基準電圧と比較増幅して得られた誤差出力を
自動利得制御回路の利得制御信号とする。
The sum of the peak value of the data signal and the value obtained by detecting each of the low frequency components outside the band occupied by the data signal in the electrical signal obtained by demodulating and amplifying the optical signal is calculated. This sum output is compared and amplified with a reference voltage, and the resulting error output is used as a gain control signal for the automatic gain control circuit.

〔実施例〕〔Example〕

以下、本発明の一実施例を図面に基づき説明する。第1
図はこの実施例の構成を示すブロック構成図である。第
1図で第2図と番号が同じ構成要素は同じ動作を行う構
成要素である。
Hereinafter, one embodiment of the present invention will be described based on the drawings. 1st
The figure is a block configuration diagram showing the configuration of this embodiment. Components having the same numbers in FIG. 1 as in FIG. 2 are components that perform the same operations.

この実施例は、従来例の構成要素の他に低域ろ波器4と
、検波器5と、加算器16とを備える。すなわち、この
実施例は、第1図に示すように、パルス列であるデータ
信号で強度変調された光信号を電気信号に変換する光電
気変換手段であるAPDlおよびこの光電気変換手段で
生成された電気信号を復調増幅する復調増幅手段である
増幅器2を有する光受信器に接続され、この復調増幅手
段で生成された電気信号に含まれるデータ信号を検波す
るデータ信号検波手段である検波器3と、利得制御信号
に基づき上記光電気変換手段の出力レベルを所定範囲内
のレベルに保つバイアス発生回路9と、上記復調増幅手
段で生成された電気信号に含まれ、この電気信号に含ま
れるデータ信号の占有する帯域外の成分を検波する雑音
検波手段である低域ろ波器4および検波器5と、上記デ
ータ信号検波手段が生成する信号とこの雑音検波手段が
生成する信号との和の信号を生成する加算器16と、こ
の加算器16で生成された信号のレベルと基準電圧のレ
ベルと比較して自回路の利得制御信号に相当の信号を生
成する比較器8とを備える。
This embodiment includes a low-pass filter 4, a detector 5, and an adder 16 in addition to the conventional components. That is, as shown in FIG. 1, this embodiment uses an APDl which is a photoelectric conversion means for converting an optical signal intensity-modulated with a data signal, which is a pulse train, into an electric signal, and a signal generated by this photoelectric conversion means. A detector 3 is connected to an optical receiver having an amplifier 2 which is demodulation and amplification means for demodulating and amplifying an electrical signal, and is a data signal detection means for detecting a data signal included in the electrical signal generated by the demodulation and amplification means. , a bias generation circuit 9 that maintains the output level of the opto-electric conversion means within a predetermined range based on a gain control signal, and a data signal included in the electric signal generated by the demodulation and amplification means. A signal that is the sum of the signal generated by the data signal detection means and the signal generated by this noise detection means; The comparator 8 compares the level of the signal generated by the adder 16 with the level of a reference voltage to generate a signal corresponding to the gain control signal of its own circuit.

次に、この実施例の動作を説明する。Next, the operation of this embodiment will be explained.

増幅器2の出力は検波器3でパルス波形のピーク検波が
行われる一方、低域ろ波器4で増幅器2の出力に存在す
る信号のうちデータ信号の帯域外の低周波成分が抜出さ
れ、検波器5で検波されて加算器16へ送出される。加
算器16は検波器3と検波器5の出力とを加算して低域
ろ波器6へ送出し、低域ろ波器6は加算器16の出力を
平滑化して比較器8へ送出する。比較器8は基準電圧源
7の出力と低域ろ波器6の出力とを比較増幅し、バイア
ス発生回路9を制御する。APDI、増幅器2、検波器
3、加算器16、低域ろ波器4、検波器5、低域ろ波器
6、基準電圧源7、比較器8およびバイアス発生回路9
で構成されるループは第2図の従来例と同じ<AGCル
ープをなすように構成され、APDIへの光入力信号レ
ベルが正常なときは、増幅器2の出力に現れるデータ信
号帯域外の成分はデータ信号に比べて小さいので、検波
器3の出力レベルに比べて検波器5の出力レベルは無視
しうる程度に小さくなり、したがって、ループは第2図
に示す従来例とほぼ同じ動作を行う。しかし、APDI
への光信号入力が断または極めて小さい場合は、APD
lの暗電流による雑音またはマイクロプラズマ雑音は増
幅器2で増幅されるので、APDIの暗電流による雑音
が主に白色雑音であることおよびマイクロプラズマ雑音
の低周波成分が大きいことを考慮するとAPDlへの光
信号人力レベルが正常な場合に比べて検波器3の出力レ
ベルに対する検波器5の出力レベルの比は大きくなり、
したがって、増幅器2の出力に現れる雑音のクロック信
号レベルは第2図に示す従来例に比べて小さくなり、増
幅器2の出力のうちクロック信号成分を抽出するクロッ
ク抽出器11の出力レベルも小さくなるので、クロック
断検出器12でのクロック断の判定も安定に行え、結果
的に禁止回路13での無意味なデータ信号やクロック信
号の禁止が効果的に行える。
The output of the amplifier 2 is subjected to peak detection of the pulse waveform by a detector 3, while a low frequency component outside the band of the data signal is extracted from the signal present at the output of the amplifier 2 by a low-pass filter 4. The signal is detected by the detector 5 and sent to the adder 16. The adder 16 adds the outputs of the detectors 3 and 5 and sends it to the low-pass filter 6, and the low-pass filter 6 smoothes the output of the adder 16 and sends it to the comparator 8. . Comparator 8 compares and amplifies the output of reference voltage source 7 and the output of low-pass filter 6, and controls bias generation circuit 9. APDI, amplifier 2, detector 3, adder 16, low-pass filter 4, detector 5, low-pass filter 6, reference voltage source 7, comparator 8, and bias generation circuit 9
The loop is configured to form the same <AGC loop as in the conventional example shown in Fig. 2, and when the optical input signal level to APDI is normal, the components outside the data signal band appearing at the output of amplifier 2 Since it is small compared to the data signal, the output level of the detector 5 is negligibly small compared to the output level of the detector 3, and therefore the loop performs almost the same operation as the conventional example shown in FIG. However, APDI
If the optical signal input to the APD is disconnected or extremely weak,
The noise or microplasma noise due to the dark current of l is amplified by the amplifier 2, so considering that the noise due to the dark current of APDI is mainly white noise and the low frequency component of microplasma noise is large, the noise to APDl is amplified. Compared to the case where the optical signal power level is normal, the ratio of the output level of the detector 5 to the output level of the detector 3 becomes larger,
Therefore, the clock signal level of the noise appearing in the output of amplifier 2 is smaller than that in the conventional example shown in FIG. 2, and the output level of clock extractor 11, which extracts the clock signal component from the output of amplifier 2, is also smaller. The clock interruption detector 12 can stably determine whether the clock is disconnected, and as a result, the prohibition circuit 13 can effectively inhibit meaningless data signals and clock signals.

〔発明の効果〕〔Effect of the invention〕

本発明は、以上説明したように、光入力信号が断または
極めて小さいときに復調出力に含まれるクロツタ周波数
成分を小さくすることができるので、クロック断検出を
容易にし、また、先人力信号が断または極めて小さいと
きに無意味なデータ信号やクロック信号が光受信器から
出力されることをクロック断検出器の出力で安定に禁止
することができる効果がある。
As explained above, the present invention makes it possible to reduce the clock frequency component included in the demodulated output when the optical input signal is cut off or extremely small, making it easier to detect the clock cut-off, and also to detect the cut-off of the signal when the optical input signal is cut off or extremely small. Alternatively, there is an effect that the output of the clock disconnection detector can stably prevent meaningless data signals and clock signals from being output from the optical receiver when the signal is extremely small.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明実施例の構成を示すブロック構成図。 第2図は従来例の構成を示すブロック構成図。 1・・・アバランシェフォトダイオード、2・・・増幅
器、3.5・・・検波器、4.6・・・低域ろ波器、7
・・・基準電圧源、8・・・比較器、9・・・バイアス
発生回路、10・・・識別器、11・・・クロック抽出
器、12・・・クロック断検出器、13・・・禁止回路
、14・・・データ信号出力端子、15・・・クロック
信号出力端子、16・・・加算器。 特許出願人 日本電気株式会社、、、V、−>、、代理
人  弁理士 井 出 直 孝
FIG. 1 is a block configuration diagram showing the configuration of an embodiment of the present invention. FIG. 2 is a block configuration diagram showing the configuration of a conventional example. 1... Avalanche photodiode, 2... Amplifier, 3.5... Detector, 4.6... Low-pass filter, 7
. . . Reference voltage source, 8 . Comparator, 9 . Bias generation circuit, 10 . Inhibition circuit, 14...Data signal output terminal, 15...Clock signal output terminal, 16...Adder. Patent applicant: NEC Corporation, V, ->, Agent: Naotaka Ide, patent attorney

Claims (1)

【特許請求の範囲】 1、パルス列であるデータ信号で強度変調された光信号
を電気信号に変換する光電気変換手段(1)およびこの
光電気変換手段で生成された電気信号を復調増幅する復
調増幅手段(2)を有する光受信器に接続され、 この復調増幅手段で生成された電気信号に含まれるデー
タ信号を検波するデータ信号検波手段(3)と、この検
波手段の出力のレベルと基準電圧のレベルとを比較して
自回路の利得制御信号に相当の信号を生成する比較器と
、この比較器の出力に基づき上記光電気変換手段の出力
レベルを所定範囲内のレベルに保つバイアス発生回路(
9)とを備えた自動利得制御回路において、 上記復調増幅手段で生成された電気信号に含まれるデー
タ信号の占有する帯域外の成分を検波する雑音検波手段
(4、5)と、 上記データ信号検波手段(3)が生成する信号とこの雑
音検波手段(4、5)が生成する信号との和の信号を生
成し上記比較器の入力とする加算器(16)と を備えたことを特徴とする自動利得制御回路。
[Claims] 1. Opto-electric conversion means (1) that converts an optical signal intensity-modulated with a data signal, which is a pulse train, into an electrical signal, and demodulation that demodulates and amplifies the electrical signal generated by this opto-electric conversion means. A data signal detection means (3) connected to an optical receiver having an amplification means (2) and detecting a data signal included in an electrical signal generated by the demodulation and amplification means, and a level and standard of the output of this detection means. a comparator that generates a signal equivalent to the gain control signal of its own circuit by comparing the level of the voltage; and a bias generator that maintains the output level of the photoelectric conversion means within a predetermined range based on the output of this comparator. circuit(
9) an automatic gain control circuit comprising: noise detection means (4, 5) for detecting components outside the band occupied by the data signal included in the electrical signal generated by the demodulation and amplification means; and the data signal It is characterized by comprising an adder (16) that generates a signal that is the sum of the signal generated by the detection means (3) and the signal generated by the noise detection means (4, 5) and inputs the signal to the comparator. automatic gain control circuit.
JP63116203A 1988-05-13 1988-05-13 Automatic gain control circuit Expired - Lifetime JPH0636503B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63116203A JPH0636503B2 (en) 1988-05-13 1988-05-13 Automatic gain control circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63116203A JPH0636503B2 (en) 1988-05-13 1988-05-13 Automatic gain control circuit

Publications (2)

Publication Number Publication Date
JPH01286654A true JPH01286654A (en) 1989-11-17
JPH0636503B2 JPH0636503B2 (en) 1994-05-11

Family

ID=14681390

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63116203A Expired - Lifetime JPH0636503B2 (en) 1988-05-13 1988-05-13 Automatic gain control circuit

Country Status (1)

Country Link
JP (1) JPH0636503B2 (en)

Also Published As

Publication number Publication date
JPH0636503B2 (en) 1994-05-11

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