JPH0128422B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to improvements in electronic translation machines and voice input/output devices, and particularly relates to an electronic translation device characterized in that input and output signal levels are correlated. .

In this specification, translation refers to (1) converting the language of one country into the language of another country, (2) mutual conversion between a standard language and a dialect, even if the language is within the same country, or converting abbreviations and original texts. mutual conversion between words (words, symbols, marks, terms, etc.) and their explanations, (3) operations (general calculations and “pi”)
(to obtain the numerical value "3.14...").

The source language refers to the language, numbers, formulas, etc. before translation, and the translated language refers to the language, numbers, formulas, etc. after translation. For example, in an electronic translation device set to translate Japanese into English, "Good Morning" is the original language, and "Good Morning" is the translated language.

The electronic translation device already proposed by the present inventor in Japanese Patent Application Laid-Open No. 103765/1983 is shown in Figs. 1 and 2A.
As shown in ~D, the audio signal of the original language from the microphone 1 is amplified to a level that allows speech recognition by the input amplifier 2, and then is subjected to spectrum analysis and speech recognition by the audio analysis circuit 3, and is converted into characters of the original language. It is converted into a signal and enters the electronic translation circuit 4. Further, the original language applied to the electronic translation circuit 4 is displayed in characters by the character display circuit 8, and when the translation is completed, the translated language is displayed.

After being translated by the electronic translation circuit 4, the character signal of the translated language is output from the electronic translation circuit 4 to the speech synthesis circuit 5.
after being converted into an audio signal in the translated language.
The signal is amplified by the output amplifier 6 and then sent to the speaker 7. The speaker 7 converts the translated language into speech and pronounces it. 2A-2D show the relative characteristics of input and output levels. Even when the input level of the audio signal applied to the microphone 1 is small as shown in FIG. 1A, the output signal level of the translated language output from the speaker 7 becomes relatively high as shown in FIG. Even when the input level is high as shown in Figure C, the output level is relatively small as shown in Figure D. That is, these signal levels a,
b, c, and d have the following relationships: a≪b, c≫d, b≒d (approximately constant), and ∴ a≪b≒d≪c. This shows that the audio output of the speaker 7 is almost constant regardless of the level of the input signal of the microphone 1. In this way, with respect to the audio input/output signal level, the front stage (microphone 1, input amplifier 2, voice analysis circuit 3) and the rear stage (speech synthesis circuit 5, output amplifier 6, speaker 7) are connected with the electronic translation circuit 4 as a boundary. ) had nothing to do with it. Therefore, since the level adjustment of the audio output from the speaker 7 cannot be controlled by the magnitude of the audio applied to the microphone 1, the output amplifier 6
Volume adjustment volume (not shown) provided in
I had to make adjustments.

Therefore, (1) when the surroundings are quiet, if you do not adjust the volume appropriately, the translated language will be pronounced loudly from speaker 7 even though you are speaking in a low voice, and the people around you will hear the translated language. is often surprising. (2) On the other hand, if the volume adjustment is not properly adjusted when the surroundings are noisy, the speaker may be saying the original language loudly into microphone 1, but the sound will only come out in a low voice from speaker 7. It was inconvenient that the other party couldn't hear me at all and I had to repeat it over and over again. Furthermore, when such an electronic translation device is used for radio or telephone, it has the disadvantage that although it can translate, the speaking style is monotonous and the nuance of the speech cannot be sufficiently conveyed.

The present invention eliminates such drawbacks and also
The present invention provides an electronic translator and a voice input/output device that are effective and highly practical.

The configuration of the present invention will be explained below. The electronic translation device of the present invention connects the source language input circuit section to the translated language output circuit section with variable gain via the electronic translation circuit section, detects the input signal level of the source language, and connects the input circuit section of the source language to the output circuit section with variable gain of the translated language via the electronic translation circuit section. By connecting to the output circuit section an output level control section that adjusts the gain of the output circuit section according to the input signal level of the source language while the output signal of the translated language corresponding to the source language is being sent out. , an electronic translation device that correlates input and output signal levels.

Next, one embodiment of the present invention will be described using FIGS. 3 to 8.

FIG. 3 is an electric circuit diagram of an electronic translation device according to an embodiment of the present invention, FIG. Figure 5 is a characteristic diagram showing the relationship between the input and output waveforms of the minimum hold circuit of the same device, Figure 6 is an electric circuit diagram showing a specific example of the reset circuit of the same device, and Figure 7 is the timing of the output of each part of the circuit. The chart diagram in FIG. 8 is a level characteristic diagram showing the relative level relationship between the input and output signal levels of the same device.

In the figure, 1 is a microphone connected to a voice analysis circuit 3 via an input amplifier 2. The speech analysis circuit is a circuit that performs spectrum analysis on a speech input signal, performs speech recognition, and converts the speech input signal into a character signal corresponding to the speech input signal. The speech analysis circuit 3 is connected to an electronic translation circuit 4 which translates the source language into a translation language. The electronic translation circuit 4 is connected to a character display circuit 8 and a speech synthesis circuit 5. A speech synthesis circuit is a circuit that converts character signals into speech signals.Speech synthesis methods include formant synthesis,
Three types of methods have been put into practical use: linear predictive coding (LPC) and waveform digitization/compression. In this example, Parcor, which has stable synthesis characteristics, is used among the linear predictive coding (LPC) methods.
The method was used in the speech synthesis circuit 5. Next, the voice synthesis circuit 5 is connected to the speaker 7 via a voltage control amplifier (hereinafter referred to as VCA) 9 whose gain can be controlled by voltage. Further, the output side of the input amplifier 2 is connected to the voice analysis circuit 3 as described above, and is also connected to the VCA 9 via the negative voltage minimum hold circuit 10. A reset circuit 11 for operating the reset switch S2 of the minimum hold circuit 10 is connected to the output side of the speech synthesis circuit 5. In this way, the electronic translation device of this example was constructed.

Here, the VCA 9 used in this example will be explained in detail. Operational Amplifier
A bias resistor 92, one end of which is grounded, is connected to the non-inverting input terminal of the OP amplifier (hereinafter simply referred to as OP amplifier) 91, and the inverting input terminal is connected to the output terminal of the OP amplifier 91 via a feedback resistor 97. At the same time, the inverting input terminal was connected to the drain of a field effect transistor (hereinafter referred to as FET) 96 and the other end of a capacitor 93 of a series connection body of a capacitor 93 and a resistor 94 for improving control characteristics. Further, the other end of the resistor 94 was connected to the resistor 95 and the gate of the FET 96, and the source of the FET 96 was grounded.

The operation of the VCA 9 configured in this way will be explained using FIG. 4. FIG. 4 is a characteristic diagram showing the relationship between control DC voltage and gain of the VCA 9. When a large negative DC voltage is applied to the resistor 95, which serves as the input terminal for applying the control DC voltage, the resistance between the drain and source of the FET 96 increases, and the
Since the amount of feedback fed back to the inverting input terminal of OP amplifier 91 increases, the gain of OP amplifier 91 decreases. Conversely, when a small negative DC voltage is applied to the resistor 95, the resistance between the drain and source of the FET 96 decreases, so the amount of feedback fed back to the inverting input terminal of the OP amplifier 91 decreases, and the OP amplifier The gain of 91 increases as a result. In this way, as shown in Fig. 4, the amount of feedback is adjusted by controlling the resistance value between the drain and source of the FET 96 by the voltage applied to the gate, and as a result, the amount of feedback is adjusted according to the control DC voltage applied. The gain of the OP amplifier 91 can be controlled.

Next, the minimum hold circuit 10 will be explained using FIG. 5. FIGS. 5A to 5C are characteristic diagrams showing the relationship between input and output waveforms of the minimum hold circuit 10.

A DC blocking capacitor 105 and the negative electrode of a bias battery 106 (BbV) whose positive electrode was grounded were connected to the non-inverting input terminal of the OP amplifier 102. Connect the output terminal of OP amplifier 102 to diode 1
03 to the non-inverting input terminal of the OP amplifier 101, and the output terminal of the OP amplifier 101 to the OP amplifier 101.
It was connected to the inverting input terminals of amplifier 101 and OP amplifier 102. A non-inverting input terminal of the OP amplifier 101 was connected to a capacitor 104, a contact point of a reset switch S2, and a contact point of a non-lock type switch S3 interlocked with a power switch (not shown) of the device. Further, the other terminal of the capacitor 104 was grounded, and both the movable contact piece of the switch S3 and the movable contact piece of the reset switch S2 were grounded via the battery 107.

In this way, the minimum hold circuit 10 was constructed. Next, explanation will be given using FIG. 5 A to C.
Figure 5 A to C are characteristic diagrams of the same circuit, where A shows the input signal to the capacitor 105 and b shows the OP
The same signal applied to the non-inverting input terminal of the amplifier 102 is shown in FIG.

When the power switch of the device is turned on, the non-locking switch S3 is turned on for a short time, so that the capacitor 104 is charged to a voltage corresponding to the voltage of the battery 107. In this embodiment, a 15V battery was used for the battery 107 due to the relationship with the VCA 9, and the capacitor 104 was charged to -15V. This voltage is fed back through the voltage follower of OP amp 101 to the inverting input terminal of OP amp 102. Now, when an input signal as shown in Figure 5A is applied to the capacitor 105, the same signal biased to -BbV by the battery 106 is applied to the non-inverting input terminal of the OP amplifier 102 as shown in Figure 5B. Ru. When the voltage of this signal is higher than the above-mentioned feedback voltage (initially -15V) (voltage close to 0V), the output of the OP amplifier 102 is at a voltage higher than the capacitor 104, that is, the voltage of the capacitor 104 is the reference voltage. If so, a positive voltage will be generated. Therefore, diode 103
is in the forward direction, and the capacitor 104 is charged with positive charge. When charging progresses and the voltage of the capacitor 104 exceeds the input voltage, the OP amplifier 102 is inverted and the output becomes a negative voltage, so the diode 103 becomes reverse biased and the capacitor 104
The charging of the positive charge stops. In this way, the negative voltage can be held to a minimum as shown in FIG.

In addition, in order to improve the hold time constant,
It is necessary to pay sufficient attention to leakage from the capacitor 104, reverse leakage from the diode 103, and input leakage from the OP amplifier 101. In this example, especially OP
Amplifier 101 is a FET input type OP amplifier manufactured by Tokyo Shibaura Electric Co., Ltd., product number TA7507M, and a film capacitor with high insulation resistance is used for the capacitor to improve the hold characteristics.

Next, the reset switch S2 is turned on to discharge the positive charge stored in the capacitor 104,
You can charge it to -15V and return it to its original state. In this way,
OP amplifier 10 is connected to the output terminal of OP amplifier 101.
The highest voltage among the signals applied to the two non-inverting input terminals is sent out. Here, the reason why the negative voltage is held to a minimum is to apply a negative voltage to the gate of the FET 96 of the VCA 9. FET9
6 can be considered as a type of variable resistor controlled by the minimum hold circuit 10 because the resistance value between the source and drain of the FET 96 can be changed by the voltage applied to the gate.

Next, the reset circuit 11 will be explained.

As shown in FIG. 3, the reset circuit 11 connects the trigger input terminal of a bistable multivibrator (hereinafter referred to as bistable multi) 111 to the output of the speech synthesis circuit 5 via a switch S1 and generates a trigger pulse. The output of the bistable multi 111 is selectively connected to the first trigger circuit 112 that generates a trigger pulse, or the second trigger circuit 113 that generates a trigger pulse when the output of the speech synthesis circuit 5 continues for a predetermined period or more without a signal. The terminal is connected to a relay (correctly speaking, a solenoid part of a relay-type switch, but simply referred to as a relay in this specification) 115 that drives switches S1 and S4, and a monostable multivibrator (hereinafter referred to as a monostable multivibrator). )11
4 trigger input terminal via switch S4,
Connected to the second trigger circuit 113. Further, the output terminal of the monostable multi 114 is connected to a relay 116 that drives the reset switch S2. Here, switches S1 and S4
are interlocked with each other, and are normally electrically connected to contacts a and c, respectively. Further, the switch S2 is normally in an open state. Next, the operation of the reset circuit 11 constructed in this manner will be explained. When the output signal is sent from the speech synthesis circuit 5, the first trigger circuit 112
generates a trigger pulse, and the trigger pulse is
The voltage is applied to the bistable multi 111 via the switch S1 which is electrically connected to the contact a. This trigger pulse causes the bistable multi 111, which had been in the first stable state, to change to the second stable state and causes current to flow through the relay 115. This causes relay 115 to operate,
Switches S1 and S4 are made conductive to contacts b and d, respectively, and maintained in that state.

Next, the output signal from the speech synthesis circuit 5 ends, and the no-signal state remains for a predetermined period of time (approximately 1 in this embodiment).
seconds), the second trigger circuit 113 generates a trigger pulse, and the trigger pulse is transmitted to the bistable multi 11
1, and at the same time, it is applied to the monostable multi 114 via switch S4, which conducts to contact d. As a result, the bistable multi 111 returns from the second stable state to the original first stable state. Therefore, the supply of current to relay 115 is stopped and switch S
1 and S4 return to contacts a and c, respectively, and conduct. On the other hand, the monostable multi 114 uses the trigger pulse of the second trigger circuit 113 to charge the charging capacitor 1 of the minimum hold circuit 10.
Current is briefly supplied to relay 116 to cause reset switch S2 to conduct for a time sufficient to discharge the charge on relay 116.

Thereafter, the minimum hold circuit 10 is reset by repeating the same operation.

Further, the reset circuit 11 will be explained in more detail with reference to FIGS. 6 and 7.

FIG. 6 is an electric circuit diagram showing a specific example of the reset circuit 11, and FIG. 7 is a timing chart of the outputs of each part of the circuit 11.

The first trigger circuit 112 was constructed by connecting a diode to a Schmitt trigger circuit via a differential circuit. Therefore, for example, when a sine wave signal is applied to the input terminal 117, Schmitt
The trigger circuit sends a square wave to the check point 112a, the differential circuit sends both positive and negative trigger pulse waves to the check point 112b, and the diode sends a positive pulse wave to the contact a of the switch S1. Trigger pulse waves are output respectively. Second trigger circuit 113
The DC blocking capacitor 41 is connected to the no-signal time-DC voltage conversion circuit via the base clip circuit.
It was configured by connecting.

In the figure, 31 is a DC blocking capacitor connected via a resistor 32 to the base of a grounded emitter type transistor 33 for performing a switching operation. The collector of the transistor 33 is connected to the +B power supply via a resistor 40, grounded via a charging capacitor 34, and connected to a diode 36 via a resistor 35.
The diode 36 is grounded via a battery 37, and the connection point between the resistor 35 and the diode 36 is connected to a DC blocking capacitor 38 and a monostable multi-layer 114.
It is connected to the contact b of the switch S1 via a diode 39 for preventing mutual interference with the bistable multi 111, and to the contact d of the switch S4 via a DC blocking capacitor 41. By configuring the second trigger circuit 113 in this way, for example, when a sine wave signal is applied to the input terminal 117, the transistor 33 will respond according to the frequency.
To turn on and off and perform switching operations,
The capacitor 34 is only repeatedly charged and discharged for a short period of time, and is not charged to the extent that it operates the base clip circuit in the next stage. However, since a bias voltage is applied to the base of the transistor 33 so that the transistor 33 is in the OFF state when there is no signal, if the no signal state continues, the capacitor 33
4 is charged through the resistor 40 until it becomes equal to the +B voltage, so check point 11
At 3a, an output voltage appears that increases with a time constant approximately determined by resistor 40 and capacitor 34. As a result of this charging, when the resulting voltage of the capacitor 34 becomes higher than the voltage of the battery 37, the base clip circuit is activated and an output of the base clip waveform appears at the check point 113b. Further, this output is sent to the contact point d via the capacitor 41 as a trigger pulse wave without a DC component.

Further, the movable contact piece of the switch S1 is connected to the trigger input terminal of the bistable multi 111, and the relay 115 is connected to the same output terminal. The movable contact piece of the switch S4 is connected to the trigger input terminal of the monostable multi 114, and the output terminal of the same is connected to the trigger input terminal of the monostable multi 114.
6. In addition, switches S1 and S4
is interlocked with relay 115.

The operation of the reset circuit 11 constructed in this way will be explained in detail with reference to FIG. FIGS. 7A to 7D are timing charts of the outputs of each part of the circuit 11.

As shown in FIG. 7A, when the audio input signal "Anatawada redesuka" is applied to the input terminal 117, the waveform is shaped by the Schmitt trigger circuit, the differentiation circuit, and the diode of the first trigger circuit 112. A trigger pulse as shown in FIG. 4B is sent to contact a of the switch S1. This trigger pulse is transmitted to the bistable multi 111 via switch S1.
The bistable multi 111 is changed from the first stable state to the second stable state as shown in FIG. This activates relay 115, causing switches S1 and S4 to conduct to contacts b and d. The voice input signal "Ana Tawa Daredesuka" consists of "Anatawa" and "Dare Desuka", and there is a no-signal time of about 0.1 to 0.25 seconds between "Anatawa" and "Dare Desuka" in normal conversation, so charging is not possible. Since the capacitor 34 is continuously charged during that time, check point 1 of the second trigger circuit 113
As shown in FIG. 13C, a slight increase in voltage is observed in 13a. However, since the specified voltage determined by the battery 37 of the base clip circuit is not reached, check point 11 is reached.
No change appears in 3b as shown in d of the figure.
Therefore, the output of the second trigger circuit 113 does not appear as shown in FIG. 7E. Next, “Daredesca”
When the audio input signal is applied, the electric charge in the capacitor 34 is discharged and returns to the original state, but after the application of the audio input signal of "Daredesuka", the no-signal input state continues for a while, so the capacitor 34 is discharged in about 1 second. 34, the voltage at check point 113a reaches the specified voltage. Therefore, the second trigger circuit 113 generates a trigger pulse as shown in FIG. This trigger pulse is sent to the bistable multi 111 via the switch S1, and is also sent to the bistable multi 111 via the switch S4.
It is also sent to the monostable multi 114 via. As a result, the bistable multi 111 returns to the first stable state as shown in FIG. Further, in accordance with this, the operation of the relay 115 is stopped and the switch S1
and S4 conduct to the contacts a and c, respectively, and return to the original state again. On the other hand, monostable multi 1
14 generates an output pulse as shown in G in the figure by applying this trigger pulse, and relay 116
is driven for a short period of time (time equivalent to the output pulse width) and immediately returns to its original state. Therefore, for this short period of time, relay 116 conducts reset switch S2, and minimum hold circuit 1
Reset to 0.

Next, the audio input signal "Watashiwatomdesu" is applied, but this audio input signal "Watashiwatomdesu" also consists of "Watashiwa" and "Tomdess", and the difference between the two is about 0.15. From about
A no-signal state of 0.3 seconds occurs during normal conversation, but in this amount of no-signal time, the second trigger circuit 11
No trigger pulse is generated from 3 onwards. Furthermore, as shown in FIGS. 7A to 7B, each part operates in the same manner and sends out the same output in response to this audio input signal.
In addition, the above no-signal time is about 0.15 seconds to about 0.3 seconds,
Furthermore, the reason for the range of 0.1 to 0.25 seconds in the above description is due to individual differences among speakers.

Next, the operation of the electronic translation device of this embodiment will be explained using FIGS. 8E to 8H.

FIGS. 8E to 8H are level characteristic diagrams showing the relative relationship between input and output signal levels of the same device.

The audio signal of the original language applied to the microphone 1 is amplified by the input amplifier 2 to a level at which speech can be recognized, and then sent to the audio analysis circuit 3 and the minimum hold circuit 10. Of these, voice analysis circuit 3
The voice signal applied to is converted into a character signal of the original language by a voice analysis circuit, and then sent to an electronic translation circuit 4. The electronic translation circuit 4 translates the applied character signal of the original language into a character signal of the translated language and sends it to the speech synthesis circuit 5. The speech synthesis circuit 5 converts the character signal of the translation language into the speech signal of the translation language.
Send to VCA9.

On the other hand, the minimum hold circuit 10 detects the highest level, so to speak, the peak value of the applied original language audio signal, holds that value in a state suitable for controlling the VCA 9, and
A DC voltage corresponding to the audio input signal is applied to the gain control terminal (resistance 95) of the VCA 9, and the gain of the VCA 9 is controlled according to the peak value of the audio input signal of the original language.

Therefore, the VCA 9 amplifies the translated language audio signal applied from the speech synthesis circuit 5 with a gain corresponding to the audio input signal level of the source language corresponding to the translated language. This output causes the speaker 7 to pronounce speech in the translated language. After the speech synthesis circuit 5 finishes transmitting the speech signal of the translated language, approximately 1
After seconds have elapsed, the monostable multi 114 of the reset circuit 11 generates an output pulse. This output pulse activates the relay 116, which turns on the reset switch S2 of the minimum hold circuit 10 and resets the minimum hold circuit 10.

From now on, such operations can be repeated.

The input/output signal levels of the electronic translation apparatus of this embodiment configured as described above have characteristics as shown in FIGS. 8E to 8H.

For example, if the electronic translation circuit 4 is set for Japanese and English,
When the user pronounces "Good morning" into the microphone 1, the speaker 7 pronounces "Good morning" depending on the volume of the voice. At that time, the relationship between the input and output signal levels is as shown in Figure 9E, when a sound is produced in a low voice into the microphone 1, the sound is only produced in a low voice from the speaker 7 as shown in Figure F. On the other hand, when the sound is produced loudly into the microphone as shown in G in the same figure, the sound is produced in a loud voice from the speaker 7 as shown in H in the same figure. Therefore, as shown in FIGS. 8E to 8H, the following relationship holds between the input and output signal levels e, f, g, and h.

e∝f, g∝h, f/e≒h/g In other words, there is a proportional relationship between the input and output signal levels. In this embodiment, the input terminals of the first trigger circuit 112 and the second trigger circuit 113 of the reset circuit 11 are connected to the output side of the speech synthesis circuit 5, but they are connected to the output side of the electronic translation circuit 4. can also operate similarly.

Furthermore, some electronic translation devices are configured so that after the transmission of the translated language signal is finished, a completion signal for notifying the end of transmission can be taken out from the electronic translation circuit.
This end signal (usually a 1000Hz sine wave) is extracted using a BPF (band pass filter) with a frequency of 1000Hz±100Hz, and the waveform is shaped to create a trigger pulse, which activates a monostable multi etc. to operate the reset switch. Further, the first trigger circuit 112 of the reset circuit 11 may be a combination of a slicer circuit and a differentiating circuit, depending on the output level of the speech synthesis circuit 5.
It can also be easily configured by a combination of a switching transistor and a differential circuit.

Further, the second trigger circuit 113 can be constructed by connecting an integrating circuit to a differentiating circuit via a Schmitt trigger circuit, and can generate a trigger pulse when the signal transmission from the speech synthesis circuit ends.

Furthermore, the non-signal part (unrecorded part, that is, the usually 20 to 30 seconds (playback time) between songs on music tapes) of recorded tapes already used in tape recorders etc. Silence,
The second trigger circuit uses an inter-track detection circuit (also called a song selection circuit, cue circuit, blank detection circuit, etc.) that detects blank areas (blank areas) and stops the motor that drives the tape. That's easy. As described above, each of these individual circuits is a known waveform shaping circuit.

Next, another embodiment of the present invention will be described using FIG. 9.

FIG. 9 is an electrical circuit diagram of an electronic translation device according to another embodiment of the present invention.

The microphone 1 is connected to the electronic translation circuit 4 via the input amplifier 2 and the speech analysis circuit 3, and the electronic translation circuit 4 is connected to the speaker 7 via the speech synthesis circuit 5 and the VCA 9a, and The input amplifier 2 is connected to the peak hold circuit 50 through the peak hold circuit 50.
Connected to VCA9a. Further, a reset circuit 11 for opening and closing the reset switch S5 of the peak hold circuit 50 was connected to the output terminal of the electronic translation circuit 4. Further, the character display circuit 8 was connected to the electronic translation circuit 4.

The microphone 1, input amplifier 2, voice analysis circuit 3, electronic translation circuit 4, voice synthesis circuit 5, speaker 7, character display circuit 8 and reset circuit 11 in the figure are the same as those in the previous embodiment.

9a is an inverting voltage controlled amplifier (hereinafter referred to as
VCA), and its operation is as follows.

When external control voltage Vc is applied to the non-inverting input terminal of OP amplifier 85 via resistor 86, OP amplifier 8
5 becomes positive, current flows through a resistor 83 to a light emitting diode (hereinafter referred to as LED) 88 in a photocoupler (hereinafter referred to as PC) 80, and LED8
8 emits light. Upon receiving the light from the LED 88, the resistance value of the light receiving element (hereinafter referred to as CdS) 87 decreases, and in principle, when the non-inverting input terminal of the OP amplifier 85 reaches the virtual ground potential (=OV), the OP The amplification thread of the amplifier 85 becomes stable. In other words, at this time
If the resistance value of CdS87 is λ ₁ , then the external input voltage
As long as the voltage of Vc does not change, the resistance value of CdS87 λ ₁
is retained. Therefore, the CdS 89 receiving light from the same LED 88 also maintains a constant resistance value λ ₂ , and the amplification thread of the OP amplifier 81 operates as an inverting amplifier with a constant voltage gain.
In addition, 90 is a power supply terminal that applies a voltage of -15V, and 82
is a resistor, and 84 is a diode.

Further, 50 is a peak hold circuit, and its operation will be explained.

First, the charging capacitor 53 is brought to 0V by temporarily turning on a non-lock switch S6 that is linked to a power switch (not shown). By doing this, this voltage (=0V) becomes
The signal is fed back to the inverting input terminal of the OP amplifier 51 via the voltage follower of the OP amplifier 54. When the input voltage is higher than this feedback voltage, the output of the OP amplifier 51 generates a positive voltage, so the diode 52 goes in the forward direction and charges the capacitor 53. When charging progresses and the voltage of the capacitor 53 becomes higher than the input voltage, the OP amplifier 51 is inverted and the output becomes a negative voltage, and the diode 52 becomes reverse biased, so the capacitor 5
3 is stopped, and the same voltage as that of the capacitor 53 is maintained at the output terminal of the OP amplifier 54.
In this way, the peak hold circuit 50 holds the maximum value (peak value) of the input signal until it is reset. In this embodiment, the OP amplifier 51,
54, product number TA7505M manufactured by Tokyo Shibaura Electric Co., Ltd. was used. S5 is a reset switch which is driven to open and close by the reset circuit 11.

Next, the operation of the electronic translation device according to this embodiment will be explained.

When you say "Good morning" into microphone 1,
The audio signal converted by microphone 1 is input to input amplifier 2.
After being amplified, the signal is subjected to spectrum analysis and speech recognition in the speech analysis circuit 3, and then converted into a character signal and sent to the electronic translation circuit 4. The electronic translation circuit 4 is
Currently, it is set to translate Japanese into English, so it sends out a character signal "Good Morning", which is converted into a "Good Morning" audio signal by the speech synthesis circuit 5, amplified by VCA 9a, and then amplified by VCA 9a. , the speaker 7 emits the sound "Good morning". However, the volume of the sound emitted from the speaker 7 changes depending on the amplification degree of the VCA 9a, and this amplification degree peak-holds the audio signal "Good morning" that is the output of the input amplifier 2, and the resulting output Controlled according to voltage.

With this structure, the input/output signal level characteristics as shown in FIG. 8 are exhibited similarly to the embodiments described above. In other words, the audio output signal level of the translated language can be changed according to the magnitude of the audio input signal level of the source language. For example, detect the peak level in the pronunciation of "Good morning", hold that level, and apply the output voltage to the VCA9a to change the gain of the VCA9a.
By controlling the peak level of the original language audio signal "Good morning", the audio level when the translated language audio signal "Good morning" sent from the speech synthesis circuit is pronounced from the speaker 7 is controlled. It is something that changes. In other words, if you say ``Good morning'' in a loud voice, the speaker will pronounce ``gutsudmorning'' in a loud voice, and if you say ``good morning'' in a low voice, the speaker will also pronounce ``gutsudo morning'' in a low voice. be.

In the embodiment, an example was shown in which a peak hold circuit and a minimum hold circuit were used to detect the input signal level and hold the level, but the present invention is not limited to this. The level to be detected is not limited to the peak value, but the input signal level of the original language audio signal, such as "good morning", is captured in units of groups of words, words, phrases, sentences, etc., and the average value is calculated. , can be used. That is, all the audio input signal levels of the sentence "Good morning" are added to an analog accumulator via a diode, integrated, the time length of the audio signal "Good morning" is measured, and these two outputs are sent to a divider circuit. The integrated value of the audio input signal level/the audio signal time = average level value is calculated, and the average level value of one sentence, phrase, word, etc. is output. This output can be held and the gain of the VCA etc. can be controlled according to this output level.

In the above two embodiments, one has a minimum
We have shown an example using a hold circuit and a peak hold circuit on the other hand, but this
This is because one of the gain control DC voltages 9 and 9a must be a negative DC voltage and the other must be a positive DC voltage.

This is relative; both are substantially the same except for the bias voltage, and the peak value of the input signal is detected and held.

Furthermore, we have shown an example in which an operational amplifier is used as a voltage-controlled amplifier to control the level of the output signal; this is because the gain can be easily changed over a particularly wide range, and the performance is stable. However, the present invention is not limited to this, and the gain can be easily changed by changing the bias voltage of a normal audio amplifier, changing the amount of negative feedback, and so on. moreover,
Variable resistor or equivalent element (FET, CdS, magnetoresistive element, etc.) without using an amplifier
This can also be implemented by using a circuit and activating it according to the output of a peak hold circuit or the like. For example, if it is a variable resistor, the sliding terminal is moved by a step motor, if it is a FET, a negative voltage is applied to the gate, if it is a CdS, a DC voltage is applied to the LED to cause it to emit light, and if it is a magnetoresistive element, a solenoid is used to move the sliding terminal. This can also be easily implemented by changing the resistance value of each element by applying a magnetic field, etc., and controlling the amount of attenuation of the output signal.

In addition, a minimum hold circuit and a peak
Although we have shown an example in which the hold circuit is connected to the output side of the input amplifier, this is because microphone 1 and input amplifier 2 are shared, and only microphone 1 is shared.
An input amplifier may be provided separately, or a microphone and input amplifier may be provided separately for level detection, and the output thereof may be sent to a peak hold circuit or the like. In this case, it is desirable that the separately provided microphone be placed near the microphone 1.

In the embodiment, the minimum hold circuit and the peak hold circuit are reset by the reset circuit, which detects the end of transmission of the translated language output signal when no signal continues for a predetermined period of time or more, and automatically resets the minimum hold circuit and peak hold circuit. This is to reset the system. Therefore, it is not always necessary to use this method. In the above two embodiments, an example was shown in which a microphone was used as the voice input means, but the invention is not limited to this.
Instead of using a microphone, the source language audio information to be translated is sent via a communication line (including frequencies assigned to radio broadcasting stations) and is received by a receiving means such as a telephone, radio, or television. By configuring the input amplifier 2 and speech analysis circuit 3 to receive the input, together with the effectiveness of the reset circuit 11, the speaker is no longer confined near the electronic translator, and the speaker has freedom of action. The necessary source language information can be sent from anywhere via telephone, etc., and the level is automatically reset for each translation unit, achieving accurate input-output level correlation. It is possible to carry out realistic translation communication.

Further, the present invention can be implemented in a speech recognition→speech synthesis type information processing apparatus (an electronic translator is one of them) as in the above embodiment.

In addition, some of the translation LSIs used in recent electronic translation devices have an output terminal that sends a signal to notify the completion of translation, and some have an output terminal for sending out a signal to notify the completion of translation.
Some LSIs already have an output terminal that sends out a signal to notify the completion of speech synthesis, so by using these, you can apply this output signal to a monostable multi to operate a reset switch. This is easy.

Also, when the VCA does not provide sufficient output,
Alternatively, if you want to obtain a larger output, you can insert a power amplifier circuit between the VCA and the speaker.

In addition, a bandpass filter (BPF) is used as a front stage of the level detection circuit (peak hold circuit, minimum hold circuit, etc.)
By providing a frequency of 240 Hz, it is possible to perform gain control with fewer errors even if the peak value detection method is used. This means that in the case of Japanese, the fundamental frequency is approximately
This is because it can cover 80Hz to 240Hz, so by detecting the peak level in this frequency band, peak detection with less noise is possible.

Also, if you adjust the volume in advance so that the volume of the voice entering the microphone 1 and the volume of the voice coming out of the speaker 7 are approximately the same, from then on, the sound will be made at approximately the same volume as the speaker's voice. You can also freely control the speaker 7 based on the volume of the speaker's voice.
You can control the volume of the voice emitted from the
It's very convenient. Furthermore, although switching is performed using relays 115 and 116 in this embodiment, switching elements such as transistors may also be used.

In this way, in the electronic translator of this embodiment, by changing the gain of the variable gain output circuit for the translated language according to the input signal level of the input circuit for the original language, the audio output signal level of the translated language can be changed to the original language. It is possible to provide an electronic translation device that can automatically change the level of speech input. As described above, according to the present invention, not only the meaning content of the original linguistic information but also the signal level of the original linguistic information can be known from a distance, and since a reset means is provided, it is possible to know the signal level of the original linguistic information from a distance. By the time the translated language information corresponding to the original language information is output to the level adjustment means, the signal level previously held by the level adjustment means is automatically reset, and the signal level previously held is reset. accurately without being affected by the size of the
Moreover, the signal level corresponding to the new translated language information is quickly adjusted, and the input/output correlation between the signal level of the source language information and the signal level of the translated language information can be maintained accurately, resulting in a more natural Translation communication can be carried out.

Furthermore, when the voice input/output device of the present invention is used in a translation telephone device, it is possible not only to convert the voice into a translated language and to convey the loudness of the speaker's voice, but also to enable multiple speakers to speak one after another on the telephone. Even when a single speaker suddenly starts speaking in a loud voice or during a conference call, an automatic reset mechanism is provided so that the volume of the voice can be immediately adjusted to the volume of the translated language. This allows the other party to immediately notice that the person has changed or that the speaker's voice has suddenly become louder, allowing them to accurately convey detailed emotional expressions to the other party. You can have natural conversations and communicate just like with a conventional telephone. Therefore, when connected to a telephone or radio, it is possible to convey the loudness of the speaker's voice, making it possible to convey and understand emotions in more detail than before. The value is great.

In this specification, the proportional relationship also includes the following.

When the input audio signal level is x and the output audio signal level is y: (i) y=ax (however, a is a constant), (ii) y=ax+b (however, a, b are constants, a≠0) ，
b≠0), (iii) y≒ax+b (however, a≠0, a and b are constants), (iv) a=1 in (i), (ii), and (iii) above, (v) Other than the above, the relationship between x and y can be partially considered as y≒ax+b, and (vi) there is a nearly proportional relationship.

[Brief explanation of drawings]

Figure 1 is an electric circuit diagram of a conventional electronic translation device, and Figures 2A to 2D are level characteristic diagrams of the same device.
C shows the input signal level of the same device, and D shows the output signal level relative to the same level of C in the same figure. FIG. 3 is an electric circuit diagram of an electronic translation device that is an embodiment of the present invention, and FIG. 4 is a characteristic diagram showing the relationship between control DC voltage and gain of the voltage control amplifier 9 of the same device.
FIG. 5 is a characteristic diagram showing the relationship between the input and output signal waveforms of each part of the minimum hold circuit 10 of the same device, FIG. 6 is an electric circuit diagram showing a specific example of the reset circuit 11 of the same device, and FIG. 7 is the same circuit. 11, and FIGS. 8E to 8H are level characteristic diagrams showing the relative level relationship between the input and output signal levels of the device, and FIG. 8E shows the input signal level of the device, Figure F shows the output signal level for the same level in Figure E, and Figure G shows the input signal level of the same device.
H in the figure shows the output signal level with respect to the same level in G in the figure. FIG. 9 is an electrical circuit diagram of an electronic translation device according to another embodiment of the present invention. 1...Microphone, 2...Input amplifier, 3...Speech analysis circuit, 4...Electronic translation circuit, 5...Speech synthesis circuit, 7...Speaker, 8...Character display circuit,
9, 9a... Voltage control amplifier, 10... Minimum hold circuit, 11... Reset circuit, 5
0...Peak hold circuit, 51, 54, 8
1, 85, 91, 101, 102...OP amplifier,
34, 53... Charging capacitor, 80... Photocoupler, 87, 89... Light receiving element (CdS),
88... Light emitting diode (LED), 111... Bistable multi, 112... First trigger circuit, 113
... Second trigger circuit, 114 ... Monostable multi,
115, 116...Relay, 112a, 112
b, 113a, 113b...check point,
S1, S4...Switch, S3, S6...Non-lock type switch, S2, S5...Reset switch.

Claims (1)

[Claims] 1. Receiving means for receiving source language information to be translated sent from a distant place via a communication line, and responding to the source language information based on the source language information received by the receiving means. a translation means for translating the translated language information into translated language information; a level adjustment means for adjusting the signal level of the translated language information translated by the translation means; and information for outputting the translated language information at the signal level adjusted by the level adjustment means. An output means maintains a correlation between a signal level of the original language information received by the receiving means and a signal level of translated language information corresponding to the original language information output from the information output means. input/output correlation control means for operating the level adjustment means, and automatically adjusting the level after the translated language information is output from the information output means and before the next translated language information is output. An electronic translator comprising: reset means for instructing the input/output correlation control means to release the holding operation of the means. 2. A patent claim characterized in that the input/output correlation control means detects the average level or peak value level of the input signal level and controls the output signal level output from the information output means via the level adjustment means. The electronic translation machine according to item 1. 3. a speech recognition means for recognizing the source language speech information received by the receiving means; a translation means for translating into translated language information corresponding thereto based on the source language information recognized by the speech recognition means; and the translation means a speech synthesis means for synthesizing corresponding translation language speech information based on the translation language information translated by the speech synthesis means; a level adjustment means for adjusting a signal level of the translation language speech information synthesized by the speech synthesis means; audio information output means for outputting translated language audio information with a signal level adjusted by the level adjustment means; a signal level of the original language audio information received by the receiving means and the original language output from the audio information output means; input/output correlation control means for operating the level adjusting means to maintain a correlation between the signal level of the translated language audio information corresponding to the audio information; and the translated language audio information is output from the audio information output means. reset means for automatically instructing the input/output correlation control means to release the holding operation of the level adjustment means until the next translated language audio information is output. An electronic translation machine. 4. A patent characterized in that the input/output correlation control means detects the average level or peak value level of the input signal level and controls the output signal level output from the audio information output means via the level adjustment means. An electronic translation machine according to claim 3. 5. Receiving means for receiving unprocessed voice information to be processed sent from a distant place via a communication line; Speech recognition means for recognizing the unprocessed voice information received by the receiving means; and the voice Information processing means for processing the unprocessed information recognized by the recognition means into processed information corresponding thereto; and audio for converting the processed information processed by the information processing means into audio information corresponding to the information and transmitting the same. a sending means; a level adjusting means for adjusting the signal level of the processed audio information converted by the audio sending means; and an audio information outputting means for outputting the processed audio information of the signal level adjusted by the level adjusting means. , maintaining a correlation between the signal level of unprocessed audio information received by the receiving means and the signal level of processed audio information corresponding to the unprocessed audio information output from the audio information output means; input/output correlation control means for operating the level adjustment means in such a manner; and a reset means for instructing the input/output correlation control means to release the holding operation of the level adjustment means. 6. A patent characterized in that the input/output correlation control means detects the average level or peak value level of the input signal level and controls the output signal level output from the audio information output means via the level adjustment means. The audio input/output device according to claim 5.