JPH01279498A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To separate the parasitic capacitor of a common data line and a data line, to relieve the load of a sense amplifier and to quicken the readout by providing a readout amplifier connected directly to the data line. CONSTITUTION:A memory array consists of arrays UM, LM. Signals L, R to select right/left series circuits and a selection signal US for the array UM are supplied to gate circuits G1, G2 and a left series storage circuit is coupled with a data line DO through MOSFETs Q2, Q1. With the signals US, R at an H level, the right series storage circuit is coupled with the line DO. Then the storage information of the storage MOSFET is read by readout amplifier circuits DA0, DA1 as sub sense amplifiers and its amplified output is outputted through a sense amplifier SA and a data output buffer DOB through a common data line CD.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to semiconductor storage devices, such as large storage capacity mask-type ROMs (read-only memories) and E-ROMs.
PROM (Erasable & Programmable ROM)
It is related to effective technology that can be used for.

[Conventional technology]

With the advancement of semiconductor technology, mask type ROM and EPROM
Semiconductor records such as +! ! Efforts are being made to increase the storage capacity of devices. As an example of a mask type ROM suitable for such a large storage capacity, for example, Japanese Patent Application Laid-Open No. 59-1169
There is a publication No. 93.

[Problem to be solved by the invention]

In order to meet the above-mentioned increase in storage capacity, elements have been miniaturized, and storage elements constituting a large number of memory cells are coupled to one data line (bit line or digit line). Therefore,
The parasitic capacitance of the data line increases and correspondingly it takes time to charge and discharge the parasitic capacitance, so the time required to read the memory cell becomes longer.

An object of the present invention is to provide a semi-donor storage device that realizes high-speed S: overflow.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief explanation of typical aspects of the invention disclosed in this application is as follows.

That is, a read amplifier that is activated by the YJ multiplier signal is provided on the data line to which the memory cell is coupled.

[For production]

According to the above means, by providing a read amplifier directly connected to the data line, the parasitic capacitance between the data line and the common data line is separated, so the load on the read amplifier and the sense amplifier provided on the common data line is reduced. By transmitting the signal amplified by the read amplifier to the common data line, the reading speed can be increased.

[Embodiment] FIG. 1 shows a circuit diagram of an embodiment of a vertical ROM ("7-screen ROM") to which the present invention is applied. The circuit is formed on a single semiconductor substrate such as, but not limited to, single-crystalline silicon using a circuit fabrication technology. Although not particularly limited, the 'fi' R, OM of this embodiment is an N-channel The integrated circuit is therefore formed on a semiconductor substrate made of single-crystal P-type silicon.The N-channel MO3FET consists of a source region, a drain region and Between the source region and the drain region, it is composed of an electrode made of polysilicon formed on the surface of the conductor substrate via a thin 8Q film.

The memory array may include, but is not limited to, a memory array UM located on the upper side and a memory array LM located on the lower side, as shown by the broken line in the figure. Each memory array UM and LM has a chip b? M for storing i number
It consists of O3FETQm connected in series. Each of the storage MOSFETs Q and m is formed as a depletion type or an enhancement type depending on the storage information. Although not limited to the back, for example, 1, the above enhancement type M
A depletion type memory MO3 having a negative threshold voltage is created by introducing a tram-shaped material similar to that of the substrate gate onto the surface of the channel region of the O3FET.
Writing is performed to form a FET. In the figure, the depletion type MOSFET is distinguished from the enhancement type MOSFET by adding straight lines to each channel portion.

In this embodiment, in order to achieve high integration of the memory array, a pair of series-type storage MO3FETs in each of the above-mentioned memory arrays IIM and LM are commonly arranged on one data line Do, DI, etc. Ru.

One end of a pair of series circuits of the memory array TJM provided for one data 810 to be connected to the data line DO is connected to an AND gate circuit Hc1 constituting a predecoder to be described later. and a switch MO3 in series form receiving a selection signal formed by G2.
FETs QI, Q2 and G3, G4 are each connected in series and commonly connected to the data line DO. The gate circuit Gl.

By the selection signal formed by G2, the data line D
A pair of serial storage M arranged on the left and right with respect to o
To select one of the OS FETs, for example MO3
FETQI and G4 are depletion type Mo SF
ET, G2 and G3 are enhancement type MO5FETs
Each is composed of:

A selection signal R for selecting the left and right series circuits and a selection signal US for the upper memory array UM are supplied to the inputs of the gate circuits Gl and G2. For example, signal US
When and L are at high level, the output signal of gate circuit G2 is set at high level, and MO3FET Q2 is turned on. As a result, the enhancement type MO5FETQ2 turned on and the depletion type MO
The left serial storage circuit is coupled to the data line DO through 3F ETQ l. Further, when the signals US and R are at a high level, the output signal of the gate circuit G1 is set at a high level, and the MO3FET Q3 is turned on. As a result, the enhancement type M that has been turned on is
O5FETQ3 and day reflex MO3FETQ4
Through the serial storage circuit on the right side, the data 49 D O
is combined with

This means that the serial storage MO3F corresponding to the data 'fFFADo in the lower memory array LM is
M OS F E TQ5 provided for ETQm
The same applies to G6, G7, and G8.

However, the AND gate circuits G3 and G4, which form the selection signals supplied to the gates of MO3FETQ5 and G6 and G7 and G8, are instructed to select the selection signals R and L and the lower memory array LM. A selection signal LS is supplied. As a result, for example, when fK signals LS and L are at a high level, the output signal of the gate circuit G4 is set at a high level, and the MO3FET Q6 is turned on. Therefore, the enhancement type MO3 turned on is
The left serial storage circuit is coupled to the data line Do through FETQ6 and depletion type MO3FETQ5.

Furthermore, when the signals LS and R are at high level, the output signal of gate circuit G3 is set at high level, and MO3FETQ
7 is turned on.

As a result, the enhancement type MO3FET Q7 and the depletion type MO3FET that have been turned on are
The right serial storage circuit is coupled to the data line DO through Q8.

Storage MO of each serial form of the above memory arrays UM and LM
Among the 3FETs, MO3FET for storage corresponds to the horizontal direction.
The gates of Qm are commonly connected to word lines WO to WSi2, respectively. These word lines WO to WSi
2 is connected to each corresponding output terminal of the row decoder XDCR.

In this embodiment, in order to realize high-speed reading, a read amplifier DAO1DA is used for the above data &%DO, DI, etc.
Input terminals such as I are connected. That is, instead of the conventional configuration in which the data lines are connected to the common data line CD through a column switch circuit, each of the data lines DO
, DI are each provided with a read amplification circuit DAOlDAl etc. that outputs a sub-sense amplifier. Although not particularly limited, the amplifier circuits DAOlDAl and the like are selectively activated by the column selection signals YO, Y1, etc.

Although not particularly limited, the column decoder YDCR may be 51
Selection signal YO1Y for two data lines Do to D511
1... is formed. Therefore, the memory arrays IJM and LM have a storage capacity of 512x512x4 bits (?) IM bits). For example, about 4
When configuring a vertical ROM with a storage capacity of M bits,
Four memory mantles consisting of memory arrays UM and LM similar to those described above are provided.

In each of the amplifier circuits DAO to DA511 provided corresponding to the data lines DO to D511, one JiQ information circuit is activated by the column selection signals YO, 'I'L, etc. is rendered inactive and its output is placed in a high impedance state. As a result, the output terminals of the amplifier circuit DAOlDAl and the like are connected to the common data line CD. In other words, the output of each amplifier circuit DAO to DA511 is connected to the common data line CD
Therefore, wired-or logic is adopted.

The common data line CD is connected to the input terminal of the sense amplifier SA. The read signal amplified by the sense amplifier SA is sent out from the output terminal Dout through the data output sofa DOB.

Note that, although not particularly limited, the sensing operation can be performed by referring to a reference voltage Vref formed by a dummy array formed of a memory circuit similar to the memory array section as the base Y$N voltage of the sense amplifier SA. In this case, the amplifying circuit DA is also provided for the dummy array. In other words, the dummy array is a memory MO3FETQ
The transistors m are all constituted by enhancement type MO3FETs, and are constantly turned on by constantly supplying the voltage Vcc to their gates.

The address selection operation of the reduced ROM in this embodiment will now be described.

Row decoder XDCR is row address eight sofa XAD
The internal address signal supplied from B is decoded to form a decoded output that sets the IX selection level to low level and the non-selection level to high level.

That is, one selected word line among the 512 word lines is set to low level, and the other 511 word lines are set to high level. As a result, if the storage MO3FETQm coupled to the selected word line is of the depletion type, a current path is formed in the series circuit, and if the storage MO3FETQm is of the enhancement type, no current bus is formed. Then, one of the four pairs of series circuits is connected to JX and connected to data) 10 to D512. The column decoder YDCR decodes the internal address signal supplied through the column address buffer YADB and outputs the 512 data lines DO.
The selection signal corresponding to one data line selected among D511 to D511 is set to a low selection level, and the other 511 is set to a low selection level.
The selection signal corresponding to the wooden data line is set to a high non-selection level.

As a result, the 1 corresponding to the selected data line is
The two readout amplification circuits 1!3DA are in operation.

As a result, the readout of the storage information of one storage MO3FET is performed by the readout amplifier circuit DA as the sub-sense amplifier, and its amplified output is sent to the common data line C.
Sense amplifier SA and data output cover sofa D through D
It is output from the terminal Dout through OB.

In addition, in the same figure, the address buffer and decoder are combined into one circuit block XADB-DCR,YAD
It is expressed as B-DCR.

FIG. 2 shows a specific circuit diagram of one embodiment of the read amplification circuit.

In the same figure, the channel (substrate gate) part with an arrow added is the P channel part SFET,
The channel portion of the N-channel MO3FET with a straight line added thereto is similar to the one described above.

One data line DO and one data line exemplarily shown? ! ! A MOSFE that forms a read current is connected to the X voltage Vcc.
TQ9 is connected. The data VDO is connected to the gate of an N-channel source-grounded amplifier MO3F-TQIO. The drain of this amplified MO3F ETQ 10 is equipped with a depletion type Mo5t” as a load.
A TQII is provided.

This depletion type MO3FF', TQ11, has its gate and source connected, thereby acting as a constant current source load. Between the load MOSFE'rQII and the power supply voltage Vcc, there is a P as a power switch.
A channel MO3FETQ12 is provided. The output signal of the inverting amplifier circuit consisting of the amplifying MO3FET QIO and the load MO3FET QII is fed to the gate of the MOSFET Q9 which forms the read current.

Lyrics for the above amplification MO3FETQIO (upper, ri)?Tff
An N-channel MO8FETQ13 was installed for the same purpose. The output signal of the inverting amplifier circuit is supplied to the gate of the amplifier N10SFM TQ15 as a level shift circuit. This star width MO3FETQ1.5 performs a source follower amplification operation. Therefore, a depletion type MO5FETQ16 as a load is provided between the source of the MOSFETQ15 and the ground potential point of the circuit. This daburension type MO3FET QI 6 operates as a constant current source in the same manner as described above by having its gate and source connected in common.

A P-channel MOSFET Qi4 as a bypass switch is provided between the drain of the amplification MOSFET'Q15 and the power supply voltage Vcc. Further, the source output of the amplifying MOSFET Q15 that performs the level shift operation is connected to the amplifying MO3FET Q17 whose source is grounded.
Supplied on a date,? L Ruyuko amplification MO3FETQ1
Between the drain and drain of 7 and the common data line CD, an N-channel type switch MOS F ETo for output control is connected.
18 are provided.

A column selection signal YO is supplied to the gates of the N-channel MOSFET QI 3 and the P-channel MOSFETs QI 2 and Qi4. Also, N channel MO
An inverted column selection signal Y is applied to the gate of 3FET018.
O is supplied.

The operation of the read amplifier circuit DAO of this embodiment is as follows.

If the column selection signal YO is at a high non-if level,
- The P-channel MO3FETQI2, Ql4 and N-channel MO3FBTQ18 are turned off, and the N-channel MO3FETQ]3 is turned on. - The inverting amplifier circuit (Qll) is turned off by the off state of the MO3FETs Q12 and Ql4.

Ql2) and the level shift circuit (Ql5.Ql6) are
Operating direct current does not flow and no current is consumed. Also, M.O.
With the 5FET Q18 in the off state, the output becomes a high impedance state. Then, due to the ON state of MO3FETQI3, the read current does not flow to the data line DO and MO3FETQI3 is turned on.
Turn FETQ9 off. As a result, the output of the selected amplifier circuit as described below is output to the common data line CD.

If the column selection signal YO is at the low selection level, the above Pchi 4 yio SF ETQ 12.0
14 and N-channel MO3FET QIL are turned on, and N-channel MO5FETGλ13 is turned off. The ON state of MO3FETQ12 and Ql4 above and M
O3FETQI3 OFF state causes the above-mentioned inverting amplifier circuit (Ql l, ul 2) and shift circuit (Ql
5. Ql 6) operation is enabled. Dear Sun,
An operating voltage is supplied by the ON state of MO3FETQ12 and Ql4. Inverting amplifier circuit, two-legged MOS
A signal is amplified according to the ratio between the conductance of FETQ9 and the combined conductance of the series MO3FE'*' circuit coupled to the data line DO. The above data line DO
If current is flowing through the inverting amplifier circuit (Q10 and Ql
The output signal of l) becomes a relatively high potential, and the MO5FET
The gate potential of Q9 is raised to prevent the data and JDO potentials from becoming too low. On the contrary, data! ? When no current flows through fDO, the output signal of the inverting amplifier circuit has a relatively low potential, which lowers the gate potential of MO3FETQ9 to prevent the potential of data line DO from becoming too high. As a result, the signal amplitude of the data line DO is suppressed, so the change between the read high level and the low level of the data 110 is small, and the current consumed for charging and discharging the parasitic capacitance on the data line DO is small. High-speed reading becomes possible.

The output signal of the above inverting amplifier circuit (QIO, Qll) is
A source follower circuit consisting of MO3FETQ15 and Ql7, the threshold voltage V thn of MO3FF and TQ15
The level of the signal is shifted by 1, and is transmitted to the gate of MO3FETQ17. This turns MO3FETQ17 on/off.
The signal is turned off and read out by the sense amplifier SA through the switch MO3FET Q18 and the common data line CD.

The sense amplifier SA is composed of an input circuit similar to the current sense circuit described above, and an amplifier circuit OA that receives an output signal from the input circuit. That is, the current sensing section of the sense amplifier SA is composed of MO3FETs Q20 to Q24, and uses an internal chip enable signal CF as a control signal.

That is, when the ROM to which the signal CE is set to low level is in the operating state, it is activated and the read signal transmitted from the common data line CD is amplified in the same manner as described above. In this case as well, high-speed reading becomes possible due to the level limiter action.

And the read amplifier DA as a sub-sense amplifier
O, etc. are used to cause a sense current to flow through one data line Do, and the sense amplifier SA causes a sense current to flow through the common data line CD and one selected amplification MO3FET Q17, etc. As a result, the parasitic capacitance of the data line and the common data line is separated, and the respective charging/discharging currents are transferred to the two amplifiers D.
Since it is performed in A and SA, the charging and discharging can be performed at high speed. This enables high-speed reading of a ROM with a large storage capacity as described above.

This can be explained quantitatively as follows.

The potential v1 of the data line DO is determined by the following equation +11.

V 1 = VthN+ (β., /β.ri ””
l VLhNo l・ ・ ・ ・ ・ (11 Here, β is the channel conductivity of each MOS FET, v th is the threshold voltage of the N-channel MOS FET, and V thNo is the depletion type MO3FE
is the threshold voltage of T.

The output voltage V3 of the level shift section is determined by the following equation (2).

V 3 =VthN+[(β.3./β.,,)I/Z
−(β.16/β.+s)””) l Vttro
l ten (2i, / β.,) I/Z ・
(2) Here, iH is the current flowing through the memory cell of the data line.

The potential 4 of the common data line CD is determined by the following equation (3).

V4=Vth, + (βazt/βoz+)”” l
VthHo l (3) The voltage v5 of the sense amplifier SA is determined by the following equation (4).

V5=2Vth, + (β., /β.1゜ν" l
VthNn l+(β.1./β.9)”” (V 3
- VthN) ... (4) Here, (β.1./β
. ,. )"" = (β., 6/β,,)l/2, if the size (W/L) of each MO3FET is set, the above equation (2) becomes the following equation (5) .

V 3-V thN →-(2in/β.,) l/2
...(5) Substituting equation (5) into equation (4), we get
The following equation (6) is obtained.

V5=2Vthh + (β, l, /βQ1゜)""
IVth, la l+(β, +7/β.,)”” (
2ix/β. ,) l/Z・ ・ ・ ・ ・ ・(
6) As a result, the signal amount ΔV5 is (β., 7/β.,)l
/2 (2iN/ β.,) l/2, and MOSFE
The signal amount is amplified by the W/L ratio of TQ9 and Q17.

Furthermore, even though each of the data lines DO to D511 is provided with an amplifier circuit as a sub-sense amplifier as described above, only one amplifier circuit is activated by the Y-system selection signal. Low power consumption can be maintained.

FIG. 3 shows a circuit diagram of another embodiment of the read amplification circuit.

In this embodiment, a current sensing section similar to the above (Q9 to QI
The output signal of 2) is supplied to a level shift circuit consisting of MOSFETQ26 and Q27, and the output signal is transferred to the MOSFET Q26 and Q27.
The inverting amplifier circuit consisting of ETQ30 and Q29 has a width of t+rI, and the source is connected to the drain output MO3FF and the gate of TQ32. Then, between the gate of the output MO5FETOR2 and the ground potential, an N-channel switch MO
3FBT Q S 1 is set up, τ is the above selection FJ?
It supplies the signal YO. Further, the operating voltage and current are supplied to the bell shift circuit and the inverting amplifier circuit receiving its output through a power switch MO5FF, T consisting of P-channel MO3FETs Q25 and Q28.

In this configuration, when the selection signal YO is at a high level (non-selected), the above-mentioned circuits become inactive, and the M
Output MO3FETQ due to ON state of OSFETQ31
32 can be turned off. This makes it possible to create an output high impedance state in non-liI+ operation. In this configuration, since the drain of the output MO3FET Q32 is directly coupled to the common data line CD, there is no on-resistance caused by the switch MO3FET QI8 as described above, and higher speed reading is possible.

The effects obtained from the above examples are as follows. That is, (1) By providing a read amplifier (sub-sense amplifier) that is activated by the YiJ selective signal on the data line to which the memory cells are coupled, the parasitic capacitance between the data line and the common data line is separated. Therefore, the load on the read amplifier and the sense amplifier provided on the common data line is reduced, and the read speed can be increased by transmitting the signal amplified by the read amplifier to the common data line. Get the effect that you can.

(2) By activating only one of the read amplifiers provided on the data line by the Y selection signal, it is possible to achieve the effect of reducing power consumption.

・(3) A pair of series MOs on the left and right for one data line
In addition to arranging the 3FETs, a data line for connecting and displacing the upper and lower memory arrays can be arranged between the diffusion layers forming a pair of series MOS FETs. With this, the day
'7 Green and 10 E 41-η2 (Anti-sha's - is relatively thick': '7 Green, 1 space insulating rib support and field insulating waist should be provided. 2. As a result, in combination with the effect of (1) above, it is possible to further improve efficiency. Zru.

7. According to the inventor of the present invention. Although the invention has been specifically explained based on 5.7 examples, it goes without saying that the invention is not limited to the above-mentioned examples and can be modified in various ways without departing from the gist of the invention. Nor. For example, if 5 FETs are connected in series to one data line in a tF- manner, various modifications can be made. The specific configurations of the sub-sense amplifiers provided and the sense amplifiers provided on the common data line can take various embodiments. In addition, in the memory array UM on the E side shown in FIG.
One in which 3 FETs are arranged and one of them is selectively connected by a column switch circuit, or the memory array is arranged in a vertically stacked configuration in three stages such as upper, middle, and lower. Various embodiments may be adopted, such as those in which: Such a ROM may constitute one storage device or may be built into a digital integrated circuit such as a microcomputer.

The present invention has been described above with respect to a vertical ROM, which is the background thereof, but the present invention is also applicable to not only a vertical ROM, but also a mask type ROM such as a horizontal ROM, and an erasable ROM such as an EP ROM and an EEPROM. It can be widely used in semiconductor memory devices that have a relatively large parasitic capacitance by connecting a large number of memory cells to a data line, such as electrically writable programmable ROMs.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows. In other words, by providing a read amplifier (sub-sense amplifier) that is activated by the Y selection signal on the data line to which the memory cell is coupled, the parasitic capacitance between the data line and the common data line is separated. The load on the sense amplifier provided on the common data line is reduced, and the signal amplified by the read amplifier is transmitted to the common data line, thereby increasing the speed of reading.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of a vertical ROM to which the present invention is applied, FIG. 2 is a circuit diagram showing an embodiment of the read amplifier circuit and sense amplifier, and FIG. FIG. 7 is a circuit diagram of another embodiment of the readout amplifier circuit. DAO to DA511...Read amplifier circuit (sub-sense amplifier), UM...Upper memory array, LM...Lower memory array, YADB-DCR...Column address buffer/decoder, XADB/DCR...Row address buffer/decoder , SA... sense amplifier, DOB
・・Data output buffer, G1-G4・・AND gate circuit, OA・・amplifier circuit,

Claims (1)

Claims: 1. A semiconductor memory device characterized in that a data line to which memory cells are coupled is provided with a read amplifier that selectively transmits an output signal to a common data line by a Y selection signal. 2. The semiconductor memory device according to claim 1, wherein the memory cell has stored information that is nonvolatile when the power supply voltage is interrupted. 3. The read amplifier comprises a current sensing section of a selected memory cell and a level shift section for amplifying the sense output, and is activated by the Y selection signal. A semiconductor memory device according to scope 1 or 2.