JPH01278142A - Modulating system for transmission line signal - Google Patents

Modulating system for transmission line signal

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Publication number
JPH01278142A
JPH01278142A JP63108290A JP10829088A JPH01278142A JP H01278142 A JPH01278142 A JP H01278142A JP 63108290 A JP63108290 A JP 63108290A JP 10829088 A JP10829088 A JP 10829088A JP H01278142 A JPH01278142 A JP H01278142A
Authority
JP
Japan
Prior art keywords
signal
series
sequence
transmission line
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP63108290A
Other languages
Japanese (ja)
Other versions
JPH0683191B2 (en
Inventor
Hiroshi Fujimura
藤村 博司
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP63108290A priority Critical patent/JPH0683191B2/en
Publication of JPH01278142A publication Critical patent/JPH01278142A/en
Publication of JPH0683191B2 publication Critical patent/JPH0683191B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Abstract

PURPOSE:To reduce same code continuation length and also to suppress the occurrence of the same code continuation itself by modulating branched signals of two series having the same contents via two M-series generators having different numbers of stages and selecting and transmitting a signal series having small code continuation length. CONSTITUTION:A speed converting circuit 7 inputs an input signal series subjected to speed conversion to a branch circuit 8. 1st and 2nd M-series signal generators 10 and 13 having different numbers of stage produce 1st and 2nd M-series signals which are supplied to 1st and 2nd exclusive OR circuit 11 and 14 respectively. Then the 1st modulation input signal series are different from the 2nd modulation input signal series. A selection circuit 15 adds information showing the specific series where the modulation is applied to the remaining bit of the signal having the smaller continuous same polarity signal length by means of the output of a specific M-series signal generator. Then said added information is outputted to a transmission line 6 as a transmission line signal. Thus it is possible to reduce the same code continuation length and at the same time to suppress the occurrence of the same code continuation itself.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明はPCM通信方式の伝送路信号に関し、特に伝
送路信号のマーク率がはホ1/2のランダム信号が得ら
れる伝送路信号変調方式に関する。
[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a transmission line signal of a PCM communication system, and in particular to a transmission line signal modulation system that can obtain a random signal with a mark rate of 1/2 of the transmission line signal. Regarding.

〔従来の技術〕[Conventional technology]

一般に、PCM通信方式における伝送路符号としては、
(A)受信側でタイミング抽出が容易であること、(B
)回路構成が簡単であることなどの理由から1とOの発
生確率がほぼ等しく一定の直流成分が得られるいわゆる
平衡符号が望ましい。
Generally, the transmission path code in the PCM communication system is as follows:
(A) Timing extraction is easy on the receiving side; (B)
) A so-called balanced code is desirable because the circuit configuration is simple and the probabilities of occurrence of 1 and O are approximately equal and a constant DC component is obtained.

第2図は従来の伝送路信号変調方式を示すブロック図で
ある。同図において、1は情報信号が入力する入力端子
、2はこの情報信号のnビット毎に1ビットの余剰ビッ
トを付加して速度変換された入力信号系列を出力する速
度変換回路、3は一定周期毎にリセットパルスが入力す
るリセット入力端子、4はM系列信号を出力するがこの
リセットパルスの入力によシリセットされるM系列信号
発生器、5は排他的論理和回路、6は伝送路である。
FIG. 2 is a block diagram showing a conventional transmission line signal modulation method. In the figure, 1 is an input terminal into which an information signal is input, 2 is a speed conversion circuit that adds 1 extra bit to every n bits of this information signal and outputs an input signal sequence whose speed has been converted, and 3 is a constant speed conversion circuit. 4 is an M-series signal generator which outputs an M-series signal and is reset by inputting this reset pulse; 5 is an exclusive OR circuit; and 6 is a transmission line. be.

次に上記構成による伝送路信号変調方式の動作について
説明する。まず、入力端子1に入力した情報信号は速度
変換回路2に入力する。この速度変換回路2はnビット
毎に1ビットの余剰ビットを付加し、速度変換された入
力信号系列を排他的論理和回路5に出力する。一方、M
系列信号発生器4はリセット信号により一定周期毎にリ
セットされたM系列信号を排他的論理和回路5に出力す
る。そして、排他的論理和回路5は入力信号系列を変調
して得られた伝送路符号を伝送路6に出力する。この伝
送路信号としては比較的長い時間にわたってみた場合、
1と0の発生確率がほぼ同程度の即ちマーク率がほぼ1
/2のランダム信号が得られる。
Next, the operation of the transmission line signal modulation method with the above configuration will be explained. First, the information signal input to the input terminal 1 is input to the speed conversion circuit 2. The speed conversion circuit 2 adds one extra bit to every n bits and outputs the speed-converted input signal sequence to the exclusive OR circuit 5. On the other hand, M
The sequence signal generator 4 outputs the M sequence signal reset at regular intervals by the reset signal to the exclusive OR circuit 5. The exclusive OR circuit 5 modulates the input signal sequence and outputs the obtained transmission line code to the transmission line 6. When looking at this transmission line signal over a relatively long time,
The probability of occurrence of 1 and 0 is almost the same, that is, the mark rate is approximately 1.
/2 random signal is obtained.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述した従来の伝送路信号変調方式は入力信号系列を一
定周期毎にリセットされるM系列信号によって変調する
ように構成されているが、このリセットパルス周期程度
の短時間では入力信号によっては同符号連続の生じる場
合があ夛、受信側でタイミング抽出が困難となったシ、
直流成分の変動のため識別マージンが劣化することがあ
る。また、連続する同符号数は確率的にしか把握できな
いし、全て同符号となるととも確率的にはあシ得ないと
いう欠点がおる。
The conventional transmission line signal modulation method described above is configured to modulate the input signal sequence with an M-sequence signal that is reset at regular intervals, but in a short period of time such as this reset pulse period, depending on the input signal, the signals may have the same sign. There are many cases where continuity occurs, making it difficult to extract the timing on the receiving side.
The identification margin may deteriorate due to fluctuations in the DC component. In addition, the number of consecutive identical codes can only be grasped probabilistically, and even if all the codes are the same, there is a drawback that it cannot be determined in terms of probability.

〔課題を解決するための手段〕[Means to solve the problem]

この発明に係る伝送路信号変調方式は、nビット毎に1
ビットの余剰ビットを付加するよう速度変換する手段と
、この速度変換された入力信号系列を2分岐する手段と
、この2分岐された信号系列と排他的論理和を取るため
のM系列信号を発生する段数の異なる2個のM系列信号
発生器と、いずれの排他的論理和出力を伝送路信号とし
て送出するかを選択しその選択情報を余剰ピッ)K付与
する回路とを有している。
The transmission line signal modulation method according to the present invention has a transmission line signal modulation method of
A means for converting the speed so as to add surplus bits, a means for branching the speed-converted input signal sequence into two, and generating an M-sequence signal for taking an exclusive OR with the two-branched signal sequence. The M-sequence signal generator has two M-sequence signal generators with different numbers of stages, and a circuit that selects which exclusive OR output is to be sent out as a transmission line signal and provides the selection information as an extra signal.

〔作用〕[Effect]

この発明は同符号連続長を大幅に短縮でき、しかも同符
号連続そのものの発生を抑圧することができる。
This invention can significantly shorten the length of the same code sequence, and can also suppress the occurrence of the same code sequence itself.

〔実施例〕〔Example〕

第1図はこの発明に係る伝送路信号変調方式の一実施例
を示すブロック図である。同図において、7は入力端子
T&に情報信号が入力し、出力端子7bからnビット毎
に1ビットの余剰ビットを付加して速度変換された入力
信号系列が出力し、出力端子7cからブロック情報信号
が出力する速度変換回路、8は速度変換された入力信号
系列を2つに分岐する分岐回路、9は第1リセツトパル
スが入力する第1リセツト端子、10はこの第1リセツ
トパルスによシ一定周期毎にリセットされ、第1M系列
信号を発生する4段構成の第1M系列信号発生器、11
は分岐された入力信号系列をこの第1M系列信号によっ
て変調し第1変調入力信号系列を出力する第1排他的論
理和回路、12は第2リセツトパルスが入力する第2リ
セツト端子、13はこの第2リセツトパルスによシ一定
周期毎にリセットされ、第2M系列信号を発生するn段
構成の第2M系列信号発生器、14は分岐された入力信
号系列をこの第2M系列信号によって変調し第2変調入
力信号系列を出力する第2排他的論理和回路、15は入
力する第1変調入力信号系列と第2変調入力信号系列の
うち同符号連続長の短い方の信号系列を選択すると共に
いずれの信号系列を伝送路符号としたかの情報を余剰ビ
ットに付加する選択回路である。
FIG. 1 is a block diagram showing an embodiment of a transmission line signal modulation method according to the present invention. In the figure, an information signal is input to the input terminal T&, an input signal sequence whose speed has been converted by adding 1 surplus bit every n bits is output from the output terminal 7b, and block information is output from the output terminal 7c. 8 is a branch circuit that branches the speed-converted input signal series into two; 9 is a first reset terminal to which the first reset pulse is input; 10 is a circuit that is reset by this first reset pulse; a four-stage first M-sequence signal generator that is reset at regular intervals and generates a first M-sequence signal; 11;
1 is a first exclusive OR circuit that modulates the branched input signal sequence with the first M sequence signal and outputs the first modulated input signal sequence; 12 is a second reset terminal to which the second reset pulse is input; 13 is this A second M-sequence signal generator 14 having an n-stage configuration that is reset at regular intervals by a second reset pulse and generates a second M-sequence signal; A second exclusive OR circuit 15 outputs two modulated input signal sequences, and 15 selects the shorter signal sequence with the same code continuous length among the first modulated input signal sequence and the second modulated input signal sequence. This is a selection circuit that adds information on whether the signal sequence of is used as a transmission path code to the surplus bits.

次に上記構成による伝送路信号変調方式の動作について
説明する。まず、入力端子1に入力した情報信号は速度
変換回路7に入力する。この速度変換回路Tはその出力
端子7bからnビット毎に1ビットの余剰ビットを付加
して速度変換された入力信号系列を分岐口−8に出力す
る一方、出力端子7cからブロック情報信号を選択回路
15に出力する。そして、この分岐回路8はこの速度変
換された入力信号系列t−2つに分岐してそれぞれ第1
排他的論理和回路11および第2排他的論理和回路14
に出力する。そして、第1排他的論理和回路11は分岐
された一方の入力信号系列を一定周期毎にリセットされ
る第1M系列信号によって変調し第1変調入力信号系列
を選択回路15に出力する。一方、第2排他的論理和回
路14は分岐された他方の入力信号系列を第2M系列信
号によって変調し第2変調入力信号系列を選択回路15
に出力する。このとき、第1排他的論理和回路11およ
び第2排他的論理和回路14の一方の入力端子に入力す
る信号は共に速度変換されたのちの情報信号でその内容
は全く同一であるが、他方の入力端子にそれぞれ入力す
る第1M系列信号および第2M系列信号はその第1M系
列信号発生器10および第2M系列信号発生器13の段
数が異なるため、この第1変調入力信号系列と第2変調
入力信号系列とは異なった信号となる。このため、選択
回路15は速度変換回路7の出力端子7Cから出力され
たブロック情報を利用し第1変調入力信号系列および第
2変調入力信号系列のnビットの連続する情報ビットお
よびそれに付加された1ビットの余剰ビット位置を検出
すると同時に、nビットの情報ビット内に含まれる連続
した同一極性信号長を第1変調入力信号系列および第2
変調入力信号系列について比較し、連続した同一極性信
号長の短い方の信号の余剰ビットにいずれのM系列発生
器出力を利用して変調をかけた系列であるかを示す情報
を付加して伝送路信号として伝送路6に出力する。この
伝送路信号も確率的にしか連続する同符号連続数を把握
できないが、同符号連続長を大幅に短縮できると同時に
同符号連続そのものの発生を抑圧することが可能となる
Next, the operation of the transmission line signal modulation method with the above configuration will be explained. First, the information signal input to the input terminal 1 is input to the speed conversion circuit 7. This speed conversion circuit T outputs an input signal sequence whose speed has been converted by adding one surplus bit every n bits from its output terminal 7b to a branch port -8, and selects a block information signal from its output terminal 7c. Output to circuit 15. Then, this branch circuit 8 branches this speed-converted input signal series into t-2, each with a first
Exclusive OR circuit 11 and second exclusive OR circuit 14
Output to. Then, the first exclusive OR circuit 11 modulates one of the branched input signal sequences with the first M sequence signal that is reset at regular intervals, and outputs the first modulated input signal sequence to the selection circuit 15. On the other hand, the second exclusive OR circuit 14 modulates the other branched input signal sequence with the second M sequence signal and selects the second modulated input signal sequence by the selection circuit 15.
Output to. At this time, the signals input to one input terminal of the first exclusive OR circuit 11 and the second exclusive OR circuit 14 are both information signals after speed conversion, and their contents are exactly the same, but the other Since the first M-sequence signal and the second M-sequence signal input to the input terminals of the first M-sequence signal generator 10 and the second M-sequence signal generator 13 are different in number of stages, the first modulated input signal sequence and the second modulated input signal sequence are different from each other. The resulting signal is different from the input signal series. Therefore, the selection circuit 15 uses the block information output from the output terminal 7C of the speed conversion circuit 7 to select the n consecutive information bits of the first modulation input signal series and the second modulation input signal series and the information bits added thereto. At the same time as detecting the surplus bit position of 1 bit, continuous signals of the same polarity included in the n information bits are combined into the first modulated input signal sequence and the second modulated input signal sequence.
The modulated input signal sequences are compared, and information indicating which M sequence generator output was used to modulate the sequence is added to the surplus bits of the shorter signal of consecutive same polarity signal length and transmitted. It is output to the transmission line 6 as a line signal. Although the number of successive identical codes in this transmission path signal can only be determined probabilistically, the length of consecutive identical codes can be significantly shortened, and at the same time, it is possible to suppress the occurrence of consecutive identical codes themselves.

〔発明の効果〕〔Effect of the invention〕

以上詳細に説明したように、この発明に係る伝送路信号
変調方式によれば、2つに分岐した同一内容の2系列の
信号を互いに段数の異なるM系列発生器の出力でそれぞ
れ変調し、同符号連続長の短い信号系列を選択して伝送
路信号として出力することができる効果がある。
As explained in detail above, according to the transmission line signal modulation method according to the present invention, two signal streams having the same content that are branched into two are modulated by the outputs of M-sequence generators having different numbers of stages. This has the advantage that a signal sequence with a short code sequence length can be selected and output as a transmission line signal.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はこの発明に係る伝送路信号変調方式の一実施例
を示すブロック図、第2図は従来の伝送路信号変調方式
を示すブロック図である。 1・・・・入力端子、6・・・・伝送路、7・・・・速
度変換回路、8−・・・分岐回路、9・・・・第1リセ
ツト端子、1o・・・・第1M系列信号発生器、11・
・・・第1排他的論理利回路、12・・・−第2リセツ
ト端子、13・・・・第2M系列信号発生器、14・・
・・第2排他的論理和回路、15・・・・選択回路。
FIG. 1 is a block diagram showing an embodiment of a transmission line signal modulation method according to the present invention, and FIG. 2 is a block diagram showing a conventional transmission line signal modulation method. DESCRIPTION OF SYMBOLS 1...Input terminal, 6...Transmission line, 7...Speed conversion circuit, 8-...Branch circuit, 9...1st reset terminal, 1o...1st M Series signal generator, 11.
. . . 1st exclusive logic circuit, 12 . . . -second reset terminal, 13 . . . 2nd M sequence signal generator, 14 .
...Second exclusive OR circuit, 15...Selection circuit.

Claims (1)

【特許請求の範囲】[Claims] 速度変換され余剰ビットを付加した入力信号系列とM系
列信号発生器の出力信号との排他的論理和を取る伝送路
信号変調方式において、nビット毎に1ビットの余剰ビ
ットを付加するよう速度変換する手段と、この速度変換
された入力信号系列を2分岐する手段と、2分岐された
それぞれの入力信号系列と段数の異なるM系列信号発生
器の各出力信号との排他的論理和を取る手段と、この排
他的論理和が取られた出力信号の予め定めた連続するn
ビットのブロック内における連続した同一極性信号の短
い方の系列を伝送路信号として送出し、いずれの系列を
伝送路符号としたかの情報を余剰ビットに付与する手段
とを備えたことを特徴とする伝送路信号変調方式。
In a transmission line signal modulation method that takes the exclusive OR of the input signal sequence to which a surplus bit has been added after speed conversion and the output signal of an M-sequence signal generator, the speed is converted so that one surplus bit is added to every n bits. means for branching the speed-converted input signal series into two, and means for calculating an exclusive OR of each of the two branched input signal series and each output signal of an M-sequence signal generator having a different number of stages. and a predetermined consecutive n of output signals obtained by exclusive ORing.
It is characterized by comprising means for transmitting the shorter sequence of consecutive same polarity signals in a block of bits as a transmission line signal, and adding information as to which sequence is used as a transmission line code to the surplus bits. Transmission path signal modulation method.
JP63108290A 1988-04-30 1988-04-30 Transmission line signal modulation method Expired - Lifetime JPH0683191B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63108290A JPH0683191B2 (en) 1988-04-30 1988-04-30 Transmission line signal modulation method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63108290A JPH0683191B2 (en) 1988-04-30 1988-04-30 Transmission line signal modulation method

Publications (2)

Publication Number Publication Date
JPH01278142A true JPH01278142A (en) 1989-11-08
JPH0683191B2 JPH0683191B2 (en) 1994-10-19

Family

ID=14480924

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63108290A Expired - Lifetime JPH0683191B2 (en) 1988-04-30 1988-04-30 Transmission line signal modulation method

Country Status (1)

Country Link
JP (1) JPH0683191B2 (en)

Also Published As

Publication number Publication date
JPH0683191B2 (en) 1994-10-19

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