JPH01276943A - Data communication controller - Google Patents

Abstract

PURPOSE:To select a proper timing signal in response to the state of an opposite connected device by providing a supervisory means monitoring the 2nd timing signal from a data line terminator and selecting a transmission clock of a serial input/output interface in response to a monitor signal from the supervisory means. CONSTITUTION:A counter CT14 generates an internal clock having a frequency corresponding to the data transfer speed designated by a microprocessor 11. The internal clock is fed to one input of a selector SEL15. An ST2 clock from an opposite DCE is supplied to other input of the selector 15 via a driver/ receiver circuit 19. A supervisory timer 16 is set when the ST2 clock is received and reset when not received. The selector 15 selects the ST2 clock as a transmission clock used in an SIO12 when a output signal of the supervisory timer 16 is set and selects the internal clock from the counter 14 as the transmission clock when the timer 16 is reset. Thus, proper transmission in response to the state of an opposite DCE is attained.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention provides a data communication control system that includes a serial input/output interface and performs synchronous serial data communication control with a data line termination device. The present invention relates to a device, and particularly to a method for selecting a timing signal used as a transmission clock.

(Prior Art) Conventionally, in a synchronous type (SYN synchronous type, flag synchronous type, etc.) serial data communication control device represented by an RS232C interface, the STl clock (ST1 clock), which is an internal clock for determining the line data transfer rate, is used. 1 timing signal, DA double signal for R3232C, or S'T2 clock (second timing signal, DB signal for R8232C) generated by the connected device (data line termination device) as the transmission clock. The STI and Sr1 selection method (transmission clock selection method) differs depending on the connected data line termination device, but conventionally the designation of whether to use STI or Sr1 was made by a microprocessor. Generally, this was done by the programmer through control, etc., or by hardware, using straps, etc. This method could result in data errors due to incorrect transmission clock specifications, or The STl clock has to be kept in mind at all times, which complicates the setup work required to start communication.Also, the STl clock is always output for purposes such as testing transmission and reception. However, if the connection cable (line) becomes in an oven state for some reason, it may become a source of crosstalk noise from other signal lines, etc., and cause other control (in the case of multi-line control,
There was a problem that had an adverse effect on the control of other lines.

(Problems to be Solved by the Invention) As mentioned above, conventionally, the user must always be aware of the specification of the transmission clock (timing signal) to be used, and if there is a specification error, a data error may occur. There was the problem of inviting. In addition, since the internally generated transmission clock (first timing signal, STI clock) is always output to the connected device, if the connection cable becomes open for some reason, other signals may be There was a problem that it became a source of crosstalk noise such as wires.

Therefore, the problem to be solved by the present invention is to enable the user to correctly select the transmission clock (timing signal) to be used without making the user aware of it.

Another problem to be solved by this invention is an internally generated transmission clock (first timing signal).

STl clock) can be output according to the connected device and the line state, thereby preventing the clock from becoming a noise source.

[Structure of the Invention] (Means for Solving the Problems) The present invention provides a data communication control device that performs synchronous serial data communication control with a data line termination device.
a timing signal generating means for generating a timing signal (STl clock); and a second timing signal generating means for generating a timing signal (STl clock);
monitoring means for monitoring whether or not the timing signal is being received and outputting a monitoring signal indicating that; and serial processing of either the first or second timing signal according to the monitoring signal from the monitoring means The present invention is characterized in that it includes a selection means for selecting a transmission clock of an input/output interface. The present invention further provides detection means for detecting that at least one of an operable notification signal for notifying that the data line terminating device is in an operable state and a monitoring signal from the monitoring means is true; The present invention is characterized in that the transmission of the first timing signal to the data line termination device is controlled in accordance with the detection result of the means.

(Function) According to the above configuration, one of the first and second timing signals is selected as the transmission clock of the serial input/output interface in accordance with the monitoring signal from the monitoring means, so that the connection partner If the second timing signal from the data line termination device is being received, it is possible to select this second timing signal, and if not, it is possible to select the internally generated first timing signal. , an appropriate timing signal (transmission clock) can be selected according to the state of the connected device. Further, when the above-mentioned detection means is provided and the output of the first timing signal is controlled according to the detection result of the detection means, at least one of the operable notification signal from the data line termination device and the monitoring signal from the monitoring means. Since the first timing signal is sent to the data line termination device only when is true, when the line is in an open state and the ready notification signal is in a false state, the sending of the first timing signal is prohibited and the same signal is can be prevented from becoming a noise source.

(Embodiment) FIG. 1 shows a block configuration of a data communication control device according to an embodiment of the present invention. In the figure, 11 is a microprocessor that controls data transmission and reception control (line control);
13 is a serial input/output interface (hereinafter referred to as S10) that performs input/output data conversion for the line (parallel/serial conversion for transmission data and serial/parallel conversion for received data), and 13 is a buffer (BUF) for data input/output to 51012. ). 14
is the internal clock (
A counter (CT) 15 generates an internal clock from the counter 14 and a connected data line termination device (hereinafter referred to as D), which is not shown in the figure.
This is a selector (SEL) that selects either one of the ST2 clocks (second timing signals) from the ST2 clock (referred to as CE) as the transmission clock for the 5IO12.

16 is a monitoring timer (TM) that monitors reception of the ST2 clock from the connected DCE. The monitoring timer 16 is composed of, for example, a retriggerable multivibrator, and the S
For example, when a rising edge of the T2 clock is detected, the state is turned ON for a certain period T, and when the next rising edge of the ST2 clock is detected during this ON period, an additional time T is generated from the time of detection.
The ON state continues for only 2 hours. Therefore, the monitoring timer 18 is in an ON state while the ST2 clock is being received, and becomes an OFF state when the ST2 clock is no longer received due to a line disconnection or because the partner DCE has stopped outputting the ST2 clock. The output signal of the monitoring timer 16 is used as a selection control signal for the selector 15.

Reference numeral 17 indicates that at least one of an operable notification signal (data set ready signal, hereinafter referred to as DR double signal) generated by the connected DCE to notify that the DCE is in an operable state, and an output signal of the monitoring timer 16. This is a gate (Gl) that detects that it is in the on state. This gate 17 is, for example, an OR gate. 18 is counter 14
S according to the output signal of
Partner DCE as Tl clock (first timing signal)
(G2). This gate 18 is, for example, an AND gate. Reference numeral 19 is a driver/receiver circuit that meets the standards of the applicable interface.

In addition to the above-mentioned ST1 clock and ST2 clock, the signals to be input and output from this driver/receiver circuit 19 include data transmission enable that is generated by the partner DCE and indicates that the DCE is in a state in which data can be transmitted to the line. Notification signal (CS signal), data receiving notification signal (data channel reception carrier detection signal, CD signal) indicating that the DCE is receiving a valid signal from the line, DCE
The reception data (RD double signal, reception timing signal (RT double signal), and transmission data (S
There are D times signals.

Next, the operation of the configuration shown in FIG. 1 will be explained.

First, the microprocessor 11 uses a buffer (BUF) 1
3, sets each predetermined parameter data necessary for data communication in the 5IO 12, and prepares for data transmission/reception. Next, the microprocessor ti transfers data (parallel data) to the buffer 13 in accordance with the data transmission request.
Output to 5IO12 via. 5IO12 converts this data into serial data according to the transmission clock from the selector (SEL) 15, sends it as an SD double signal, and sends it to the driver/
It is output to the transmission line (SD) via the receiver circuit 19. On the other hand, data input (data reception) is performed as follows. First, the RD double signal RT on the receiving line (RD)
510 through the driver/receiver circuit 19 for both double signals.
12 is input. 81012 receives this RD-multiplied signal (serial data) in response to the RT-multiplied signal and converts it into parallel data. The microprocessor 11 has 5IO12
The parallel data converted in is input through the buffer 13.

Now, the counter (CT) 14 is the microprocessor 1
It generates an internal clock with a frequency corresponding to the data transfer rate specified by 1. This internal clock is □
It is supplied to one input of the selector (SEL) 15. The ST2 clock from the partner DCE is supplied to the other input of the selector 15 via the driver/receiver circuit 19. This ST2 clock is also supplied to the supervisory timer (TM) 1B.

As described above, the monitoring timer 1B turns on if the ST2 clock is received, and turns off if the ST2 clock is not received. If the output signal of the monitoring timer 1B is in the ON state, that is, if the ST2 clock is being received, the selector 15 selects
If the ST2 clock is selected as the transmission clock used in the 5IO12, and the output cuff signal of the monitoring timer 1B is in the off state, that is, if the ST2 clock is not received, the internal clock from the counter 14 is used as the transmission clock. select. This enables appropriate transmission depending on the state of the partner DCH.

The output signal of the monitoring timer 1B is supplied to the gate (Gl) 17 together with the DR multiplied signal from the partner DCE.

The gate 17 outputs an active signal only when at least one of the output signal of the monitoring timer 16 and the DR multiplied signal is on. The output signal of this gate 17 is the gate (G
2) Used as an enable signal for 18. gate 1
The internal clock from the counter 14 is introduced to the input of the counter 8. The gate 18 outputs the internal clock from the counter 14 as the STl clock only when the output signal of the gate 17 is active, and when the output signal of the gate 17 is not active, that is, the ST2 clock is not received and the DR multiplied signal is output. If it is off, the output of the STl clock is stopped.

As described above, according to this embodiment, if the data communication control device shown in FIG.
Depending on the status B of the ST2 clock from the CE (whether it is received or not), it is switched to either the ST2 clock or the internal clock, and output of the ST1 clock is also permitted. On the other hand, if the line becomes open due to some reason, the ST2 clock from the other DCE will be stopped and not received by the device shown in Figure 1, and the DR double signal will be turned off. , 5I012, the internal clock is used, but the output of the STl clock is prohibited. As a result, there is no possibility that the STl clock becomes a source of crosstalk noise from other signal lines when the line is open.

The various interface signals with the outside shown in Figure 1 are based on the CCITT (International Telegraph and Telephone Consultative Committee) Recommendation v, 24.
They correspond to the circuit numbers defined in Table 1 below.

Table 1 DR...Circuit number 107. Sr1...Circuit number 114STI...Circuit number 113. RT...
・Circuit number 115SD...Circuit number 103. R
D...Circuit number 104C8...Circuit number 10B, CD...Circuit number 109 [Effect of the invention] As detailed above, according to the present invention, the connection partner device Since the timing signal (transmission clock) can be appropriately selected according to the state of the clock, the user does not have to be conscious of the transmission clock selection, and it is possible to prevent problems such as data errors due to errors in clock selection specification. In addition, a second timing signal (ST
2 clock) is not received and the ready notification signal (D
When the R times signal is off, it is assumed that the line may be in an open state, and the first timing signal (
Since it is prohibited to send the STl clock to the connected partner, it is possible to prevent the same signal from becoming a source of crosstalk noise on other signal lines.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a data communication control device according to an embodiment of the present invention. 12... Serial input/output interface (810),
14...Counter (CT, timing signal generation means)
, 15... Selector (SEL), 1B... Monitoring timer (TM), 17... Gate (Gl, detection means)
, 18...gate (G2, timing signal output control means). Applicant's agent Patent attorney Takehiko Suzue Jgl Figure

Claims (2)

[Claims] (1) In a data communication control device that is equipped with a serial input/output interface that performs parallel/serial conversion of transmitted data and serial/parallel conversion of received data, and that performs synchronous serial data communication control with a data line termination device, a timing signal generating means for generating a first timing signal; a monitoring means for monitoring whether or not a second timing signal generated by the data line terminating device is being received and outputting a monitoring signal indicating that; In response to the monitoring signal from the monitoring means, the first
and selection means for selecting one of the second timing signals as a transmission clock of the serial input/output interface. (2) Detection for detecting that at least one of the operable notification signal generated by the data line terminating device to notify that the device is in an operable state and the monitoring signal from the monitoring means is true. and timing signal output control means for outputting the first timing signal to the data line termination device according to the detection result of the detection means. Device.