JPH01273140A - Emergency operation circuit - Google Patents

Abstract

PURPOSE:To prevent the system constitution from being fixed even if one holing means in a duplexed EMA circuit causes a fault by generating an emergency operation state value of each system by selecting alternately a holding means of the own system which is inverted at every emergency operation processing and holds a value for determining a new system constitution, and the same holding means of the other system. CONSTITUTION:A holding means is inverted at every emergency operation processing and holds a value for determining a new system constitution, and a value held by this holding means is informed to an EMA circuit 2 of the other system by a value transmitting terminal H1. Also, a value held by the holding means of the EMA circuit 2 of the other system is inputted by a value receiving terminal H2, a selecting circuit 20-1 selects alternately the value held by the holding means of the own system and the value held by the holding means of the other system, and a generating circuit generates an emergency operation state value of the own system from this selected value and the system number of the own system. In such a way, even if one holding means in the duplexed EMA circuit causes a fault, it is prevented that the system constitution is fixed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an emergency operation circuit that performs an emergency control operation on a duplex processing device.

[Conventional technology]

In general, in a duplex processing device that is made up of a 0-system processing device and an I-system processing device, when an abnormality occurs in the processing device, the system type, operation type, and system initialization are performed, and the system is operated. guarantees continuity. Here, the system type is processing system (ACT system), standby system (SBY
(system), and the operation type refers to synchronous operation or asynchronous operation.

By the way, system reconfiguration of a duplex processing device is normally performed by internal means operated by an instruction from outside the device or an internal clock, but apart from this internal means, if an abnormality occurs within the device, The emergency operation (EMergenc) is a circuit that detects a situation where the method cannot be executed and autonomously reconfigures the system type and initializes the system.
yAction circuit.

There is a circuit (hereinafter referred to as EMA).

Conventionally, as shown in FIG. 3, the mounting unit PB3
An EMA circuit 5 is provided on the mounting unit PB5 independently of the redundant processing device composed of the 0-system processing device 3 above and the 1-system processing device 4 on the mounting unit PBd, and this EMA circuit 5 allows both systems to be connected to each other. The system was configured to monitor abnormalities in the processing devices 3.4 and execute emergency control operations when an abnormality occurs.

[Problem to be solved by the invention]

As mentioned above, conventionally, only one HMA circuit is provided for a duplex processing device, so the EMA
If the circuit itself were to fail, there was a risk that the system would be completely unable to recover.

Furthermore, since only one EMA circuit is provided, replacement and maintenance of the HMA circuit while the system is in operation is difficult and dangerous.

Furthermore, since the EMA circuit is configured as a separate system from the redundant processing device, even if the EMA circuit itself is miniaturized through LSI, etc., it is configured as an independent system for hardware, so the system as a whole requires a lot of hardware. I needed it.

These conventional problems can be solved by duplicating the EMA circuit. That is, for a duplex processing device that is duplicated into a 0-system processing device and a 1-system processing device, S! A 0-system EMA circuit that executes emergency operation processing and an I-system EMA circuit that is implemented in the same mounting unit as the 1-system processing device and executes emergency and operation processing for the 1-system processing device are provided, and these 0-system EMA circuits If the configuration is such that the emergency control operation of the duplex processing device is performed by the 1-system EMA circuit and the
Since the circuit is mounted in the same way as each processing device, the overall amount of hardware is reduced, and the EMA circuit is duplicated, so even if one HMA circuit fails, the other HMA circuit can perform the minimum emergency control operation. possible and maintenance of the EMA circuit,
Replacement is also easy.

By the way, in the emergency operation control by the EMA circuit, the system configuration is changed, that is, the processing system and the standby system are switched.

In the conventional system where there is only one HMA circuit, there is only one means for holding a value for determining a new system configuration, and new system configurations for both systems are determined based on that value. Therefore, if the holding means fails, the system configuration becomes fixed.

On the other hand, when the EMA circuits are duplicated, each HMA circuit can be provided with a means for holding the value that determines the new system configuration, but in that case, each EMA circuit can only follow the value of its own holding means. When operating, the same problem as in the case of singlexing occurs.

SUMMARY OF THE INVENTION An object of the present invention is to provide an HMA circuit that can prevent the system configuration from becoming fixed even if any of the holding means in the duplicated EMA circuit fails.

[Means to solve the problem]

In order to achieve the above object, the EMA circuit of the present invention has the following features:
In emergency, operational circuits with redundant configurable functions,
A holding means for holding a value that is inverted every time an emergency operation process is performed in the own system and determining a new system configuration, a value transmission terminal for notifying the value held by this holding means to the EMA circuit of the other system, and a value transmitting terminal for notifying the EMA circuit of the other system a value receiving terminal for receiving the value held by the holding means of the EMA circuit; a selection circuit for alternately selecting the value held by the holding means and the value received at the value receiving terminal; From the value and the system number of the own system, the emergency 2 of the own system,
and a generation circuit that generates an operating state value.

[Effect]

In the EMA circuit of the present invention, the holding means is the self-system S!
A value that is inverted every time a sudden action process is performed and determines a new system configuration is held, and the value held by this holding means is notified to the HMA circuit of the other system through a value transmission terminal, and the holding means of the HMA circuit of the other system is The value to be held is input through the value receiving terminal, the selection circuit alternately selects the value held by the holding means of its own system and the value held by the holding means of the other system, and the generation circuit selects this selected value and the value held by the holding means of the other system. The emergency operation state value of the own system is generated from the system number of the system.

〔Example〕

Next, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a pronk diagram showing an example of a duplex processing system to which the EMA circuit of the present invention is applied. In the same figure, 1
1 is a 0-system EMA circuit, and 3 is a 0-system processing device, which are mounted in the same mounting unit FBI and operate with the same power supply. Further, 2 is a 1-system EMA circuit, and 4 is a 1-system processing device, which are also mounted in the same mounting unit PB2 and operate with the same power supply. 0 system EMA circuit 1 is 0 system processing device 3
The 1-system EMA circuit 2 performs an emergency control operation for the 1-system processing device 4.

And both HMA circuits 1.2 synchronize the emergency control operation,
Various types of information are exchanged to ensure system changes and to monitor other systems.

FIG. 2 is a block diagram of an embodiment of the 0-system EMA circuit 1 and the 1-system EMA circuit 2, with both HMA circuits l.

2 have the same configuration. In FIG. 2, 10-1.
10-2 is HMA sequencer, 11-1゜11-2 is E
MA counter, 12-1.12-2 is soft ink face section, 13-1.13-2 is HMA sequencer monitoring circuit, 14-1.14-2 is power processing section, 15-1.1
5-2 is EMA factor monitoring circuit, 16-1.16-2 is H
MA processing drive circuit, 17-1.17-2 is 1 bit E
MA state counter, 18-1.18-2 is OR circuit, 19-1.19-2 is AND circuit, 20-1.20
-2.21-1.21-2 is selector, 22-1.22
-2 is the inverter, A1 is the operating status transmitting terminal of the HMA sequencer 10-1, A2 is its receiving terminal, B2 is the EMA
Operation status transmission terminal of sequencer 1O-2, B1 is its reception terminal, C1 is count value transmission terminal of EMA counter 11-1, C2 is its reception terminal, B2 is EMA counter 1
1-2 count value transmitting terminal, Dl is its receiving terminal, E
l, B2 are selector control signal transmission/reception terminals, Fl is an initialization completion transmission terminal, F2 is its reception terminal, G2 is its initialization completion transmission terminal, G1 is its reception terminal, Hl is a system decision value output terminal, and F2 is its reception terminal. Terminal, ■2 is system decision value output terminal, 1
1 is its receiving terminal. Note that the corresponding terminals are connected by wiring, respectively.

In the 0-system EMA circuit 1, the 0-system processing device 3 receives EMA.
When a prisoner in need occurs, it is detected by the EMA factor monitoring circuit 15-1.
is detected, and the EMA sequencer 10-1 is activated.

When activated, the HMA sequencer 10-1 operates the EMA processing drive circuit 16-1 to start a series of EMA sequences for the 0-system processing device 3. That is, normally, changes in the operating mode, separation from other systems, stopping of the processor, updating of the values of the EMA counter 11-1 and HMA state counter 17-1, changes in the system configuration, and It controls a series of sequences such as reset, run of the processor, and initialization by software on the 0-system processing unit 3.

The 1-system EMA circuit 2 also operates in the same manner as the 0-system EMA circuit 1.

During the above EMA processing, the EMA counter 11-1.
The EMA cow collar 11-2 is counted up by a signal applied to the up terminal UP from the EMA sequencer 10-1 and 10-2 for each EMA process, and is counted up based on the value of the zero counter on the O yarn processing device 3 and the 1 system processing device 4. The initialization level performed by the software is determined. Therefore, both EM
The A counters 11-1 and 11-2 must show the same value in both systems. For this reason, the following configuration is adopted in this embodiment.

First, when the power of the own system is turned on while the power of the other system is turned off, the EMA counter of the own system is cleared and becomes the same clear state as the EMA counter of the other system. That is, when the 1st system EMA circuit 2 is powered off, the EMA counter 11-2 is cleared, and the count value transmission terminal D2. Its receiving terminal D1
For example, ; is input to the input terminal IN of the EMA counter 11-1 through the input terminal IN of the EMA counter 11-1. When the O system EMA circuit 1 is powered on in this state, 1'' is applied to the set terminal SET of the EMA counter 11-1 from the $ source processing unit 14-1 via the OR circuit 18-1, and the EMA counter The contents of 11-1 become zero.When the power of 0 system EMA circuit 1 is turned off, 1 system E
Similarly, when the MA circuit 2 is powered on, the l-system EMA
EMA counter 11-2 of circuit 2 is cleared.

Also, if the power of the own system is turned on while the power of another system is turned on,
The same value as the HMA counter value of the other system is set in the EMA counter of the own system. That is, if the value of the EMA counter 11-2 is "a" when the 1st system EMA circuit 2 is powered on, that value is transmitted to the count value transmission terminal D2. The input terminal IN of the EMA counter 11-1 passes through the receiving terminal D1.
74 of O-system EMA circuit 1 in this state.
When the power is turned on, the OR circuit 1 is output from the power processing section 14-1.
A cent signal is sent to the EMA counter 11-1 via the EMA counter 8-1, and "a" is set in the EMA counter 11-1.

Furthermore, when HMA processing is executed, the next EM
In order to maintain continuity in the initialization level of the A process, upon completion of initialization, a system that has been successfully initialized transfers its own EMA caulkal value to the partner system. That is, if the 0 system has been successfully initialized, the software of the 0 system processing device 3 notifies the soft ink face section 12-1 of this fact, and the soft ink face section 12-1 responds to this. Initialization completed transmission terminal Fl, reception terminal F2. 1'' through the OR circuit 18-2 to the set terminal SET of the EMA counter 11-2.
Therefore, E, which is applied to the EMA counter 11-2 via the count value transmitting terminal CI and the receiving terminal C2, is added to the EMA counter 11-2.
The count value of MA counter 11-1 will be set.

Next, a circuit configuration for ensuring that the operations of the duplicated MA circuits proceed simultaneously in both systems will be described.

Referring to FIG. 2, the operating status of the EMA sequencer 10-1 of the O-system EMA circuit 1 is notified to the own system's EMA sequencer monitoring circuit 13-1, and the operating status transmission terminal A
I, the EMA sequencer monitoring circuit 13-2 of the l-system EMA circuit 2 is notified via the reception terminal A2, and conversely, the l-system E
The operating status of the EMA sequencer 10-2 of the MA circuit is notified to the EMA sequencer monitoring circuit 13-2 of its own system, and the operating status transmission terminal B2. The EMA sequencer monitoring circuit 13-1 of the O-system EMA circuit is notified via the reception terminal B1. HMA sequencer monitoring circuit 13-1.13
-2 monitors the operation status added from EMA sequencers 10-i and 10-2, and when it detects that a formal mismatch has occurred in HMA processing between its own system and other systems, it sends a message to that effect via a software interface. The software/ink face unit 12-1.12-2 sends this information to the software on the O-thread processing device 3.1 system processing device 4 or to a maintenance person (not shown). Notify the machine interface device. Therefore, by setting this notification as an opportunity for re-EMA processing of the software, the HMA processing can be automatically repeated until the HMA processing is performed normally, or by serving as a warning to the maintenance personnel, prompt action can be taken. becomes possible.

As mentioned above, BMA processing usually involves changing the operating mode, separating from other systems, stopping the processor, updating the HMA cow color value and EMA state value, changing the system configuration, resetting, running the processor, It consists of a series of sequences such as initialization processing by software.

Therefore, HMA sequencer monitoring is performed by notifying pulses to the EMA sequencer monitoring circuits of both systems for each of the above processes, and checking whether the count values are equal in both systems or whether the final stage of HMA processing has been reached. E of both systems
This can be done by notifying the MA sequencer monitoring circuit and determining whether both systems have reached the final stage at the same time.

Next, a circuit configuration for reliably changing the EMA state value that determines a new system configuration for each EMA process even if one of the EMA state counters fails during HMA operation will be described.

Referring to FIG. 2, the EMA state counter 17-1 of the 0-system EMA circuit 1 is counted and amplified by the signal applied to the up terminal UP from the EMA sequencer 10-1 every time HMA processing is performed, and the EMA state counter 17-1 of the 0-system EMA circuit 1 is - The counter 17-2 is counted up by a signal applied to the up terminal UP from the EMA sequencer 10-2 every time EMA processing is performed. And these EMA states
Since the counters 17-1 and 17-2 are 1-bit counters, the values are inverted alternately by O and l each time HMA processing is performed. Also, the EMA state counter 17-1
The output of the OR circuit 18-1 is connected to the set terminal SET of E.
The output of the OR circuit 18-2 is applied to the cent terminal SET of the MA state counter 17-2. Therefore, E of both systems
The MA state counters 17-1 and 17-2 are set to EMA state counters 17-1 and 17-2 of the other system when the power of the own system is turned on or when the initialization process of the other system is completed.
The value of the state counter is transferred, and the values of the EMA state counters 17-1 and 17-2 of both systems will show the same value.

The value of EMA state counter 17-1 is determined by selector 20.
-1 is manually inputted to the a terminal, and the system decision value transmission terminal 12
The value of the EMA state counter 17-2 is input to the a terminal of the selector 20-2 via the receiving terminal H2, and the value of the EMA state counter 17-2 is input to the b terminal of the selector 20-2, and the system decision value transmitting terminal 12. b of selector 20-1 via
input to the terminal. The selector control terminal S of the selector 20-1 and 20-2 includes an AND circuit 19-1 that performs a logical AND operation between the value of the second lower bit of the count value of the EMA counter 11-1 and the system number "0"; An OR condition signal is added to the output of an AND circuit 19-2 which takes the logical product of the second lower bit of the count value of the EMA counter 11-2 and the system number "1".

Here, since the output of the AND circuit 19-1 to which the system number "O" is added is always "0", the selectors 20-1, 20-
The selector control terminal S of 2 has an EMA counter 11-2.
Each time the state of the second lower bit of the count value is added.

The selector 20-1, 20-2 has a selector control terminal
When the selector control signal is "0", a inputs are selected and output, and when the selector control signal is "1", b inputs are selected and output. The output of selector 20-1, 20-2 is directly sent to selector 21-
1. Input to terminal a of 21-2 and inverter 2
2-1.22-2 inverts selector 21-1.21
-2 is input to the b terminal. Selector 21-1.21-
System numbers rQJ and r1 are added to the selector control terminals S of No. 2, respectively. Therefore, the selector 21-1 always selects and outputs the value of the a terminal, which becomes the θ-system HMA state value. Further, the selector 21-2 always selects and outputs the value of the b terminal, which becomes the EMA state value of the 1st system.

Now, if the values of the EMA state counters 17-1 and 17-2 are both "O" and the value of the second lower bit of the count value of the EMA counter 11-2 is "0", then the selector 2
0-1.20-2 is the value of a inputs, that is, the EMA of O system
The value "0" of the state counter 17-1 is selected, and the O-system EMA output from the selector 21-1
The state value is "0", and the EMA state value of $1 output from the selector 21-2 is "1". Also, EMA
Assuming that the process is performed once, the value of the EMA state counter 17-1.17-2 is inverted and becomes "1", and becomes 0.
The system's EMA state value is "1".

The EMA state value of system 1 becomes "0". When EMA processing is performed one more time, the EMA state counter 17
-1. The value of 17-2 is inverted and becomes "0", and the second lower bit of the count value of EMA counter 11-2 becomes "1", so the output of AND circuit 19-2 becomes "1". As a result, the selector 20-1, 20-2 selects the value of the b terminal, that is, the value "0" of the 1-system EMA state counter 17-2, and the 0-system EMA state value is rQ, 1
The system's EMA state value is "1", and in this way, the polythread's EMA state value is "0" for each EMA process.

"1" changes alternately.

In addition, as mentioned above, the EMA state counter 1 of the 0 system
Since the EMA state counter 7-1 and the 1-system EMA state counter 17-2 are used alternately, even if one of the EMA state counters fails, the EMA state value of the multiple threads will be fixed. disappears. As a result, it is possible to prevent the EMA-treated yarn configuration from being fixed, initialization failure, and system failure.

In Fig. 2, AND circuits 19-1 and 19-2 are provided that manually input the system numbers, and only the counter of one of the two HMA counters is used, and depending on the value of this counter, EMA state counter 17-1 for both systems
．． 17-2 are used alternately. The reason for using only one HMA counter in this way is that the probability that both the EMA counter and the EMA state counter will fail at the same time is low, and that the EMA counters 11-1.
11-2 can be monitored by monitoring its value externally via the soft ink face section 12-1.12-2. In addition, in this embodiment, the means for holding the value that determines the EMA state is a 1-bit EMA.
Although this was implemented using a state counter, it may also be implemented using a flip-flop.

As described above, in this embodiment, the EMA circuit, which has not been duplicated as a separate system from the conventional duplex processing device, is provided with various monitoring circuits, synchronization of the EMA processing state, and means for ensuring changes in the EMA processing yarn. This makes it possible to include the HMA circuit within the processing system without having it as a separate system, and the fault tolerance can be improved compared to conventional EMA circuits that are not duplexed.

〔Effect of the invention〕

As explained above, the EMA circuit of the present invention alternately selects the holding means of the own system that holds a value that is inverted and determines a new system configuration every time an emergency operation process is performed, and a similar holding means of the other system. Since the operation status HM is generated for each prefecture, even if any of the holding means in the duplicated EMA circuit fails, the system configuration can be prevented from becoming fixed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of a duplex processing system to which the HMA circuit of the present invention is applied, FIG. 2 is a block diagram of one embodiment of the HMA circuit, and FIG. 3 is a block diagram of a conventional example. In the figure, l...0 system EMA circuit 2...1 system EMA circuit 3...0 system processing device 4...1 system processing device 10-1.10-2...HMA sequencer 11-1
．． 11-2...EMA Kaukakara 12-1.12-2.
...Soft interface section 13-1.13-2...
・EMA sequencer monitoring circuit 17-1.17-2...
EMA state counter 20-1.20-2.21-
1.21-2...Selector

Claims (1)

[Scope of Claims] An emergency operation circuit having a function capable of being configured with redundancy, comprising: holding means for holding a value that is inverted every time emergency operation processing is performed in its own system and determining a new system configuration; and a value held by the holding means. a value transmission terminal for notifying an emergency operation circuit of another system; a value reception terminal for receiving a value held by a holding means of the emergency operation circuit of another system; and a value held by the holding means and the value reception. It is characterized by comprising a selection circuit that alternately selects the value received at the terminal, and a generation circuit that generates an emergency operation state value of the own system from the value selected by the selection circuit and the system number of the own system. emergency operation circuit.