JPH01272148A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To conduct guarantee to the sudden washing-away of charges from a nodal point at a high level, and to obtain more stable static operation by using a TFT as active block to a resistor as passive block. CONSTITUTION:When a high level is written to a nodal point A and a low level to a nodal point B from the outside, only a MOSFET N2 is conducted, and other N1, TN1 and TN2 are not conducted. Consequently, the nodal point B continues to be discharged at ground potential through the N2, and the nodal point A is detached from both VDD and GND and the high level is held. When the charges of the nodal point A suddenly washes away by alpha-rays at that time, the charges of a gate electrode C are discharged with the time later than the nodal point A by a certain value by a resistor R1 and a capacitance C1. Accordingly, potential difference is generated between the source (the nodal point A) of the TFTT N1 and the gate (electrode C), the TFTT N1 is conducted and the nodal point A is supplied with charges from VDD, and the breaking of information is prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to the construction of semiconductor memory devices, and particularly to the construction of memory cells for static RAM (RAM).

[Prior art] Field effect transistor (hereinafter referred to as MOSFET)
The circuit of the static RAM memory cell using
The circuit shown in the figure is the mainstream. In FIG. 4, the sources of N-channel MOSFETs NI1 and N12 are connected to a ground potential (denoted as GND). N channel M
Drain of O9FETNI 1 and N-channel MOS
The gates of FETNi2 are commonly connected at node A2, and N
The drain of channel MOSFET N12 and the gate of N-channel MOSFET N11 are commonly connected at node B2. Node A2. Resistors R11 and R12 are connected between B2 and a power supply (denoted as VDD), respectively.

In addition, there is an N-channel MOS between node A2 and the bit line.
FETN13 is connected to N-channel MOSFETN14 between node B2 and bit line D (over par),
A word line W is connected to the gates of N-channel MOSFETs N13 and N14. FIG. 5 is a plan view showing an example of the layout when the circuit shown in FIG. 4 is created on a semiconductor substrate.

301 is the source of N-channel MO3FET NI 1,
An N-type region 30.2 is formed on the single-crystal silicon substrate as a train, and 30.2 is an N-type region formed of the first polycrystalline silicon.
This is the gate electrode of channel MO5FET NII. 3
03 is an N-channel MOSFET N12. This is an N-type region N14, and 304 is a gate electrode of an N-channel MOSFET N12 formed of the first polycrystalline silicon layer.

305 is an N-type region that becomes N-channel MOSFET N13, and 306 is N-channel MOSFET N13.
This is a word line W formed of a first polycrystalline silicon layer which becomes a gate electrode of N14.

A dotted line 307 is a region connecting the N-type region and the first polycrystalline silicon layer. 311 and 312 are each resistor R11
, R12, and 3]3
is a region connecting the first and second polycrystalline silicon layers. VDD, GND or bit line in Figure 4,
The connection with D (over par) is omitted because it is not a truly important part in the present invention, which will be described later.

The example shown in Figures 4 and 5 is called a load resistance type cell, and the memory operation is maintained using an N-channel MOSFE.
TNII and resistor R1, N-channel MOSFET N12
This is performed using the resistance ratio of the resistance R2 and the resistance R2. In general, the resistance value of an N-channel MOSFET is on the order of kiloohms (KΩ) when the gate electrode is at a high level (same potential as VDD) and conductive, and when the gate electrode is at a low level (same potential as GND). When it is in a non-conducting state, it is on the order of several hundred teraΩ (TΩ). The resistors R1 and R2 are designed to be approximately mega ohms (M Ω) to giga ohms (G Ω).

Now, node A2 is at a high level from the outside, and node B2 is at a high level.
Suppose that is written to a low level, the level of node B2 makes the N-channel MOS F E TNil non-conductive, and node A2 can be seen as being connected to VDD by resistor R1, and node A2 is held at high level. be done. The N-channel MOSFET Nl2 becomes conductive depending on the level of the node A2, and the level of the node B2 is determined by the resistance ratio of the N-channel MOSFET N12 and the resistor R1, and as described above, the resistance value of the resistor R2 is the MOS when conductive.
Since the resistance value is three orders of magnitude larger than the resistance value of the FET, the node B2 is held at a potential extremely close to GND.

[Problems to be Solved by the Invention] In the conventional example described above, the node 82 side at the II LIT level is connected to V by the resistor R2 and the N-channel MOSFET N12.
A DC path is formed between DD and GND, and its power consumption is approximately determined by resistor R2. Therefore, the resistors R1 and R2 are designed to have high resistance in order to reduce power consumption. For example, in the recently announced 1 megabit SRAM, several thousand Ω
~ Several TΩ. Next-generation large-capacity memories will require even higher resistance to reduce power consumption. Therefore, the resistance value is very close to the resistance value when the MOSFET is non-conducting, and in the example shown in Figure 4, when charge suddenly flows away from node A2 due to external noise or alpha rays, charging from VDD is stopped by resistor R1. This has the disadvantage that the stored information will be destroyed. Furthermore, in the actual manufacturing of the device, there is a drawback that it is technically difficult to manufacture extremely high resistance in the polycrystalline silicon layer as shown in FIG. 5, 311 and 312.

[Differences between the invention and the prior art] In contrast to the conventional static RAM memory cell described above, the present invention uses an active element instead of a resistor to prevent sudden charge loss caused by α rays from high-level nodes. The difference is that it provides guarantees and enables static operation. It is also relatively easy to manufacture compared to resistors.

[Means for Solving the Problems] The gist of the present invention is to provide first and second field effect transistors of one conductivity type formed on a semiconductor substrate, and a third field effect transistor of one conductivity type formed on a silicon thin film. and a fourth field effect transistor, gate electrodes of the first and fourth field effect transistors are commonly formed of a first conductive layer, and gate electrodes of the second and third field effect transistors are formed in common. are commonly formed in a second conductive layer, the sources of the first and second field effect transistors are connected to a first power supply, and the drains of the third and fourth field effect transistors are connected to a second power supply. a first node that connects the drain of the first field effect transistor and the source of the third field effect transistor; a first node that connects the first node and the second conductive layer; a resistor element, a second node connecting the drain of the second field effect transistor and the source of the fourth field effect transistor, and connecting the second node to the first conductive layer. and a second resistive element.

[Example] Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a circuit diagram showing a first embodiment of the present invention. N1
~N4 is an N-channel MO9 formed on a semiconductor substrate
FET, GND, word line W, bit line, D(
(over par) or the connections with nodes A and B are Nll-N14, GND, W, D, in Figure 4.
D (over par) or the same as A2 and B2. The characteristics of Figure 1 are VDD and nodes A2 and B in Figure 4.
In place of the resistors R11 and R12 connected between the N-channel thin film transistor (Thin
Film Transistor (hereinafter referred to as TFT) TNI and TN2 were used, and a resistor R1 was inserted between nodes A and N2 and the gate electrode C of TNI, and a resistor R2 was inserted between nodes B and Nl and the gate electrode of TN2. It is. Capacitors ff1c1. attached to gate electrodes C and D. Although C2 is a parasitic capacitance such as a gate capacitance, a capacitive element can be provided separately.

The operation of the circuit according to the present invention shown in FIG. 1 is that if a high level is written to node A and a low level is written to node B from the outside, only MOS FET N2 becomes conductive, and the other Nl, TNI, TN2 becomes non-conductive.

As a result, node B continues to be discharged to the ground potential through N2, and node A is disconnected from both VDD and GND and is held at a high level.

Here, when the charge at the contact A is rapidly dissipated due to α rays or the like, the charge at the gate electrode C is discharged with a certain delay from the node A by the resistor R1 and the capacitor ff1c1. Therefore, a potential difference occurs between the source (node A) and gate (electrode C) of TPTTN1, and TFTTN1 becomes conductive, causing VD
Charge is supplied from D to node A to prevent information from being destroyed.

Next, a layout for fabricating this embodiment on a semiconductor substrate will be explained. FIG. 2A is a plan view showing the layout, and FIG. 2B is a sectional view taken along the line xx' in FIG. 28. In the figure, 1 is single crystal silicon that becomes the N-channel MO5FETNI.

N-type region formed on the substrate, 2 is N-channel MO5
A polycrystalline silicon layer 3 serves as the gate electrode of FETNI and TFTTN2, and 3 is an N-channel MOSFETN2. N
4 is the N-type region, 4 is the N-channel MOSFET N2
and a polycrystalline silicon layer which becomes the gate electrode C of TFTTNI, 5 an N-type region which becomes an N-channel MOSFET N4, and 6 an N-channel MOSFET N3. A word line W formed of a polycrystalline silicon layer serves as a gate electrode of N4.

7 is a region connecting the N-type region and the polycrystalline silicon layer, 8 is a silicon thin film that becomes TPTTN2, and 9 is a silicon thin film that becomes TFTTNI. 8 and 9 are respectively provided on the polycrystalline silicon 2.4 with a thin insulating film serving as a gate insulating film interposed therebetween, as shown in FIG. 2B. Reference numeral 10 denotes a connection region between the polycrystalline silicon layer and the silicon thin film, and has a shape in which three different layers are connected to each other at the same time. 11 is a high resistance region provided in a part of polycrystalline silicon 2 and 4;
12 is an insulating layer that separates the N-type regions from each other.

In Figures 2A to 2B, a and b are TFTTN
I, the channel region of TN2. In forming a and b, as shown in Figure 2B, a silicon thin film is on the gate electrode, so when forming the source and drain of TPT, an impurity diffusion blocking material such as photoresist is formed on the channel region. However, by forming the channel region over a larger area than the lower electrode, leakage current during non-conduction can be reduced.

FIG. 3A is a plan view showing the layout of a second embodiment of the present invention, and FIG. 3B is a sectional view taken along line xx' in FIG. 3A. Third
201 to 209.211, 21 in Figure A to Figure 3B
2. c and d are 1 to 9 in FIGS. 2A to 2B, respectively.
11. 12. Corresponds to a and b. The feature of this embodiment is that a silicon thin film is provided under the polycrystalline silicon layer as shown in FIG. 3B. Therefore, a connection region 213 between the N-type region and the silicon thin film and a connection region 214 between the silicon thin film and the polycrystalline silicon layer are newly added.

In this embodiment, when forming the TPT channel C2d, the source and train regions can be formed in a self-aligned manner using polycrystalline silicon as an impurity diffusion blocking material, and the manufacturing process can be simplified compared to the first embodiment. There are advantages.

[Effects of the Invention] As explained above, the present invention uses TPT, which is an active blocking method, in contrast to the conventional passive blocking resistor.
It is possible to guarantee against sudden charge loss from high level nodes and obtain more stable static operation.

Further, since the resistance block does not need to have extremely high resistance as in the conventional example, it can be manufactured more easily than the resistance block in the conventional example.

Note that the silicon thin film serving as TPT may have any crystallinity.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention, FIG. 2A is a plan view showing a layout when the first embodiment is created on a semiconductor substrate, and FIG. 2B is a line x-x in FIG. 2A. Fig. 3A is a plan view showing the layout of the second embodiment of the present invention, Fig. 3B is a sectional view taken along the line xx' in Fig. 3A, Fig. 4 is a circuit diagram of the conventional example, and Fig. 5 FIG. 2 is a plan view showing a layout when a conventional example is created on a semiconductor substrate. N1~N4°Nil~N14...N channel MO9FET. TNI, TN2...Silicon thin film transistor, R1
, R2, R11, R12...resistive element, CI, C2
...Capacity, A, B, A2. B2... Node, C, D... Gate electrode, VDD... Power supply, W... Word line, D, D (
Over par)...Bit line, 1, 3. 5.
201°203, 205. 301゜303.305・・・・・・N-type region, 2, 4
．． 6. 202°204, 206. 302°304.306... Polycrystalline silicon layer, 7.
207,307...Connection region between N-type region and polycrystalline silicon layer, 8.9,208,209...Silicon thin film, 10.2
14... Connection region between silicon thin film and polycrystalline silicon layer, 213... Connection region between N-type region and silicon thin film, 11
．． 211... High resistance region provided in polycrystalline silicon layer, 12.212... Insulating layer, 311.312... Second polycrystalline silicon layer serving as resistance, 313... 311 and Connection area between 302, 312 and 303, a, b, c, d...TFT channel area. Patent applicant: NEC Corporation Representative Patent attorney Kiyoshi Kuwai - Figure 1 Figure 2A Figure 2B Figure 3A Figure 4 Figure 5

Claims (1)

[Claims] The first field effect transistor is composed of first and second field effect transistors of one conductivity type formed on a semiconductor substrate, and third and fourth field effect transistors of one conductivity type formed on a silicon thin film. and the gate electrode of the fourth field effect transistor is formed in common with the first conductive layer, and the gate electrode of the fourth field effect transistor is formed in common with the first conductive layer;
The gate electrodes of the first and second field effect transistors are commonly formed in a second conductive layer, the sources of the first and second field effect transistors are connected to the first power supply, and the gate electrodes of the third and fourth field effect transistors are connected to the first power supply. A drain of the field effect transistor is connected to a second power supply, a first node connects the drain of the first field effect transistor and the source of the third field effect transistor, and the first node and the a first resistive element connecting the second conductive layer; a second node connecting the drain of the second field effect transistor and the source of the fourth field effect transistor; and the second node and a second resistive element connecting the first conductive layer and the first conductive layer.