JPH01271995A - Memory reading circuit - Google Patents

Abstract

PURPOSE:To obtain a memory reading circuit to stably read data by providing a precharge detecting circuit to detect large current supply to a bit line and a circuit to receive the detected signal of the precharge detecting circuit and temporarily hold a potential. CONSTITUTION:When bit lines 7 and 8 are switched, and large current is supplied from a sense circuit to the bit lines, a precharge detecting circuit 11 operates a holding circuit 12 between an output circuit 4 and an amplifying circuit 3, holds the data state of the output circuit 4, which is the one before the sense circuit supplies the large current, and simultaneously separates the amplifying circuit 3 and the output circuit 4. When the potentials of the bit lines 7 and 8 become higher, and the current supplied to the bit lines is reduced, the precharge detecting circuit 11 detects this, makes the holding circuit 12 into an OFF state, and links the amplifying circuit 3 and the output circuit 4. When the sense circuit is charged, the output circuit 4 is held and separated from a front step circuit, and when the charging of the sense circuit is completed, the holding is released, and the output circuit 4 is linked with the front step circuit. Thus, a meaningless deflection in the output circuit 4 can be suppressed, and the data can be read stably.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a memory read circuit that is used in a read-only memory device and is capable of stable reading with little circuit-generated noise.

[Conventional technology] FIG. 3 shows a conventional memory read circuit.

N8, N' (N-channel type MOS transistors) are transistors for selecting bit lines 7 and 8, and output signals c and c' of a bit line selecting decoder are applied to the gates thereof.

N,, N',, Nss N's (N-channel type M
OS transistor) is a memory cell transistor, and its gate receives word line selection decoder output signals wL, w'
L is applied.

The circuit consisting of P3, p* (p-channel type MOS transistor) and N1, N2 (n-channel type MOS transistor) is a sense circuit, P.

are memory cell transistors N4, N'4, N5, N'
N, which has the function of detecting the current of g, is a switching transistor which, in combination with a feedback circuit consisting of P2 and N2, has the function of keeping the potential of the bit line 7.8 constant.

The minute signal detected at Pl is amplified by amplifier 3 to a signal at power supply potential level 1 and ground potential level 2, and is outputted to an external terminal via an output circuit 4 having sufficient driving ability.

Now, C and WL are at power supply potential, C', WL', and B L' are at ground potential, and memory cells N4 and N'4 are transistors with no current capability (data 0 storage cell) even if the gate and drain potentials are sufficient. ).

Assume that C changes from the power supply potential to the ground potential, and C' changes from the ground potential to the power supply potential. A potential change diagram at each node at that time is shown in FIG. 4, where the vertical axis represents voltage and the horizontal axis represents time. In FIG. 4, VB is a potential indicating a boundary in which when the potential of the node 10 is above this value, the output data is 0, and when it is below this, the output data is 1.

Since the bit line 8 has no potential, the bit line 9 is set to lower the potential.
The potential of N+ increases and a large current is supplied to the bit line 8 from N+. Since Nl is connected to the power supply potential via Pl, it is necessary to provide a sufficient potential difference between the source and the gate/drain of Pl to correspond to the current. Therefore, the potential of 10 is lower than VB.

When bit line 8 rises in potential, 9 falls and the current supply from N1 to bit line 8 gradually decreases.
The potential at point 10 also rises above VB again.

Finally, the potential of each node becomes the same as before the second series of changes (except for bit line 8, which had no potential before)
, This series of changes causes the output circuit to swing in the opposite direction. In the conventional circuit, this is the only case in which the output circuit is swung in the opposite direction at one end.

The fact that an output circuit with a large current capacity operates is surprising for other circuits, especially sense circuits with small operating amplitudes. Movement of the output circuit must be minimized.

[Problems to be Solved by the Invention] In the circuit shown in FIG. 3, when the bit line is switched, the data transitions from 0 to 0, and the destination bit line has no potential, the output circuit moves in the opposite direction at one end.

An object of the present invention is to solve the above-mentioned problems.

[Means for Solving the Problem] One end of a switching transistor is connected to the drain of a memory cell transistor, the other end is connected to one end of a current detection transistor, and the other end of the current detection transistor is connected to a power source. a sense circuit configured of a feedback transistor circuit connected to each other and whose input is the drain of the memory cell transistor and whose output is the gate potential of the switch transistor; an amplifier circuit that amplifies the output of the sense circuit in terms of potential; and the amplifier circuit. A memory read circuit comprising an output circuit that outputs an output of a bit line to an external terminal, the precharge detection circuit detecting that a large current is supplied from the sense circuit to the bit line to precharge the bit line; A memory read circuit consisting of a holding circuit that receives a detection signal from a detection circuit and temporarily holds a potential.

[Function] When the bit line is switched and a large current is supplied from the sense circuit to the bit line, the precharge detection circuit detects this and operates the holding circuit provided between the output circuit and the amplifier circuit. The output circuit is held in the data state before the sense circuit supplies a large current, and at the same time the amplifier circuit and the output circuit are separated.

When the potential of the bit line increases and the current supplied from the sense circuit to the bit line decreases, the pre-charge detection circuit detects this and turns off the holding circuit, and at the same time connects the amplifier circuit and the output circuit. When charging the circuit, the output circuit is held to the previous data and at the same time disconnected from the previous stage circuit, and when charging is completed, the hold is released and the output circuit and the previous stage circuit are connected again, thereby suppressing the meaningless swing of the output circuit. can.

[Example] Fig. 1 shows an example according to the present invention. The 11 precharge detection circuits are P6 and N, , P, and N, , P4 and N2, P
It consists of four inverter circuits: 3 and N6. (P6, P
5, P4, P,...P channel type MOS transistor, N1, N8, N,, N6... N channel type MO
(Sl-transistor) 12 is a holding circuit, which controls Pl, pH, N
ll, a latch circuit consisting of N11, and Pl which controls the operation and non-operation of this latch circuit. , N 14, P2, P, which disconnects or connects the latch circuit and the amplifier circuit 3.
It consists of,N,,,N,,,. (,P,,P,,Po,p
,,p,,-p channel type MOS transistor, N1°, Nll, N12, Nll, N14...
N-channel MOS transistors) C and WL are power supply potentials, C', wL' and B L' are ground potentials, and memory cells N4 and N4' are transistors with no current capacity even if their gate and drain potentials are sufficient (
arc 0 storage cell).

Assume that C changes from the power supply potential to the ground potential, and C' changes from the ground potential to the power supply potential. FIG. 2 shows a potential change diagram at each node, where the vertical axis shows voltage and the horizontal axis shows time.

When charging of the bit line 8 begins, the potential at the drain/gate point 10 of the current detection transistor drops significantly.

The ability of P3 increases and the potential of 13 rises. In response, 15 falls and 14 rises.

P. , N14 becomes conductive, and Pe, P++, N
The latch circuit consisting of 1□ and N13 is in the ON state and 1
At the same time that the potential of 6.17 is held as it is, P? ,
N,1 becomes non-conductive, and the relationship between the circuit after the latch and the amplifier at the previous stage is cut off.

As the potential of bit line 8 rises, lO also rises913
starts to decline because the ability of P decreases. In response to this, 15 rises and 14 falls.

P. and N+4 become non-conductive, turning off the latch circuit, and Pl and N become conductive, connecting the circuits after the latch circuit to the amplifier.

The time it takes for the potential of 10 to fall and the precharge detection circuit to detect it and turn on the holding circuit must be shorter than the time it takes for the potential of 10 to fall and the output of the amplifier to start swinging in the opposite direction. It won't happen.

The timing at which the potential of lO falls and the precharge detection circuit detects this and turns off the holding circuit must be after the output of the amplifier returns to the previous data state.

[Effect of the invention 1 According to the present invention, bit line switching, data transition 0→0,
When the destination bit line has no potential, it is possible to prevent the output circuit from moving in the opposite direction at one end, thereby providing a memory read circuit that can perform stable reading.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of the present invention, and FIGS. 2(a) and (b) are waveform diagrams showing the operation of the circuit of the present invention. FIG. 3 is a conventional circuit diagram, and FIGS. 4(a) and 4(b) are waveform diagrams showing the operation of the conventional circuit. l...Power supply potential 2...Ground potential" 3...Amplifier circuit 4...Output circuit 5...Output circuit output voltage, 8...Bit lines 6, 9, 10, 13, 16...Circuit node 11...Precharge detection circuit 12...Holding circuit 14.15...Precharge detection circuit output 17...
・Holding circuit output 'c, c'... Pit line selection decoder output signal WL, WL' ・Word line selection decoder output signal PL, Pt, Pg, P4. Pa, Pat P7Ps,
Pa, Pla-P++...P-channel type MOI-transistor Nr, N2, N1, Ns', N4, N4', N
s, N,', Na, N? , Ns , No, NIo,
Nth・NI2・Nth・N+4...N channel type MOS transistor →t 3rd) Sword

Claims (1)

[Scope of Claims] One end of a switching transistor is connected to the drain of a memory cell transistor, the other end is connected to one end of a current detection transistor, and the other end of the current detection transistor is connected to a power supply, a sense circuit including a feedback transistor circuit whose input is the drain of the memory cell transistor and whose output is the gate potential of the switch transistor; an amplifier circuit that potential-amplifies the output of the sense circuit; In a memory read circuit consisting of an output circuit that outputs to an external terminal, (a) a precharge detection circuit that detects that a large current is supplied from the sense circuit to the bit line for bit line precharging; (b) A memory reading circuit comprising: a holding circuit that receives a detection signal from the precharge detection circuit and temporarily holds a potential.