JPH01270428A - Clock reproducing circuit - Google Patents

Abstract

PURPOSE:To shorten the phase leading-in time and to reduce the phase jitter by making the pass band width of a loop filter different between the phase leading-in period and the phase settling period in a clock reproducing circuit using a PLL circuit. CONSTITUTION:Counted values which designate two kinds of loop band, namely, a wide band and a narrow band are set to a digital PLL circuit 1 by switches 28 and 29. In the phase leading-in period, a select control signal SS in the high level is supplied from an AND gate 26 to a selector 27. As the result, the selector 27 selects the counted value of the switch 28, and the loop band of the wide band is set to a loop filter 13 of the PLL circuit 1, and the PLL circuit 1 performs the leading-in operation with the loop band of the wide band. Thus, the phase leading-in period is shortened. After the phase leading-in period, the output of the AND gate 26 is inverted, and the selector 27 selects the counted value of the switch 29, and the PLL circuit 1 reproduces the clock signal with the loop band of the narrow band.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a clock regeneration circuit used for regenerating a clock signal from a received burst signal, for example in a satellite communication device.

(Prior Art) Conventionally, this type of circuit has often been based on an analog system such as a baseband square tank limiter system, and when regenerating a clock signal from a burst signal in such a circuit, Countermeasures such as tank cracking have been taken. On the other hand, with recent advances in digital technology, it has been considered to configure a clock recovery circuit using a digital PLL circuit. This kind of circuit is
It is very promising because the circuit can not only be made smaller but also inexpensive.

However, when configuring a clock recovery circuit using a digital PLL circuit like this, there is no particular problem as long as the input signal is a continuous signal. In the case of reproduction, it was necessary to take into consideration two contradictory requirements: the phase pull-in time and the phase jitter of the reproduced clock. In other words, in order to shorten the phase pull-in time, it is sufficient to widen the loop band of the PLL circuit, but widening the loop band of the PLL circuit in this way increases the phase jitter of the recovered clock; If the loop band of the PLL circuit is set to be narrow in order to reduce the noise, there is a problem in that the phase pull-in time becomes longer, which interferes with the data reception operation. For this reason,
Conventionally, both the phase pull-in time and the phase jitter have to be set within an allowable range for the operation of the device, and it cannot be applied to systems with severe operating conditions.

(Problem to be Solved by the Invention) As described above, the conventional circuit has a problem in that it cannot sufficiently satisfy both the shortening of the phase pull-in time and the reduction of phase jitter. Focusing on this point, the present invention attempts to provide a clock regeneration circuit that can sufficiently shorten the phase acquisition time and reduce phase jitter.

[Structure of the Invention] (Means for Solving the Problems) The present invention comprises a loop filter that determines the loop band of a PLL circuit whose pass band can be variably set, and which adjusts the phase pull-in period and phase of the PLL circuit. A signal generating means for generating a signal representing an establishment period, and a band setting control means for controlling a passband of the loop filter, and the band setting control means performs phase pull-in according to the signal generated from the signal generating means. During the period, the pass band of the loop filter is set to a wide band, and during the phase establishment period, the pass band of the loop filter is set to a narrow band.

(Function) As a result, the loop band of the PLL circuit is set to a wide band during the phase pull-in period, so the phase can be pulled in in a short time after the start of input of the received burst signal, while the phase after the phase pull-in is completed is Since the loop band of the PLL circuit is set to a narrow band during the establishment period, a clock signal with less phase jitter can be reproduced during this period. That is, according to the present invention, clock regeneration can be performed with a short phase acquisition time and with little phase jitter.

(Embodiment) FIG. 1 is a circuit block diagram showing the configuration of a clock recovery circuit in an embodiment of the present invention, where l indicates a digital PLL circuit and 2 indicates a band setting control circuit.

The digital PLL circuit l includes a frequency division counter 11 and a pulse addition/removal circuit 15 that operate as a voltage controlled oscillator (VCO), and the phase of the reproduced clock O8 outputted from the frequency division counter 11 and the clock Is of the received burst signal. It is composed of a phase comparator 12 for comparison and a loop filter 13 for generating a ti control pulse according to the comparison output of the phase comparator 12. Of these, loop filter 13
is composed of a programmable counter 14.

On the other hand, the band setting control circuit 2 includes the digital PLL circuit 1
a switch 2 that generates two different count values for specifying a loop band for the programmable counter 14;
8.29, and a selector 27 that selectively supplies the count values output from these switches 28.29 to the programmable counter 14. The band setting control circuit 2 also includes counters 21a to 21c having a three-stage series configuration, switches 22a to 22c for specifying count values corresponding to the phase pull-in period to these counters 21a to 21c, and each of the counters 21a to 21c. A count end detector 23 detects the end of the counting operation of 21c, and a flip-flop 2
4 and two Antoge) 25.26.

Among these, the flip-flop 24 is set at the rising edge of the intermediate frequency detection signal IF of the received burst signal, and is reset at the rising edge of the end detection signal output from the count end discriminator 23, and is set during the set period. That is, the AND gate 25 is opened during the phase pull-in period to supply the count clock C8 to the counter 21a. The flip-flop 24 also supplies an open signal to the AND gate 26 during the set period, thereby opening the AND gate 26 and outputting the intermediate frequency detection signal IF.
is supplied to the selector 27 as a selection control signal SS.

Next, the operation of the circuit configured as above will be explained.

First, before starting the burst signal reception operation, the switches 28 and 29 set count values for designating two loop bands, a wide band and a narrow band, for the digital PLL circuit 1, respectively. Further, the switches 22a to 22c are operated to set the count values corresponding to the phase pull-in period T from the start of the preamble to the counters 21a to 21c, respectively.

This phase pull-in period T is a TDMA in which burst signals are arranged on the line as shown in FIG. 2(a), for example.
In the case of a satellite communication system, the demodulation symbol B is added to the beginning of each burst signal as shown in Figure 2(b).
It is set to approximately the length of the TR reception period. In addition, R in FIG. 2(a) is a reference burst, A, B, and C are data bursts, and UW in FIG. 2(b) is a unique word, SIC is a station identification code, and OW is a meeting line. It shows.

Now, in this state, reception of the burst signal is started, and the intermediate frequency detection signal IF of the burst signal is sent to the flip-flop 24.
When input, the flip-flop 24 is activated at the rising edge.
is set. Then, the AND gate 26 is opened and the selection control signal SS of "H rubel" is supplied to the selector 27, which causes the selector 27 to select the switch 28 and supply the counted value to the programmable counter 14 of the digital PLL circuit 1. .For this reason, digital PL
A wide loop band is set in the loop filter 13 of the L circuit 1, and thereafter the digital PLL circuit 1 starts a phase pull-in operation using the wide loop band. therefore,
The digital PLL circuit 1 can pull in a phase in a relatively short time.

Also, during this phase pull-in period, the counters 21a to 21
C performs the counting operation of the count clock C8 supplied via the AND gate 25.

Then, when the count value of each counter 21a to 21c reaches the count value set by the switches 22a to 22c, that is, when the preset phase pull-in period T has elapsed, the end detection signal is generated from the count end detector 23. Flip-flop 24 is reset. Therefore, the selection control signal SS output from the AND gate 26 becomes "L" level at this point, and as a result, the selector 27 selects the switch 29 instead of the switch 28 that had been selected up until then. 14 is supplied with the narrowband count value set by the switch 29, so that the digital PLL circuit 1 thereafter reproduces the clock signal using the narrow loop band.Therefore, reproduction with less phase jitter is possible. Clock O8 is obtained.

Note that when the flip-flop 24 is reset, the supply of the count clock C8 to the counters 21a to 21c is stopped at this point, and the supply of the count clock C8 to the counters 21a to 21c is stopped.
The respective count values are cleared in preparation for the next burst signal.

In this embodiment, the counter for the loop filter of the digital PLL circuit 1 is configured by the programmable counter 14, and two count values for wideband and narrowband are supplied to the programmable counter 14. The digital PLL circuit 1 can pull in the phase in a short time using a wide loop band when pulling in the phase. On the one hand, it is possible to establish the phase, and later to perform stable lock playback with less phase jitter due to the narrow loop band. Therefore, even if the device has severe operating conditions, the phase pull-in time and phase jitter conditions can be fully satisfied.

Note that the present invention is not limited to the above embodiments. For example, in the above embodiment, the phase pull-in period T is set in advance and the loop band is switched when this period elapses, but the phase error detected by the phase comparator 12 of the digital PLL circuit 1 is less than or equal to a predetermined amount. Alternatively, the loop band may be switched at the point in time. Alternatively, two count values to be supplied to the programmable counter 14 may be stored in a ROM, and each count value may be selectively read out and supplied to the programmable counter 14 by switching the address of this ROM.

In addition, various modifications may be made to the set value of the phase pull-in period T, the configuration of the signal generating means representing the phase pull-in period and the phase establishment period, the configuration of the band setting control means, etc. without departing from the gist of the present invention. Can be implemented.

[Effects of the Invention] As detailed above, according to the present invention, the loop filter that determines the loop band of the PLL circuit is configured with a filter whose pass band can be variably set, and the phase pull-in period and phase establishment period of the PLL circuit are controlled. A signal generating means for generating a signal representing a period, and a band setting control means for controlling a pass band of the loop filter, and the band setting control means:
The pass band of the loop filter is set to a wide band during a phase pull-in period and the pass band of the loop filter is set to a narrow band during a phase establishment period according to the signal generated from the signal generating means. Accordingly, it is possible to provide a clock regeneration circuit that can sufficiently shorten the phase acquisition time and reduce phase jitter.

[Brief explanation of the drawing]

FIG. 1 is a circuit block diagram showing the configuration of a clock recovery circuit in an embodiment of the present invention, and FIG. 2 is a diagram showing an example of the signal configuration of a burst signal and phase pull-in period T used to explain the operation of the circuit. be. DESCRIPTION OF SYMBOLS 1... Digital PLL circuit, 2... Band setting control circuit, 11... Frequency division counter, 12... Phase comparator,
13... Loop filter, 14... Programmable counter, 15... Pulse addition/removal circuit, 21a-2
1c...Counter, 22a-22c...Switch for setting phase pull-in time, 23...Count end detector, 24...Flip-flop, 25.26...AND gate, 27...Selector , 28.29...Switch for loop band setting. Applicant's agent Patent attorney Takehiko Suzue Figure 1 Figure 2

Claims (1)

[Claims] A clock regeneration circuit that regenerates a clock signal from a received burst signal using a PLL circuit including a phase comparator, a loop filter, and a voltage-controlled oscillator, the loop filter having a variably settable passband, and the phase pull-in period of the PLL circuit. and a signal generating means for generating a signal representing a phase establishment period; and a signal generating means for setting the passband of the loop filter to a wide band during the phase pull-in period according to the signal generated from the signal generating means, and setting the passband of the loop filter to a wide band during the phase establishment period. 1. A clock regeneration circuit comprising: band setting control means for setting a passband of the clock to a narrow band.