JPH01265341A - Memory access controller - Google Patents

Abstract

PURPOSE:To improve the reliability of a multi-task system by setting and registering previously the ID task numbers and the address areas to which the tasks can access and stopping immediately the instruction cycle via a CPU with an improper access different from a task ID number. CONSTITUTION:A memory access controller 2 registers the ID numbers for identification of tasks and the accessable address areas for each task at initialization. A dispatcher of an operating system always informs the task ID numbers when the tasks are switched and hereafter always an address bus when a microcomputer 1 gets into a memory cycle. Then an instruction is immediately given to the microcomputer 1 for its interruption as long as the address received from a microprocessor is unaccessable. Such improper accesses are excluded for protection of a memory. Thus a protecting function is secured even for the microcomputer 1 at the memory access in a comparatively simple and inexpensive way.

Description

DETAILED DESCRIPTION OF THE INVENTION [Purpose of the Invention (Field of Industrial Application) The present invention relates to a microcomputer system that performs multitask software processing, and relates to a protection function during memory access in the microcomputer system.

(Prior art) In a computer system that performs multitasking processing, it is possible for a specific task to accidentally access a memory area outside its control range due to a bug or other factors, and affect other tasks, especially when writing. This may cause a system downtime by destroying important parameters and data of the operating system software that performs task management. This is a very important problem in the case of various control systems where such system failure must be avoided at all costs. Therefore, in such a system, it is necessary to use tasks and jobs as the basic units when using memory resources, determine the memory areas that they can access, and exclude access to other memory areas by some method. becomes. Conventionally, equivalent countermeasures were not taken externally to deal with such problems, and instead, it was necessary to thoroughly verify that the above-mentioned problems would not occur during the debugging stage before the system was activated, or to implement hardware measures. This problem has been dealt with using various software methods, such as providing an access control switch for each memory area.

Also, in recent years, some microcomputers with 16 bits or more support virtual memory, and MMU for this purpose.
Some devices have a built-in memory protection mechanism (some have a memory management unit built into the CPU), and this is sometimes used.

(Problem to be solved by the invention) However, it is clear that the conventional method of prior verification cannot deal with unexpected runaways, and the time required for debugging to completely eliminate bugs increases, making it difficult to solve problems in the development process. The problem is that it is disadvantageous. Next, hardware methods require complicated circuits for memory access, resulting in increased costs, reduced reliability, and inapplicability to other systems. Additionally, although the computer architecture itself has a memory protection function, it is not supported by most 16-8 bit microcomputers, making it difficult to implement in systems that do not require the use of high-performance microcomputers. be.

The purpose of the present invention is to relatively simply and inexpensively realize a protection function when accessing memory in any microcomputer. An object of the present invention is to provide a memory access control device that realizes task-specific memory protection through simple command control.

[Structure of the Invention] (Means for Solving the Problems) A memory access control device of the present invention is provided in a microcomputer system that performs multi-task processing, and is configured to identify a task ID number for each task and an address area that can be accessed by that task. means for setting and registering the task ID number in advance, means for constantly monitoring the address bus when the task ID number is notified at the time of memory access, and means for immediately causing the CPU to abort the instruction cycle in the event of an illegal access different from the task ID number. It has the following characteristics.

(Operation) According to the memory access control device of the present invention, an ID number for identifying the task and an accessible address area are registered for each task at the initial stage. The operating system dispatcher always notifies the task ID number when switching tasks, and thereafter monitors the address bus whenever the microcomputer enters a memory cycle, and if the address output by the microprocessor is outside the accessible range, Immediately instruct the microcomputer to interrupt, eliminate such unauthorized access, and protect the memory.

(Example) An embodiment of the present invention will be described with reference to FIGS. 1 to 4.

FIG. 2 is a block diagram of the memory access control device.

In the diagram, microcomputer 1 is Z80 (product name)
It is. An address bus and a data bus are connected to the memory access control device 2 between the microcomputer 1 and the memory 3, respectively. 4 is a decoder; 5.
6.7.8 is an OR gate. The memory access control device 2 is an IC and may be of any type, but in any case, a system lock is required, so if you use the CPU clock without creating an external clock, you cannot use the microprogramming method. First, it is composed of ASIC of wire rossic type or array type. Each control line that controls these systems is connected via gates and buffers, and the INT terminal is connected to the I/O terminal of the microcomputer 1.
Connected to the NT terminal. Memory access control device 2
The WRE signal is ANDed with the MWRITE signal of the device 2 and connected to the memory 3 as the MWRITE signal of the memory system. Although FIG. 2 is a simplified diagram, an actual system would actually be more complex since various peripheral devices such as an interrupt controller are used. Fourth
The figure shows access permission information for tasks registered in the memory access control device 2 called an address disk libter, in which an ID number is attached to each task, and accessible ranges are set and registered for each code and data. A maximum of 256 address discriminators can be registered. FIG. 3 shows the register configuration of the memory access control device 2 and the contents of the control register. The initial setting flow is as follows: (1) In the registration mode, use or unuse the WRE terminal and INT terminal and set a vector in the vector register.

(2) Set all address disc libters.

(3) Move to execution mode.

Next, the operation of this embodiment configured as described above will be explained. The operating system that controls the multitasking system always notifies the ID number of the task to be executed when disbatching the task and writes it into the register of the memory access control device 2. At this point, the memory access control device 2 selects an address discreptor with this ID number, and starts monitoring the address bus whenever the CPU enters a memory cycle. However, all fetch cycles immediately after writing are ignored.

(For register restoration and RET instruction execution).

The address monitoring timing is the MREAD signal.

This is the case when either the MWRITE signal or the CFETCH signal becomes active and the τ1 signal is negative. At this time, if the determined address of the address bus is not within the address permission range specified by the address distributor, the memory access control device 2 immediately enters burst mode.
If determined at the time of initial setting, the periods in which the INT signal and WRE signal are active are as follows: INT signal is activated until an interrupt is acknowledged, WRE signal is activated until the currently executed instruction is completed (the next fetch occurs). ).

In this way, illegal accesses are eliminated and memory protection for each task is achieved.

By using such a memory access control device 2, memory protection for each task can be realized with a simple configuration and procedure for both hardware and software. This makes it possible to construct a highly reliable multitasking system using a microcomputer that is optimal for the application without increasing costs.

In this embodiment, this device has been described as being incorporated into a system, but instead of being incorporated into a system, it can be used as a piggyback device (mounted with multiple ICs and paired with a microprocessor).
The same function can be achieved even if it is used only when depacking (with an interface so that it can be inserted into the U socket).

[Effects of the Invention] The memory access control device of the present invention uniquely provides a memory access protection function that is essential in a multitasking system, and by realizing memory protection using a very simple algorithm, This usage is easy,
Since it is simple, it is possible to realize a complete multitasking system that does not increase costs and is highly reliable.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of a memory access control device showing an embodiment of the present invention, Fig. 2 is a block diagram of a memory access control device using a Z8o (product name) microcomputer, and Fig. 3 is a memory access control device. FIG. 4 is a diagram showing the configuration of the address discriminator. 1...CPU. 2...Memory access control device 3...Memory block agent Patent attorney Noriyuki Chika

Claims (1)

[Claims] In a microcomputer system that performs multi-task processing, means for presetting and registering a task ID number for each task and an address area accessible by that task, and constantly monitoring an address bus when the task ID number is notified at the time of memory access. and the task ID
1. A memory access control device comprising means for causing a CPU to immediately stop an instruction cycle when there is an illegal access different from the number.