JPH01264307A - Modulator - Google Patents

Abstract

PURPOSE:To reduce the number of additions and that of subtractions by consti tuting a Nyquist filter of a digital signal processor, dividing the Nyquist filter into groups having tap coefficients at every baud cycle, and selecting the tap coefficient appropriately at the time of performing multiplication and the addi tion. CONSTITUTION:The impulse responses h(nTs)203 and 204 of the Nyquist filter are constituted of a FIR filter generally to guarantee constant phase lag. The FIR filter is constituted of delay apparatuses (300-302), multipliers (303-307), the tap coefficients (h0-hn-1), and an adder 308. Firstly, the initialization of the delay apparatuses (300-302) are performed, Following that, an input signal is fetched in at every Ts, and equation is operated. In the equation, in(iTs) expresses an input signal system, and out(nTs) expresses an output signal sys tem. At the time of performing the arithmetic operation, control is performed in such a way that no multiplication is performed on input data whose value is recognized as '0' from the beginning out of the input data in(iTs) by substitut ing the order of the tap coefficients of the Nyquist filter.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a modulation device comprising a Nyquist filter using a digital signal processor.

[Prior Art] When transmitting digital signal data via a general public line (analog line), a modulator/demodulator (modem) converts the digital signal into a desired analog signal and vice versa.
is required.

In recent years, with the development of digital technology, areas that can be processed digitally have been expanded to DSP (digital signal processing processor).
It is often composed of

In addition, for the modulator that modulates the transmission data in the transmitting side device, many modulation methods have been considered depending on the data transfer speed, etc., and the typical one is phase modulation that changes the phase of the carrier wave. There are a frequency modulation (FSX) method that changes the carrier frequency, an amplitude modulation (AM) method that changes the amplitude, and a quadrature amplitude modulation (QAM) method that changes the amplitude and phase.

The signal modulated by this modulator is converted into an analog signal by a D/A converter and sent to an analog line. The signal is then demodulated back to its original state by the receiving device.

Conventionally, when a modulator is configured with a DSP, transmission source data d (nTd) is converted into a two-dimensional code of, for example, an X component x (nTb) and an X component y (nTb) and output. Therefore, in order to completely restore this on the receiving side, the transmitting side must sample at 2/(Tb) [Hz] or higher.

Here, Td: transmission source data period, Tb: baud period.

[Problem to be solved by the invention] Therefore, in order to perform this restoration, n multiplications and n additions must be performed in a short time, which is extremely time consuming to perform Nyquist filtering on a DSP. High speed is required, and in some cases there is a risk that calculations may not be completed in time.

In other words, if CCITT recommendations V27ter and V2O are to be realized, the number of Nyquist filter taps will also need to be 32 to 32.
Approximately 64 calculations were required, which required a huge amount of calculation.

[Means for Solving the Problems] The present invention has been made for the purpose of solving the above-mentioned problems, and includes the following configuration as one means for solving the above-mentioned problems.

That is, the modulation device is constructed by constructing a Nyquist filter using a digital signal processor, and the Nyquist filter is constructed by dividing the Nyquist filter into groups having tap coefficients for each baud period.

[Operation] In the above configuration, by appropriately selecting the tap count of the Nyquist filter when performing multiplication and addition, the number of multiplications and additions can be significantly reduced.

[Example 1] Hereinafter, an example according to the present invention will be described in detail with reference to the drawings.

FIG. 1 shows a modulation/demodulation device (modem) according to an embodiment of the present invention.
This is a block diagram of the DSP.
(digital signal processing processor).

In FIG. 1, 100 and 118 are transmitting terminals and receiving terminals that are connected to the modem of this embodiment and generate digital signals to be transmitted.

101 is a scrambler that randomizes transmission data in order to prevent continuous output of the same data; 102 is an encoder that assigns a code to the signal from the scrambler 101 for each tribit, guibit, etc.; and 103 is a code amount interference of the signal. Pulse shaping filter (roll-off filter) that prevents
04 is a modulator that performs predetermined modulation processing on the signal from the pulse shaping filter 103. This modulator 10
The modulation method in No. 4 is a quadrature amplitude modulation (QAM) method that changes the amplitude and phase of a carrier wave.

The signal modulated by this modulator 104 is converted into an analog signal by a D/A converter 105 to be sent to an analog public line, etc., and is further processed by a low-pass filter 106 to match the transmission band of the transmission path. harmonic components are removed and sent to the transmission line.

On the other hand, from the transmission signal from the transmission path, components outside the transmission band are first removed by a bandpass filter 110, then controlled by the AGCll to a signal level that can be handled on the receiving side, and then converted into a digital signal by the A/D converter 112. be converted into After being converted into a digital signal, it is demodulated by the demodulator 113 into the original signal before modulation. Here, 114 is an equalizer, which removes distortion components received during transmission from the received signal as described above, and extracts the original transmitted signal. The output signal of the equalizer 114 is sent to a determiner 115, where it is determined to be a code point, and then decoded by a decoder 116 and sent to a descrambler 117.
The signal randomized by the scrambler 101 on the transmitting side is restored to its original state.

In this way, the signal is returned to the same signal as the transmission signal output from the transmitting terminal 100, and is output to the receiving terminal 118 side.

In this way, by using a modem, it is possible to transmit digital signals via a public line, which is a general analog line.

The detailed configuration of the modulator portion of the DSP (digital signal processing processor) of this embodiment having the above configuration will be explained below with reference to FIG.

In FIG. 2, 200 is a code converter which converts transmission source data d (nTd) into x (nT
b) and y component y (nTb) and output. Therefore, on the receiving side, x (nTb) and y (
nTb), on the transmitting side 2 / (T b
) Must be sampled at or above [Hz].

Here, Td: transmission source data period, Tb: baud period.

201 and 202 are zero insertion circuits to satisfy the above-mentioned sampling theorem, and x (nTb) and y (nTb) points other than the (nTb) point are set to "0'°. These zero insertion circuits 201, 202
The outputs of are a(nTs) and b(nTs). 203
, 204 is the impulse response h (nTs) of the Nyquist filter. Here, a (nT
s) and b (nTs), and p (nTs) and q (nTs) are output as a result. This convolution has a sampling period Ts
must be finished in between.

The outputs p (nTs) and q (nTs) are converted into cos (Wc-nTs) and s i by multipliers 205 and 206, respectively.
n (Wc-nTs), both multiplication values are added by an adder 207, and output as a modulation signal s (nTs). This modulated signal s (nTs) is sent to a D/A converter 208 (D/A converter 105 in FIG. 1), and is converted into an analog signal.

In addition, impulse response h (nTs) 203.2
04 is usually configured with an FIR filter to ensure constant phase delay.

The configuration of this FIR filter will be explained below using FIG. 3.

In FIG. 3, 300 to 302 are delay units, 303 to 307 are multipliers, ho''h n-+ is a tap coefficient, and 308 is an adder.

First, delay units 300-302 are initialized. Next, the input signal is taken in every Ts and ○u t (nT
s) = "l-'h,, -+ ・i n (i Ts
) is calculated. Here, in (iTs) represents an input signal sequence, and out (nTs) represents an output signal sequence.

Therefore, if we try to perform all of these calculations on a DSP as in the past, out (nTs):', E-'hn-I H
The operation of i n (i Ts) includes n multiplications and n additions, and must be completed within Ts.

For this reason, the DSP is required to have considerable high speed.

Therefore, in this embodiment, when performing the above calculation, by changing the order of the tap counts of the Nyquist filter, the input data 1n (iTs) is set to "0" from the beginning.
Control is performed so that multiplication is not performed for those that are known to be .

Below, we will specifically explain Figures 4 (A), (B) and Figure 5 (
This embodiment will be explained using A) and (B) in comparison with the conventional one.

In addition, in this example, as a Nyquist filter,
Modulation speed 1200 bps, sampling speed 9600H
z, a Nyquilt filter with 32 taps was adopted.

Both Fig. 4 (A), (B) and Fig. 5 (A), (B),
Ramp and Ram1 indicate an example of the storage area of the built-in RAM in the DSP, and each has two sides (A) and (B).

The ROF in Fig. 4 (A) and Fig. 5 (A) is Ram0
and the start address of Ram1, Fig. 4 (B), Fig. 5 (
RVDT in B) is the start address of Ram1. In the figure, 16 shown on the right side of Ram0 and Ram1
The two-digit numbers are relative addresses to the ROF and RVDT, respectively.

First, using Fig. 4 (A) and (B), the conventional out
The calculation method of (nTs)=Σhn−+ −in (iTs) will be explained. In Figure 4, ha"hs+
is the tap coefficient of the Nyquist filter.

First, (00 to IF) of Ram1 is initialized. i
n (0-Ts) is the start address of Ram1 (00')
out (0-Ts)=Σh-+・i n (i
Ts) is calculated.

Subsequently, 1n (1=Ts) is stored in Ram1 (IF) and out (1・Ts)=Σh+−+ −in (iT
s) is calculated.

Here, in (1・Ts) is stored in Ram1 (IF), which is a method of speeding up the convolution operation by using a ring counter, which makes full use of the known DSP architecture. Therefore, the explanation will be omitted.

By repeating the above series of operations, out (
0-Ts), out (1-Ts), -..., out
(n-Ts), . . . are found. In this way, when calculations are performed using the conventional method, T
All must be done within s time. Therefore, a huge amount of calculation is required in the end time.

The calculation method of this embodiment for this purpose will be explained.

In this example, the tap coefficients are changed from Fig. 4 (A) to Fig. 5 (
They are rearranged as shown in Ram0 in A). In other words, the first 4 words start with ho and the frequency is (9600Hz/1
200bps) = “8” every ゛ha, h+a, h
Select tap coefficients as shown in 24. The next four words start from hl and similarly select tap coefficients every "8", such as he, h+t, and h2B.

Following the above procedure, tap coefficients h0 to h31 are arranged on Ram0 as shown in FIG. 5(A) until the tap coefficients are used up.

Next, as shown in FIG. 5(B), four words are prepared as RAM1 for storing input data 1n (iTs).

Here, if we focus on the input data 1n(iTs), this 1n(iTs) corresponds to a(nTs) or b(nTs) in FIG.
b) or has information of y(nTb), and other points are “0”
It is.

Therefore.

out (nTs)=Σl”In−+ Hin (i
It can be seen that the multiplication of hn-+·in (iTs) in Ts) has a value other than "0" every (8Ts), and the other points are "O" without any calculation.

Taking advantage of this characteristic, out (nTs) = Σ'hn-t 1 i n, (i
The main objective of the present invention is to efficiently calculate Ts).

Therefore, prior to the calculation, Ram1 in FIG. 5 is initialized, and 1n (0-Ts) is stored in Ram1 (00). At this point, Ram0 (00) to Ram0 (03
) and Ram1 (00) to Ram1 (03) are taken.

Subsequently, a convolution of Ram0 (04) to Ram0 (07) and Ram 1 (OO) to Ram 1 (03) is taken.

This series of operations is Ram○ (IC) ~ Ram0 (IF)
This process is repeated until the convolution of Ram1 (00) to Ram1 (03) is completed.

When the above operation is completed, 1n(1・Ts) is Ram1
(03), and the same series of operations is repeated.

Therefore, in this example, out (nTs)=g, i+, 1-+ Hin (
iTs) requires only four multiplications and four additions, making it possible to significantly reduce the amount of calculations.

Note that this embodiment has been described with reference to an example in which a sampling rate of 9600 Hz at a modulation rate of 1200 bps and a 32-tap Nyquist filter are adopted when using the 2400 bps transmission rate in the CCITT modem recommendation V27ter. The invention is not limited to this example; for example, the V29 2400
A sampling rate of 9600 Hz and a 64-tap Nyquist filter may be employed for bps.

In this case as well, out (nTs)=Σhn−r −in (iT
s) requires only 16 multiplications and 16 additions. In this way, 64 multiplications and 6
Compared to the case where addition is performed four times, it is possible to significantly reduce the amount of calculation.

A similar effect is obtained for the V27ter, 1600 bps, with a sampling rate of 9600 Hz, and 48
If a tap Nyquist filter is used and the configuration of this embodiment is used, only eight multiplications and eight additions are required.

The detailed operation in this embodiment will be explained with reference to the flowchart in FIG.

First, in step 600, before input data is stored, Ra
m1 is initialized, and in step 601, a counter n used for the storage address of input data is initialized. In the following step 602, the Ram1 address is determined using nmod4. Therefore, the first input data is Ram1 (0
0). In the next step 603 h
A, ha, has, hza are convolved with Ram1, and the result is output in step 604.

Similarly, in step 605, h+ %he s htt, h
Perform convolution of as and Ram1, output the result in step 606, and output h2 in step 607.
% h 10, hllb has, h
Convolution is performed between aa and Ram1, and the result is output at step 610. h4 in step 611
, hl□, h 20% h is and Ram1 are convolved, the result is output in step 612, and hll, hI3, h 211 is output in step 613.
h Perform convolution with 2Q and Ram1,
Step 614 outputs the result, step 615 performs convolution of hll, h14, h22, hso and Ram1, step 616 outputs the result, step 617 h7, h16, h23, h
Convolution is performed between a1 and Ram1, and the result is output in step 618.

After the above series of arithmetic operations, the address counter n of the input data storage RAM1 is decremented in step 619, and then it is checked in step 620 whether or not this counter n is "0". If counter n is here, step 6
01, the counter n is again initialized to "4", and the above-described processing is performed.

On the other hand, if the counter n is not "O", the process returns to step 602 and the above-described process is performed.

The above operations are continued as long as the input data series continues.

As explained above, according to this embodiment, the following effects can be achieved.

Using a digital signal processor, out(nTs) = Σhn-+ Hi n (i T
s) If Nyquist filtering is performed, 32 multiplications and 32 additions must be performed within the time Ts, but by adopting the algorithm according to this embodiment, the sampling rate can be reduced to 9 with a V27ter modem.
When a 600 Hz, 32 tap Nyquist filter is used, only four multiplications and four additions are required within the Ts time, and the effect is absolute.

Furthermore, the present invention is not limited to the above-described embodiments, but can be applied to a V27ter modem using a 48-tap Nyquist filter at a modulation rate of 1600bps and a sampling rate of 9600Hz, or a V29 modem with a modulation rate of 2400bps and a sampling rate of 9600Hz, 6
Even when a 4-tap Nyquist filter is used, the same effect can be obtained by performing modulation processing using a similar algorithm.

[Effects of the Invention] As described above, according to the present invention, by appropriately selecting the tap count of the Nyquist filter when performing multiplication and addition, it is possible to significantly reduce the number of times of multiplication and addition.

[Brief explanation of the drawing]

FIG. 1 is a basic configuration diagram of a modem according to an embodiment of the present invention, FIG. 2 is a basic circuit diagram of the modulation section of FIG. 1, FIG. 3 is a Nyquist filter circuit diagram of this embodiment, and FIG. A) and (B) are tap coefficient arrangement diagrams of a conventional Nyquist filter, FIGS. 5A and 5B are tap coefficient arrangement diagrams of this embodiment, and FIG. 6 is an operation flowchart of this embodiment. In the figure, 100... transmitting terminal, 101... scrambler, 102... encoder, 103... pulse shaping filter, 104... modulator, 105, 208... -D/
A converter, 106...Low pass filter, 110...
・Band pass filter, 111...AGC, 112・
...A/D converter, 113... Demodulator, 114...
Equalizer, 115... Determiner, 116... Decoder, 1
17... Descrambler, 118... Receiving terminal,
200... Code converter, 201, 202... Zero insertion circuit, 205, 206... Multiplier, 20
7゜303~308,403-...adder, 300~3
02... Delay device. Ram0 Ram1 (A)
CB) Figure 4 Ram0 (A) aml Figure 5

Claims (1)

[Claims] A modulation device comprising a Nyquist filter configured by a digital signal processor, wherein the Nyquist filter is divided into groups having tap coefficients for each baud period, and the tap count is selected appropriately when performing multiplication and addition. A high-speed modulation device characterized by significantly reducing the number of multiplications and additions.