JPH01263855A - Parity bit application system - Google Patents

Abstract

PURPOSE:To realize the reduction of the parity memory capacity by allocating just a single parity bit to plural addresses. CONSTITUTION:A counter CNT performs a count-up action with reception of a clock pulse and supplies the addresses to a data memory DMEM and a parity memory PMEM. A parity production circuit PG produces the parity bits to 9 bits in all for the data on a data bus DB and the output data on a gate G while the data are written into the DMEM. The result of said production of the parity bit is latched by a flip-flop F/F and then written into the PMEM. The F/F is reset when the writing action is through to the PMEM.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for assigning a parity bit to a memory, and particularly to a method for assigning a parity bit for failure detection.

[Prior Art] The parity bit method is the most commonly used method for detecting memory failures. Depending on whether the number of 1's in the address data (multiple bit strings consisting of binary values of "1" or "0") is odd or even, the parity bit for that data is set to °1' or °0. ’.

[Problem to be solved by the invention]

In the conventional parity bit assignment method described above, a parity bit is required for every address, which not only increases the memory capacity, but also requires a large address space since the memory element for the parity bit has a bit width of 1 bit. If there is no parity bit, the amount of memory for parity bits increases,
This method has the disadvantage that the amount of hardware increases and is economically disadvantageous.

[Means to solve the problem]

The parity/soto assignment method of the present invention adds a new sequential read cycle in addition to a random read cycle during a read operation in a memory that performs sequential writing and random allocation operations, or a memory that performs only random allocation operations. [
Examples) Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. In FIG. 1, DMEM is a data memory that stores data, PMEM is a parity memory that stores parity bits, and CNT is a counter that performs a count-up operation in response to clock pulses, and operates to count up data memory DMEM and parity memory PMEM. This is for supplying addresses. PG is a parity bit generation circuit, F,
/F is a flip-flop, and G is an l-restate gate. AD is an address line consisting of 16 bits 1-,
QD is the run 1 data of counter CNT and consists of 16 bits. SEL is a selector, and address line A
Either D or count data QD is selected, and the selected information is supplied as address information to data memory DMEM and parity memory PMEM. DB is a data bus consisting of 58-bit data lines.

The capacity of the data memory DMEM is 64 words x 8 bits, and this memory transfers address information to the selector 5EI-
It receives 16-bit data. On the other hand, the capacity of parity memory P M E M is 1 word x 1 bit, and this memory is used as address information by selector S.
It receives the upper 10 bits of the 16 bits of data output from the EL.

Now, a method for creating parity bits and a write operation to the parity memory I) MEM will be explained when data is sequentially written to all addresses in the data memory DMEM.

In the initial state, all outputs of the counter CNT are “0”.
', the outputs of flip-flops F and /F are also 0', and gates 1-G are enabled. Further, the selector SEL selects and outputs the count data QD. Write data to the data memory DMEM is sent to the data bus I)B, and the write data is input to the data memory DMEM to perform a write operation. During this write operation, the parity generation circuit PG
A parity bit is created for a total of 9 bits of data of B and Jl and the output data of gate G (0° in the initial state), and the result is sent to flip-flop F.
,/'F Niu Sochi. Next, increment the counter CNT and set the address for the data memory D M E M to 1.
address, sends the next write data to the data bus DB, and performs 4 writes to the data memory DMEM. In this write operation as well, in the parity creation circuit, the data on the data bus DBJI and the output data of the gate G are 9 in total.
Create a parity bit for the bit data,
The result is newly latched into the flip-flop F/F. By repeating these operations sequentially, the data memory D
The MEM address is address 63 (address 3F in hexadecimal)
When the parity bit creation is completed, the output data of the flip-flop F/F is sent to the parity memory PMEM via the gate G, and the data is written to the parity memory PMEM.
The address of EM is address 0. In other words, at this point, all data 512 bits (64 x 8 bits) from addresses 0 to 63 of the data memory DMEM are created to create a 1-bit parity bit, and that bit is stored at address 0 of the parity memory PMEM. It means you have written it down. Note that the flip-flop F/F is reset at the end of the write operation of the parity memory PMEM. For 64 addresses from 64 to 127 in the data memory DMEM, repeat the same operation described above for addresses 0 to 63, and place the 64 to 127 addresses in the data memory DMEM at address 1 in the parity memory PMEM. Writes the parity bit for 512 pin data. Finally, the address of the data memory DMEM is F in hexadecimal notation.
FF When memory writing at address F (end address R) is completed, address of valid day memory P M E M becomes 1.
Writing to the parity memory PMEM at address 3FF (last address) in hexadecimal representation is also completed at the same time, and all write operations are completed.

Next, the memory reading and validation checking operations will be explained.

Two memory read cycles, a random read cycle and a sequential read cycle, occur alternately.

During a random read cycle, the selector SEL selects the address line AD, and during a sequential read cycle, the selector SEL selects the count data QD.
Address information is supplied to data memory DMEM and parity memory PMEM. During a random read cycle, only the data memory IIMEM is read,
The parity memory PMEM is not read.

Also, parity generation circuit PG, flip-flop 1F/
F, gate G is not operated at all.

In the following, we will focus only on sequential read cycles,
The memory read and parity check operations will be explained. Therefore, originally, a random read cycle and a sequential read cycle occur alternately one cycle at a time, but here, the random read cycle is ignored and only the sequential read cycle is assumed to occur continuously.

As an initial state, the output of counter CNT is all bits °O.
, and the gate G is in a high impedance state.

The data memory DMEM and the parity memory PMEM are read in a state where the output of the counter CNT is all 0'. At this time, the address of both memories is 0'. Read data from the data memory DMEM and parity memory PMEM is input to a parity generation circuit PG, and the generated parity bit is latched by a flip-flop F/F. After this, gate G is enabled.

Next, the counter CNT is incremented and the data memory DMEM is
The parity generation circuit PG requests the 1st address of the data memory DMEM and the parity bit for the data of a total of 9 bits 1-, which is the data read from the data memory DMEM and the parity bit already latched in the flip-flop 1F/F. Create a new one and latch it into flip-flops F,/F again. Similarly, for address 2 of the data memory DMEM, reading and parity reading of the data memory DMEM is performed.
Create Soto and repeat up to address 63. The parity bit created at address 63, that is, the output data of flip 70 1F/F, indicates the result of the parity check, and it can be determined whether the solicited data from address O to address 63 of the data memory DMEM is normal. It is.

For example, the parity generation side of the parity generation circuit PG and (
-, if the odd parity rule (if the number of 1's in 9-bit data is an even/odd number, l', /'0' is created as a parity bit), then the 63'4 location of the data memory DMEM. The parity bit created when reading the
In other words, the output data of the flip-flop F/F is 0'
If it is 1, it is normal, and if it is 1, it is abnormal. 12 from address 64 of data memory DMEM
The same is true for addresses up to address 7, and the normality of 512 bits of data for 64 addresses can be checked using 1 parity bit.

〔Effect of the invention〕

As explained above, the present invention is a system in which only one bit of the parity bit is allocated to a plurality of addresses, and therefore has the effect of significantly reducing the parity memory. Furthermore, by setting only one parity bit for every address, validation memory becomes unnecessary, and by simply installing 11 flip-flop circuits in place of parity memory, it is possible to check the normality of the memory. There are some advantages.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of one embodiment of the present invention. AD...address line, CNT...counter, DB...
...Data bus, DMEM...Data memory, F/F
...Flip-flop, G...Game I, PG...Parity creation circuit, PMEM...Parity memory, QD
...power, fit times

Claims (1)

[Claims] In a memory that performs sequential write and random read operations or a memory that performs only random read operations, a new sequential read cycle is added in addition to the random read cycle during these read operations, and the parity bit for memory failure detection is set as described above. A parity bit assignment method characterized in that only one parity bit is assigned in common to multiple addresses in memory.