JPH01263731A - Interruption control system - Google Patents

Abstract

PURPOSE:To reduce a probability in which interruption is neglected, to make unnecessary the interruption with a control circuit and to execute other processing by grasping and resetting a signal to output when the control circuit receives the interruption, in an interruption control system. CONSTITUTION:When a CPU 1 executes a processing X, an active interrupting signal is outputted through a signal line 8 at the time point of A. Then, an interrupting condition holding circuit 2 holds this and as the result, an active interrupting signal is given through a signal line 5 to the CPU 1. The CPU 1 outputs address data (0034)H through an address bus 6 in order to execute the processing for the interruption at the time point of B. An interruption receiving supervising part 3 fetches the address data, compares them with the address data (0034)H held by itself, and at the time of the coincidence, a resetting signal is given to the interrupting condition holding circuit 2. On the other hand, the CPU 1 executes the interrupting processing with a program read from a storage device 4.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to an interrupt control system suitable for giving an interrupt to a control circuit such as a CPU of a computer system, etc. .

(Prior Art) Conventionally, when issuing an interrupt to a CPU, a system has been used in which an interrupt signal from the outside is held in an interrupt state holding circuit made of a flip-flop, etc., and the interrupt signal is given to the CPU. ing. This interrupt state holding circuit is reset during processing after the CPU accepts an interrupt.

Therefore, even if the next interrupt signal becomes active after the CPU accepts an interrupt until the interrupt state holding circuit is reset, the interrupt state holding circuit cannot hold the next interrupt signal. A problem occurred in that the interrupt was ignored. Further, there is another problem in that the CPU is forced to perform a reset process for the interrupt state holding circuit, and this process time is wasted.

(Problems to be Solved by the Invention) As described above, according to the conventional interrupt control system, the interrupt state holding circuit is reset as part of the interrupt processing accepted by the control circuit. There is a problem in that between the time the circuit accepts an interrupt and the time when the interrupt state holding circuit is reset, the interrupt cannot be processed via the interrupt state holding circuit and is ignored. A problem has arisen in that a wasteful process of resetting the interrupt state holding circuit, which is not directly related to the interrupt process, must be performed.

The present invention was made in order to solve the problems of the conventional interrupt control system.The purpose of the present invention is to enable the control circuit to receive an interrupt and output a signal at the same time. The interrupt state holding circuit is reset after every 1L of processing, thus reducing the probability that vJ interrupts will be ignored.
Another object of the present invention is to provide an interrupt signal system that allows the control circuit to perform other processing.

[Configuration of the Invention] (Means for Solving the Problems) The present invention includes an interrupt state holding circuit that holds interrupt number 13 from the outside and provides it to the control circuit; An interrupt reception monitoring unit is provided which accepts one active interrupt signal held in the state holding circuit 1, detects a predetermined signal outputted by τ, and resets the state holding circuit 1. The control system is congruent ().

(Function) According to the above configuration (,:), the control circuit receives an active interrupt signal and detects a predetermined signal to be output, and resets the interrupt state holding circuit. This allows the interrupt state holding circuit to be reset appropriately.

<Example) An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. In the figure, 1 indicates a CPU which is a control circuit, a2 which accepts interrupts and performs predetermined processing is an interrupt state holding circuit, 3 indicates an interrupt reception monitoring unit, and 4 indicates a storage device. Show] No. The interrupt state holding circuit 2 receives an interrupt signal from a terminal or the like via a signal line 8 and holds it. The output signal of the interrupt state holding circuit 2 is sent to the CPU 1 via the signal line 5.
is given to the interrupt terminal of The interrupt state holding circuit 2 is reset by the interrupt reception monitoring section 3. The storage device 4 stores two programs to be executed when CPtJl accepts an interrupt. The CPU 1, the interrupt reception monitoring unit 3, and the storage device 4 are connected by an Atnos bus 6,
Via CPLll, storage device 4 and [JT''-Kvass 7,
T-connected. The interrupt reception monitoring unit 3 uses CPtJl
accepts an interrupt [Pl;: When first, it holds the address data τ to be output to read the data of the storage device 4, and the address data τ1q is received via the monthly bus 6. 1! When the data matches the data at 1, the state holding circuit 2 including υ1 is reset (
This output signal is made active.

As above, 1,1 is drawn 4'1. The interrupt handling operation in the system will be explained with reference to FIG. C.P.
Assume that an active interrupt signal is output via the signal line 8 at time Δ while U 1 is executing process X. In other words, the interrupt state holding circuit 2 holds this state, and as a result, the active interrupt signal is transferred to CP via the signal line 5.
Transferred to tJl. CPtJl receives this interrupt signal and sends the 7th address data (00
34). The interrupt reception monitoring unit 3 uses this address 1.
It takes in the NOS data (003/X)H and compares it with the AT1 NOS data (0034) which is held by itself, and since they match, it gives a heliset signal to the vj busy state holding circuit 2. As a result, the interrupt state holding circuit 2 is reset and the next interrupt can be accepted.

On the other hand, the CPU 1 executes interrupt processing based on the program read from the storage device 4, and ends the interrupt processing at point D. Therefore, conventionally, the CPU 1 handles the interrupt state holding circuit 2 during interrupt processing ().
In this case, at time C, the interrupt state holding circuit 2
is reset, and from then on it is possible to accept the first interrupt, but in this embodiment, it is no longer possible to accept the next interrupt from point B onwards. In the past, the interrupt processing took until the point E from the reset 1-end time (:,,), but in this embodiment, the interrupt processing is
Since this is not performed, the interrupt processing ends up to point D.

[Effects of the Invention] As explained above, according to the present invention, since the control circuit captures and resets the signal output when it receives an interrupt, the probability that the interrupt will be ignored is reduced, and the control circuit Since there are no interrupts, this control circuit can perform other processing.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a time chart for explaining the operation of the embodiment of the present invention. 1...CPU 2...Interrupt status holding circuit 3...Interrupt acceptance monitoring unit 4...Storage device 6...Address bus 7...Data bus agent Patent attorney Book 1) Sodai Figure 1 Figure 2

Claims (1)

[Claims] an interrupt state holding circuit that holds an external interrupt signal and supplies it to a control circuit; and a predetermined signal that the control circuit receives and outputs an active interrupt signal held in the interrupt state holding circuit. An interrupt control system comprising: an interrupt reception monitoring section that resets the interrupt state holding circuit when