JPH01260573A - Vector multiplex computing system - Google Patents

Abstract

PURPOSE:To improve the operation rate of an arithmetic pipeline and the throughput of a vector arithmetic processing unit by sharing and using plural arithmetic pipelines by all of the instructions under execution simultaneously without allocating on each vector instruction. CONSTITUTION:By providing means 2 and 3 to process plural vector arithmetic instructions independent with each other by dividing into every element unit and distributing to plural arithmetic pipelines, the plural vector arithmetic instructions independent with each other are processed in every element unit by respective arithmetic pipeline 4. Therefore, it is possible to use the null time of a certain arithmetic pipeline 4 due to data neck, etc., in executing a certain vector instruction in the processing of another vector instruction. In such a way, the operation rate of the arithmetic pipeline 4 can be heightened, and the throughput of the arithmetic processing unit can be improved.

Description

[Detailed Description of the Invention] [Summary] Regarding the vector multiple operation method in a pipelined vector operation processing device, the present invention relates to a vector operation pipe in a vector operation processing device operating in a MIMD (multiple instruction, multiple data stream) method. With the aim of improving the operating rate of the line and improving the speed of the vector arithmetic processing unit, a number of mutually independent vector arithmetic instructions are
A configuration is provided in which means is provided for dividing into units and distributing them to a plurality of vector processing pipelines for processing, and each vector processing pipeline processes the plurality of mutually independent vector operation instructions in units of elements. do.

[Industrial application field]

The present invention relates to a vector multiplex calculation method in a pipeline type back-to-back calculation processing device.

In recent years, so-called supercomputers have begun to adopt a parallel processing method in which a single vector instruction is operated in parallel using a plurality of arithmetic pipelines in order to improve processing performance.

However, in the current situation where one vector instruction is executed by multiple arithmetic pipelines, if the arithmetic pipeline interrupts the operation in the middle of processing due to waiting for data and the arithmetic pipeline is empty. However, the arithmetic pipeline is occupied by the vector instructions for a long time,
There is a problem in that the load is not necessarily evenly distributed and the multiple calculation pipelines are not fully utilized. A method is needed.

[Prior Art and Problems to be Solved by the Invention] FIG. 3 is a diagram illustrating the second conventional vector multiple operation method.

2. Description of the Related Art Vector arithmetic processing methods based on MIMD (Multiple Instructions, Multiple Data Streams) have been known for some time.

As shown in this figure, when processing instruction 1 and instruction 2 at the same time, conventionally, for example, the operation pipeline A
and B4 were assigned to instruction 1, and arithmetic pipeline C4 was assigned to instruction 2, so that they were processed in parallel.

In this way, if the arithmetic pipeline 4 is assigned to a certain little instruction, the assigned arithmetic pipeline 4 will be exclusively used by that instruction until the instruction is completed. - Even if the arithmetic pipeline 4 became vacant due to the tsuku, it was not possible to process other vector instructions.

In the example shown in the figure, even if the calculation pipelines A and B4 are in an idle state due to the supply of input data of instruction 1, the processing of instruction 2 cannot be executed, and the processing of instruction 2 and other Even though the calculation pipelines (A, B) 4 were vacant, the processing had to be performed only by the calculation pipeline C4.

In view of the conventional drawbacks described in 1., the present invention provides that in a vector multiplex operation method based on the MTMD method, when a certain operation pipeline is empty, the empty operation pipeline is passed to another vector instruction for processing. The purpose of this is to provide a method for executing the program.

[Means to solve the problem]

FIG. 1 is a diagram illustrating the principle configuration of the vector multiple calculation method of the present invention.

The above problems can be solved by a vector multiple operation system configured as follows.

In a pipelined vector arithmetic processing device, means 2 and 3 are provided for dividing a plurality of mutually independent vector arithmetic instructions into element units and distributing them to a plurality of edge processing pipelines 4 for processing. , each vector processing pipeline 4 is configured to process the plurality of mutually independent vector operation instructions element by element.

[Effect]

That is, according to the present invention, in the vector multiplex operation method, a plurality of operation pipelines are not allocated to each vector instruction, but are shared and used by all instructions being executed simultaneously.

That is, as shown in the configuration diagram of FIG. 1(a), the plurality of arithmetic pipelines are configured to be able to execute arithmetic operations for any instruction in element units. Therefore, along with each element data, the type (order) of the instruction corresponding to the element is sent to the plurality of calculation pipelines.
Each arithmetic pipeline executes as many processes as l□-Qi without being concerned at all with the operation of the instruction rail corresponding to the element.

In the example of operation time chart 1- shown in FIG. 1(b),
Initially, the instruction ■ was processed in the calculation pipelines A and B4, and the instruction ■ was processed in the calculation pipeline C4, but when the instruction ■ became a data neck in the second calculation cycle, the calculation was processed in the next calculation cycle. Pipeline A, B, C4
When the instruction (2) is executed and the data neck of the instruction (2) is resolved in the fourth arithmetic cycle, operation is performed to allocate the arithmetic pipelines A and B to the instruction (2) again.

Therefore, the vacant time on the arithmetic pipeline due to data necks, etc. is dynamically switched to processing other instructions, which improves the utilization rate of the arithmetic pipeline and improves the efficiency of the vector arithmetic processing unit. This has the effect of improving throughput solenoid.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

The above-mentioned FIG. 1 is a diagram explaining the principle of the vector multiple operation method of the present invention, in which (a) shows an example of the configuration, and (tl)
2 shows an operation time chart 1, and FIG. 2 is a diagram showing an embodiment of the present invention, in which (a) shows an example of the overall configuration, and (b) shows a specific configuration of the instruction processing unit. An example is shown in which a plurality of instruction processing units 2 each receive one . The calculation pipe control (#0~) 3, which receives the element along with the order, performs processing in units of the Niremen]. When the calculation is completed, the next Element 1~ A means necessary to carry out the present invention is a means in which a plurality of arithmetic pipelines execute the processing of a plurality of command instructions in parallel on an element-by-element basis by repeating the process of waiting for . Note that the same reference numerals indicate the same objects throughout the figures.

Hereinafter, the multiplex operation system of the present invention will be explained with reference to FIG. 2 while referring to the principle configuration of FIG. 1.

First, the overall operation will be explained with reference to FIG. 2(a).

Not shown, for example, multiple request acceptors (II sail 11L --, l1n) from the scalar unit
The vector instruction received at 1 is sent to any available instruction processing unit (+10.Ill) by each request acceptor (no, Ill, --, #n).
, -, #k) 2.

The instruction processing unit 1-(110, Ill, -, 1k)
2, each controls only one . Therefore, the instruction processing unit 1-2 is prepared as many instructions as the number of instructions that can be executed in parallel.

Each instruction processing unit (#0.IIL-, 1lk) 2 controls any arithmetic pipe control (#0.
, -, #1)3, the processing target Niremen1-information (
address), the order of processing contents is specified for each element, and the vector instruction is processed.

Then, when the execution of operations of all elements of the instruction is completed, the instruction processing unit i~2 becomes vacant,
It functions to wait for the next vector instruction.

On the other hand, the arithmetic pipeline (A, B, C, -) 4 operates the plurality of instruction processing units l-(110,
11, ---, Itk) Receives an order for processing target and processing content from one of 2, reads vector data from a data storage device (for example, vector register (VR) +5, performs arithmetic operations, and The results are stored in the data storage device 5 again.

When the processing of one element is completed, it functions to receive and take the next order from any instruction processing unit 2 again.

Next, based on the specific example shown in (, b), Vector Processing-9
= The operation in unit 2 will be explained in more detail.

Typically, one vector unit (VU) receives reconists from a plurality (for example, two) of scalar unisothos (not shown). And the hector uniso 1-(V
U) is a vector register (VR) for each scalar unit
independently. The request acceptor (110, 1) 1 of the hector unisoto (VU) exists for each scalar unisoto (VU). ) 1 is the content of the request (instruction call operand Vll address 1 vector-1 (V
L), scalar unit ID) is sent to the vacant instruction processing unit 2.

The instruction processing unit 2 executes the instruction processing unit 2.
There are as many instructions as the number of instructions that can be processed in parallel in U), and the number does not exceed the number of arithmetic pipelines 4. The instruction processing unit 2 is capable of processing only one "1 vector instruction" at the same time, and when it receives one vector instruction, it becomes busy and waits until the next vector instruction is completed. I do not accept Hector's orders.

In FIG. 2(b), the above instruction row 1. is set in the OP code 21, and the register (R2) 22. If register (R3) 23, the address of the vector register (VR) of the operation source operand is stored in register (R1-).
24 is a hex I register (V) for the operation result operand.
The address of R) is set in the register (R4), and the address of the mask register group R) is set, respectively.
A vector length (VL) is set in the register (VL) 26.

Then, in operations asaincon 1 to roll 27, empty calculation pipe control (no, #],

--, tli) 3 to the corresponding BUSY 110. ,
- Detects that the signal is "off" and accepts the acceptance signal (ACPT) from the corresponding arithmetic pipe control 010.Ill-,-,Iti)3 (#O,ll], --,
tti), the free calculation pipe control (1
10, ltl, -, 1li) J
2.The above registers (R1,) 22 to (I14)
24 to n+n+1. + "-", n+: Outputs the address and index of the 4-element I of 3.

Then, I went to Kotoba Operation Vibe City 11F Wholesale (110, 11,
−, l1i) As many elements as the number of elements that were accepted or 1 in 3,
Counter (+m) 28 is incremented by I~.

That is, each instruction processing unit (llO, Ill −, 1
lk) 2 is the acquired arithmetic pipe control (lto, Il
l, -=-,1li) For 3, break down the hack 1-le instruction into nilemens 1-, and as one request-da-da for each coni-element, -I- written operation code F, operand VR7+' The response, index, and scalar Uniso 1-ID are sent. Calculation bits back wholesale (book to,
l11. −． l1i) 3 executes an operation on the specified element based on the request order, stores the operation result in the specified register (VR), and waits for the next request order.

In this way, the calculation pipe control (IO, Ill,
, -, 1li) 3 executes the -\little command and is completely unrelated to the operation of \\, and each instruction processing unit (1li)
10, Ill, -=-, 1lk) Passively receives the element-wise order from 2 and performs each nylenon I unit operation for each double operation nicle.

Conflicts of operands that occur in this element-based vector arithmetic processing are handled by each instruction processing unit h.
(110, Ill, , -, 1lk) In the operation assign control 27 in 2, communication between each instruction processing unit is performed, and the ink clock is transferred to the instruction processing unit (# O, #1.-.
1lk) This is done by not issuing any orders from step 2 onwards.

” 2, each instruction processing unit h (#0.month, -, l1k) 2 shown in FIG. 2(a)
A processing request for Niremen I units from is dynamically switched to the plurality of calculation pipe controls (#0.#1.-, 1fi) 3, accepted, and executed.

The calculation pipe control (lto, Ill, -, #
i) In the reception method in step 3, for example, the operation pipe control ( #0.
#L-, 1li)3 is the above acceptance signal (8C
By controlling the return of (#Sail tlL-5#1), a certain priority order can be automatically assigned.

”2 priority signal is for each instruction processing unit 1-2.
In operation 27, for example, the waiting time is counted, and when the waiting time increases, an arbitrary priority signal is generated by increasing the own priority. be able to.

As described above, in the pipeline vector operation processing method, the present invention allows a plurality of mutually independent vector operation instructions to be processed into one in the plurality of instruction processing units provided in the vector UNISO 1 to (VU). Address reception,
By dividing the process into element units and sending it to an empty uniso t- in the plurality of arithmetic pipe control uniso I and having it processed in element units, each of the plurality of arithmetic pipelines can process the plurality of The feature is that vector instructions are processed in units of one element.

〔Effect of the invention〕

As described above in detail, the vector multiple operation method of the present invention is a vector multiple operation method in which a plurality of mutually independent vector operation instructions are A means is provided for dividing the unit into l-units and distributing them to a plurality of vector processing pipelines for processing, and each vector processing pipeline processes the plurality of mutually independent Muku-l operation instructions in element units. Since the vector instruction is being executed, the idle time in a calculation pipeline due to data neck etc. can be used to process other vector instructions, improving the utilization rate of the calculation pipeline. However, there is an effect of improving the throughput of the vector processing unit.

[Brief explanation of the drawing]

FIG. 1 is a diagram illustrating the principle configuration of the Heritor multiple calculation method of the present invention. FIG. 2 is a diagram showing an embodiment of the present invention. FIG. 3 is a diagram illustrating the conventional Heritre multiple calculation method. It is. In the drawing, 1 is a request acceptor (lto, Ill, -, #n
). 2ba instruction processing unit (#sail #1.-. #k). 21 is the OP code. 22 to 26 are registers (ill, -R4, VL). 27 rolls to Operation Asaincon 1. 28 is a counter (+m). 3 is arithmetic pipe control (#0.Ill, -, Iti). 4 is an arithmetic pipeline (8, B, -). 5 is a data storage device (solid 1 hell register (VR) 1
■,■ are vector instructions or simply instructions. ACPT (110,-) is an acceptance signal. BUSY (#O, -) is a low signal. are shown respectively.

Claims (1)

[Claims] In a pipelined vector processing device, a plurality of mutually independent vector processing instructions are divided into elements to form a plurality of vector processing pipelines (4).
A vector multiplexing method characterized in that means (2, 3) for distributing and processing the plurality of mutually independent vector operation instructions are provided in each vector processing pipeline (4) in units of elements. Calculation method.