JPH01256832A - Synchronization multiplexing control system - Google Patents

Abstract

PURPOSE:To eliminate the need for applying duplicate scrambling at a terminal station and to form a multiplex data economically by selecting the phase difference alpha of scrambling as alpha=2<n>/l ((n) is the number of stages of pseudo random pattern generating circuit, and (l) is the degree of multiplex). CONSTITUTION:Let the number of stages of a pseudo random pattern generating circuit 2 of a scrambler 1 be (n) and the degree of multiplex be l=2<k> (k=1, 2, 3...), then the phase difference alpha of the (l) multiple section corresponding to channels CH1-CHl of the generating circuit 2 is selected to be alpha=2<n>/l. To set the phase difference alpha of the pseudo random pattern to the relation of alpha=2<n>/l, the phase difference alpha has only to be preset at the initial reset of the generating circuit 2. Then the data corresponding to the channel is converted serially and multiplexed, then since the relation of alpha=2<k>/l exists, a multiplex data equivalent to the data subjected to scrambling in the series sampled at the interval of 2<j>=2<n-k> is obtained.

Description

[Detailed Description of the Invention] [Summary] The present invention relates to a synchronous multiplexing control method for transmitting at least scrambled multiplexed data, and is aimed at economically forming multiplexed data. In a synchronous multiplexing control method for transmitting data with multiplicity β, the number of stages of the pseudo-random pattern generation circuit of the scrambler is n, the multiplicity l is 2, and the number of stages of the pseudo-random pattern generation circuit of the scrambler is By setting the phase difference α in the l multiplexing unit corresponding to each channel or the phase difference α in the l multiplexing unit of each scrambled channel frame to the relationship α=2'#, β channels The configuration was designed to multiplex the data.

[Industrial application field]

The present invention relates to a synchronous multiplex control method for transmitting at least scrambled multiplexed data.

In order to statistically bring the mark rate of the transmission code closer to 1/2,
A method is adopted in which the transmitted data is scrambled using a pseudo-random pattern, and "O" is used as the transmission code.
”, for example, 1 for n bits.
Various types of B include nBlc, which adds an inverted bit, nBIMS, which adds a 1-bit mark to n bits, and nBIP, which adds a parity bit to n bits.
S T (Bit 5equence Indep
IC, LM, I
Bits such as P are called BSr bits.

Furthermore, when multiple systems of data are individually scrambled and those data are multiplexed and sent to a transmission path, the multiplexed data must also be scrambled again. In addition, the data for each channel is scrambled, data for multiple channels is multiplexed, this multiplexed data is scrambled again, sent out to the transmission path, and demultiplexed at the receiving end station. Since the channel data is scrambled, demultiplexed data can be sent to the transmission path.

In these systems, the transmitting terminal station performs double scrambling, making the multiplexing device complex and expensive.

Therefore, it is desired to simplify the configuration and make it more economical.

[Conventional technology]

FIG. 7 is a block diagram of a conventional example, in which a 4-channel CHI
- This shows a case where the data of CH4 is multiplexed and transmitted, and the multiplexing unit 41 multiplexes and transmits data of each channel CHI to CH4, for example,
It has a function of scrambling and multiplexing 0 Mb/s data or a function of multiplexing and scrambling, a function of inserting a frame synchronization signal, etc. In the case of an optical fiber transmission line, it is equipped with an electro-optical conversion element such as a semiconductor laser.

When 100 Mb/s data is multiplexed by 4 in order to insert a frame synchronization signal in the multiplexer 41, generally 100 Mb/s data is divided into 50
Slow down to Mb/s and (50Mb/s)
s ) × 9 multiplexing is performed to yield 450 M b /
s multiplexed data.

FIG. 8 shows a case where data of four channels is multiplexed and two channels of data are multiplexed, and the multiplexing section 4 in FIG.
The multiplexing units 41a and 41b similar to 1 multiplex the data of the channels CHI-CH4, CH5 to CH8, respectively, and the multiplexing unit 44 multiplexes the data of the multiplexing unit 41, for example.
The multiplexed data of 450 Mb/s from 3.41b is multiplexed into two and is transmitted from the transmitter 45 to the transmission path 46 as multiplexed data of 900 Mb/s.

In this case, the multiplexing units 41a and 41b perform scrambling, but since it is necessary to correctly scramble the data sent from the transmitting unit 45, the multiplexing unit 44 also performs two-way multiplexing. The converted data will be scrambled again. However, since scrambling is performed in the multiplexing section 44, frame synchronization must be achieved, which requires a complex circuit configuration that operates at high speed, making it difficult to realize the multiplexing section 44 economically. becomes.

When multiplexing the data of 8 channels C'H1 to CH8 in this way, the multiplexing units 41a and 41b.

It is conceivable to provide 8 multiplexing units without using 44. Even in such a configuration, it is possible to multiplex 8 and 90
In order to obtain 0 Mb/s data and to perform scrambling, it is difficult to put it into practical use from the viewpoint of processing speed and economy. Also, a multiplexing section 41a.

41, b multiplexed by e.g. 450 M b
/s data with different wavelengths, for example 1.3
It is conceivable to convert it into optical signals of μm and 1.5 μm, wavelength-multiplex the optical signals, and send them to an optical fiber transmission line. Although such a wavelength multiplexing configuration is also possible, it is not economically advantageous.

In addition, the data of each channel is scrambled and the BS
A system is also known in which the code is transmitted as a 19BIM code in which a mark of 1 bit is inserted every 19 bits.

FIG. 9 is a block diagram of the main parts of the scrambler. The scrambler is composed of an n-stage pseudo-random pattern generation circuit 51 and an exclusive OR circuit 52, and the scrambled data is sent to the multiplexer 53. I was told,
A frame synchronization signal from the frame synchronization generation circuit 54 is inserted and sent out.

The pseudo-random pattern generation circuit 51 is initialized by a reset signal and generates a 2'-1 pseudo-random pattern (
PN) and is added to the exclusive OR circuit 52, where scrambling is performed by exclusive ORing with data. In this case, for example, for high-speed data of about 100 Mb/s or more, an m-bit parallel pseudo-random pattern such as word units is output, and the m-bit parallel data is scrambled and sent to the multiplexer 5.
3, a frame synchronization signal is inserted and converted into serial data.

FIG. 10 is a block diagram of the main parts of the multiplexing section, showing a case where data of four channels CHI to CH4 are multiplexed. In the figure, 61 is an n-stage pseudo-random pattern generation circuit, 62 is an exclusive OR circuit, 63 is a multiplexer, 64 is a frame synchronization generation circuit, and 65 is a parallel-to-serial conversion circuit.

For example, the data of each channel CHI to CH4 is 100M
If it is equivalent to b/s, it is added to the parallel-to-serial conversion circuit 65 as m-bit parallel data, converted to m-bit parallel serial data, and added to the exclusive OR circuit 62, and the data from the pseudo-random pattern generation circuit 61 is It is scrambled by exclusive OR with an m-bit parallel pseudo-random pattern (PN), is added to the multiplexer 63 as m-bit parallel scrambled data, and a frame synchronization signal from the frame synchronization generation circuit 64 is inserted. and converted into serial data of, for example, 450 Mb/s.

Figure 1) is a block diagram of the main parts of the receiving terminal station, for example,
In the CATV system, 4 channels of video signals are multiplexed, 450 Mb/s data is scrambled and sent, and the receiving terminal station separates the demultiplexed 100 Mb/s data corresponding to each channel. After that, in order to retransmit, the 4 5 received by the receiving section 71 is further scrambled and sent to the subscriber.
The multiplexed data of 0 Mb/s is sent to the demultiplexer 72.
Frame synchronization is established, and the one corresponding to each channel is
The data is separated into 00 Mb/s data, and these data are added to the selector 73, where channel selection is performed by a control signal according to request information from subscriber terminals, etc.
The signals are modulated and transmitted from the transmitters 74 to 77 in accordance with the characteristics of the transmission path.

If the transmitting terminal station performs scrambling for each channel CHI to CH4, the data of each channel separated by the demultiplexer 72 will also be scrambled, so the transmitters 74 to 77 will not scramble the data. It can be sent to the transmission line without any additional processing.

However, if the transmitting terminal station does not perform scrambling for each channel CHI to CH4, for example, the multiplexing unit 41 in FIG. When multiplexed data is subjected to scrambling, as shown in FIG. Since the corresponding data is not scrambled, the data corresponding to this channel is scrambled by scramblers 84 to 87, and the data is sent from transmitters 88 to 91 to modulation corresponding to the characteristics of the transmission path. I will go and send it out.

[Problem to be solved by the invention]

When data corresponding to a channel is scrambled and transmitted individually, and when these data are multiplexed and sent out to the transmission path, or when the receiving end station retransmits the demultiplexed data, it is necessary to It is necessary to send scrambled data. When retransmitting data that has been received and demultiplexed as in the latter case, if the data corresponding to the channel is not scrambled at the transmitting terminal station, scramblers 84 to 87 are installed at the receiving terminal station as shown in FIG. Therefore, the configuration of the receiving terminal station becomes complicated. Therefore, it is required that the transmitting terminal station scrambles the data corresponding to the channel.

In these cases, even if the data corresponding to the channel is scrambled and multiplexed, there is a possibility that consecutive same codes may occur, so it is necessary to scramble the multiplexed data again. occurs. That is, as shown in FIG. 8, in the past, it was necessary to employ a configuration in which scrambling is performed each time multiplexing is performed, which has the drawback that the configuration of the multiplexing section of the transmitting terminal station is complicated and expensive.

The invention aims at economically forming multiplexed data.

[Means to solve the problem]

The synchronous multiplexing control method of the present invention selects the phase difference for multiplexing based on the relationship between the degree of multiplicity and the number of stages of the pseudo random pattern generation circuit of the scrambler. Refer to and explain.

The number of stages of the pseudo-random pattern generation circuit 2 of the scrambler 1 is n, and the multiplicity is 1=2k (k=1゜2.3...
), the phase difference α in the l multiplexing section corresponding to channels CHI to CH1 of the pseudo-random pattern generation circuit 2,
Or scrambled channels CHI to CHI
The phase difference α at the l multiplexing section of the O frame is α=2・/i
t and multiplexed by the parallel-to-serial converter 3.

In addition, when BSI-converted billa bits are inserted, the insertion period is W, and l of the scrambled frame of each channel is
The phase difference α2 in the multiplexing unit is set to the relationship α2=w/l, and the phase difference αi in the β multiplexing unit corresponding to channels CHI to CHI of the pseudo-random pattern generation circuit 2 is set to
is set to 2'/l, and multiplexed by the parallel-to-serial converter 3.

Moreover, this phase difference αi. In order to simultaneously realize α2, the phase difference α2 is set, and in order to give the phase difference αi in the multiplexer, the preset value α3(1 ), α3(il=
Set as α3(1)+(i 1) (αi+α2).

[Effect]

M sequence (Maximum length) used for PN code
thsequence) has a period of 2k-1, and the sequence obtained by sampling every 2J in this M sequence also has the property of being an M sequence. Based on this known theory, the channel CHI input to the parallel-to-serial converter 3
NCHj! The corresponding data can be obtained by setting the phase difference α to 2'/l for the frame phase or scramble phase, and then
The relationship is α].

In order to set the phase difference α of the pseudo-random pattern to a relationship of 2'/1, it is sufficient to preset the value of the phase difference α at the initial reset of the pseudo-random pattern generation circuit 2. In order to set the phase difference of the pattern generation circuit 2 to O and the frame phase difference α to the above-mentioned relationship, it is sufficient to provide a panzer memory or the like and delay it in accordance with each channel. Then, by serially converting and multiplexing the data corresponding to the channels, (since 1 = 2 k, multiplexing equivalent to data scrambled with a sequence sampled every 2' = 2k -') Data is obtained.

In addition, when multiplexing data that has been input with BSI-converted billa bits, based on the BSI-converted billa-bit input period W and the multiplicity l,
The phase difference α2 at the l multiplexing part of the frame is α2 = w
/1, and the phase difference αi in the l multiplexing section of the pseudo-random pattern generation circuit 2 is set to 21'/l, and the multiplexed data is input with BSI bits at a predetermined period, and is scrambled. has been applied.

Further, as a method of providing the phase difference α2, a method of performing a synchronization operation of each channel by shifting the phase toward α2, a method of actually delaying the data of each channel, etc. can be used.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 2 is a block diagram of an embodiment of the present invention, showing a case where data of eight channels CHI to CH8 are multiplexed.

In the figure, 1)-1.1)-2 is a multiplexing unit, 12-
1.12-2 is an n-stage pseudo-random pattern generation circuit, 13-1.13-2 is an exclusive OR circuit, 14 is a parallel-to-serial converter for multiplexing, 15 is a transmitter, 16-1 to 1
6-8 is an A/D converter.

The transmitter 15 has a modulation transmission function corresponding to the characteristics of the transmission path, and when transmitting via an optical fiber transmission path,
It has the function of converting into an optical signal using an electro-optical conversion element such as a semiconductor laser and transmitting the signal.

For example, video signals of the input channels CHI to CH8 are converted into digital signals by A/D converters 16-1 to 16-8, and are added to multiplexers 1)-1.1)-2, respectively. 4 multiplexed, scrambled by a pseudorandom pattern from pseudorandom pattern generation circuits 12-1 and 12-2, and a frame synchronization signal is inserted. This multiplexing section 1)-1.1)-
2 has the configuration shown in FIG. 10, for example, and the multiplexing unit 1)
-1 to the multiplexer 1)-2, and generates a pseudo-random pattern generation circuit 12-1.12-.
This is to perform the second synchronous operation.

If the multiplicity l of the parallel-serial converter 14 is 2, and the number n of stages of the pseudo-random pattern generation circuits 12-1 and 12-2 is, for example, 7, then the pseudo-random pattern generation circuits 12-1, 12-2 The pseudorandom pattern of is 2
'-1=12n, and their phase difference α is α=2k
/1=2n/2=64. Therefore, pseudorandom
When the pattern generation circuit 12-1 is initially reset, it is preset to 1, and the pseudo-random pattern generation circuit 12-2 is preset to 1.
At the time of initial reset, 1+64=65 is preset and the devices are operated synchronously.

Each channel CH by A/D converter 16-1 to 16-8
For example, the video signal of I to CH8 is 100Mb/s
When converted into a digital signal, the multiplexer 1)-1.
1)-2, as mentioned above, 450 M
The data will be b/s. Then, by 2 multiplexing by the parallel-to-serial converter 14, 900 Mb
/s multiplexed data and is scrambled. This multiplexed data is modulated by the transmitter 15 in accordance with the characteristics of the transmission path, and is transmitted to the transmission path.

The parallel-to-serial converter 14 includes a multiplexer 1)-1 that multiplexes four
．． 1) The multiplexed data from 2 is further multiplexed by 2, but it is economical because it simply converts 2 parallel data into serial data and does not insert a frame synchronization signal etc. This is also a feasible configuration.

FIG. 3 is an explanatory diagram of the above-mentioned multiplexing, and shows the multiplexing section 1)-
The multiplexed data scrambled from 1 to Xn(
θ), the scrambled multiplexed data from the multiplexer 1)-2 has a phase difference of α, so Xn
(θ+α).

The numbers indicate pseudo-random pattern generation circuit 12-1.1
2-2, the first bit of the pseudo-random pattern from the pseudo-random pattern generation circuit 12-1 and the pseudo-random pattern generation circuit 12-2 with a phase difference of 64. The scrambled data corresponding to the 65th bit of the pseudorandom pattern is applied to the parallel-to-serial converter 14 and multiplexed, and the multiplexed data becomes Xn(θ+β). This multiplexed data Xn(θ+β) is also correctly scrambled due to the properties of the M sequence described above.

Therefore, since the multiplexed data obtained by multiplexing scrambled data is also scrambled data, there is no need to perform scrambling again, and the configuration of the multiplexing section of the transmitting terminal becomes simple. Also, depending on the purpose of use, the same multiplexing section 1)-1 can be used for 4-channel transmission and 8-channel transmission. Furthermore, at the receiving end station, the data that has been demultiplexed into two is scrambled, so that the data can be retransmitted as is to the transmission path.

Also, pseudo-random pattern generation circuit 12-1゜12-2
When the phases of the pseudo-random patterns are matched and scrambled, the multiplexer 1)-1.1)
The frame phase difference between the data of channels CH1 to CH4 and the data of channels CH5 to CH8 that are input to -2 is set to α, and in that case, as shown in Fig. 3, scrambled multiplexed The phase difference of the encoded data becomes α, and the data multiplexed by the parallel-to-serial converter 14 is correctly scrambled as described above.

FIG. 4 is a block diagram of another embodiment of the present invention, showing a case of four-way multiplexing, in which 21-1 to 21-4 are scramblers that also insert frame synchronization signals, 22-1 to 22-4
are pseudo-random pattern generation circuits, 23-1 to 23-
4 is an A/D converter, 24 is a parallel-to-serial converter, and 25 is a transmitter.

For example, video signals of channels CHI to CH4 are converted into digital signals by A/D converters 23-1 to 23-4, and are applied to scramblers 21-1 to 21-4, respectively, to generate pseudo-random pattern generation circuit 22. -1 to 22
Scrambling is performed using a pseudo-random pattern from -4, and a frame synchronization signal is inserted, and Xn(
θ), Xn(θ+α), Xn(θ+2α), Xn(θ+
3α), the data of each phase difference α is sent to the parallel-to-serial converter 2.
4, multiplexed into 4 and added to the transmitter 25,
It is transmitted after being modulated in accordance with the characteristics of the transmission path.

The scramblers 21-1 to 21-4 can adopt, for example, the configuration shown in FIG. 21-4 are operated synchronously.

In this embodiment, the multiplicity l is 22=4, and if the number of stages n of the pseudo-random pattern generation circuits 22-1 to 22-4 is 7, then the pseudo-random pattern generation circuits 22-1 to 2
The phase difference α of 2-4 is α-2n/22=32. Therefore, if the preset value of the pseudorandom pattern generation circuit 22-1 is 1, the preset value of the pseudorandom pattern generation circuit 22-2 is 33, the preset value of the pseudorandom pattern generation circuit 22-3 is 65, and the preset value of the pseudorandom pattern generation circuit 22-3 is 65. Set the preset value of the random pattern generation circuit 22-4 to 97.
Based on the pseudo-random pattern generation circuit 22-1, the phase differences of the other pseudo-random pattern generation circuits 22-2 to 22-4 are α, 2α,
It becomes 3α.

FIG. 5 is an explanatory diagram of multiplexing in the above-mentioned embodiment, and since the phase difference α is 32, the scramblers 21-1 to 21-2
The data from Data is parallel to serial converter 2
4, the scrambled data corresponding to the next 2nd bit, 34th bit, 66th bit, and 98th bit are converted into serial data and applied to the transmitter 25, and then the scrambled data corresponding to the next 2nd bit, 34th bit, 66th bit, and 98th bit are sent to the parallel-to-serial converter 24. The signal is converted into serial data and applied to the transmitter 25. Therefore, according to the above-mentioned known theory,
The multiplexed data Xn(θ+β) is also correctly scrambled data due to the properties of the M sequence described above.

Also, pseudo-random pattern generation circuits 22-1 to 22-4
It is also possible to multiplex the frames of data corresponding to channels CHI to CH4 manually inputted to the parallel-to-serial converter 24 by setting the phases to the same and setting the phase difference α to α, and in this case, the multiplexed data is also scrambled. It becomes something.

FIG. 6 is an explanatory diagram of multiplexing in the case of BSI-adapted billa bits (al indicates data of each channel of 15B1'M code, M indicates mark bit. In this case, the BSI-adapted billa bit input period W is 16, and the multiplicity l is 4, so the pseudo random pattern generation circuits 22-1 to 22
-4, the number of stages n is 7, the phase difference αI in the l multiplexing section of the pseudorandom pattern generation circuits 22-1 to 22-4
-2″#=2n/4=32, and the frame phase difference of the channel in the β multiplexer α2 = W/l = 16
/4'-4. Such a phase difference αi. α2, pseudo-random pattern generation circuits 22-1 to 22-4
The multiplexing is performed by setting a preset value of , or the amount of data delay of each channel.

Moreover, the phase difference αi. In order to simultaneously realize α2, the phase difference α
2 is actually given, and then the Bricesotoy direct α3(1) of the pseudo-random pattern generation circuit of the i-th channel is expressed as α3(1)−α3(1)+(i −1) (αi
+α2). In this case, if the preset value α3 (1) = 1 for the first channel,
2.3.4th channel preset value α3 (21
, α3(3), α3(4) are α3(2)=1+
(2-1)(32+4)=37α3(31=1+(31
) (32+4) =73α3(41=1+ (4-
1) (32+4)=109.

Therefore, as shown in (b) to (e), the data of the first to fourth channels input to the parallel-to-serial converter 24 have frame phases of 4.0 and 4.5, respectively, based on the data in (b). 8.12 bit difference, and scrambled
Each bit of data has a phase difference of 32 bits,
For example, scrambled data corresponding to the 13th bit, 45th bit, 77th bit, and 109th bit of the data of the first to fourth channels are converted into serial data and multiplexed. Then, the multiplexed data becomes data in which mark bits M are inserted at a 4-bit period and scrambled data is obtained.

When such multiplexed data is demultiplexed at the receiving terminal,
Since the data is separated into the data shown in (bl to (8)) in FIG. 6, the BSI-converted billa bits are added to each data and scrambled, and it is possible to retransmit it to the transmission line as it is.

The present invention is not limited to the above-mentioned embodiment, but can perform multiplexing by arbitrarily selecting the multiplicity 1 = 2 k, the number of stages n of the pseudorandom pattern generation circuit, the insertion period W of BSI bits, etc. It is something that can be transformed into

〔Effect of the invention〕

As explained above, in the present invention, the phase difference α of scrambling is set to α-2″/l in the relationship between the number of stages n of the pseudo-random pattern generation circuit 2 and the multiplicity l, thereby achieving multiplexing. The transmitted data is also scrambled, and there is no need for double scrambling at the transmitting terminal, which has the advantage of being an economical configuration.

In addition, in the case where BSI converted billa bits are included to facilitate reception processing, the phase difference α+=2'/j! By multiplexing the frame phase difference α2 of each channel as α2=w// using the BSI bit input period W, the BSI bits are inserted at a period according to the phase difference α2, and scrambling is performed. Since the transmission terminal station does not need to perform double scrambling, it has the advantage of being an economical configuration.

Further, in the l multiplexing section, after giving the phase difference α2, the preset value α3(1) of the pseudo-random pattern generation circuit of the i-th (i=1.2.'...1) channel is set. ,α
3(1)=α3(1)+(i 1) (α.

By setting the relationship as +α2), the data of each channel can be scrambled with a predetermined phase difference of −, and the multiplexed data will also be scrambled, making the configuration of the transmitting terminal more economical. can be achieved.

[Brief explanation of the drawing]

FIG. 1 is a diagram explaining the principle of the present invention, FIG. 2 is a block diagram of an embodiment of the present invention, FIG. 3 is a diagram explaining multiplexing of an embodiment of the present invention, and FIG. Block diagram of the embodiment, fifth
FIG. 6 is an explanatory diagram of multiplexing according to another embodiment of the present invention, FIG. 6 is an explanatory diagram of multiplexing including BSI bits of the present invention, FIGS. 7 and 8 are block diagrams of the conventional example, and FIG. A block diagram of the main parts of the scrambler, FIG. 10 is a block diagram of the main parts of the multiplexing section,
FIG. 1) and FIG. 12 are block diagrams of main parts of the receiving terminal station. CHI to CH6 are channels, 1 is a scrambler, 2 is a pseudo-random pattern generation circuit, 3 is a parallel-to-serial converter,
1)-1.1)-2 is a multiplexing unit, 12-1.12-2 is a pseudo-random pattern generation circuit, 13-1.13-2
14 is a parallel-to-serial converter, 15 is a transmitter, and 16-1 to 16-8 are A/D converters. Fig. 1 is an explanatory diagram of the principle of the present invention. Fig. 2 is a block diagram of an embodiment of the invention. Fig. 4 is a block diagram of another embodiment of the invention. Figure 5: Block diagram of conventional example Main part block diagram of scrambler Figure 1:15 Figure 1o Figure 1o Main part block of control signal receiving terminal station 'Lock diagram Figure 12

Claims (3)

[Claims] (1) In a synchronous multiplexing control system for transmitting at least scrambled data with a multiplicity l, the number of stages of the pseudo-random pattern generation circuit (2) of the scrambler (1) is n, and the The severity l is 2^k (k=1
, 2, 3, . . . ), the phase difference α in the channel-corresponding multiplexer of the pseudo-random pattern generation circuit (2) or the scrambled frame between each channel in the multiplexer A synchronous multiplexing control method characterized in that data of l channels are multiplexed by setting a phase difference α of α=2^n/l. (2) In a synchronous multiplexing control system that transmits data with a multiplicity l that has been scrambled and has BSI bits inserted, the pseudo-random pattern generation circuit (2) of the scrambler (1) The number of stages is n, and the multiplicity l is 2^k (k=1
, 2, 3, ...) and the insertion period of the BSI bit is w, the phase difference α_2 at the l multiplexing section of the frame of each scrambled channel is α_2=w.
/l, and furthermore, the phase difference α_i in the channel-corresponding l multiplexing section of the pseudo-random pattern generation circuit (2) is set to 2^n/l, and the data of the l channels are multiplexed. A synchronous multiplex control method characterized by: (3) The phase difference α_2 in the l multiplexing unit of the scrambled frame of each channel is set to the relationship α_2=w/l, and the pseudo-random pattern generation circuit (2 ) preset value α_3(i), α
_3(i)=α_3(1)+(i-1)(α_i+α_
3. The synchronous multiplexing control system according to claim 2, wherein the data of l channels is multiplexed by setting the relationship of 2).