JPH01253879A - Disc memory servo index system - Google Patents

Abstract

PURPOSE: To improve indexation of a disk memory servo by attaining identification of a track due to absence of a track positioning gate signal with a timing circuit constituted of a gate, an FF and a one shot multiviblator. CONSTITUTION: Although the multivibrator 50 is inverted in response to synchronizing pulses S2, S3, the vibrator 50 doesn't invert when the pulse S3 doesn't exist, and thus, the inversion Q output of the FF 38 is high as it is, and thus, an SIG gate signal in the output of a NAND gate is prohibited. Then, the SIG gate signal is monitored, and when the absence of the SIG gate signal exists once at every 10 frames, a guard band is instructed, and when the absence of the SIG gate signal exists once at every 30 frames, a track zero is instructed. Then, the prohibited SIG gate signal is added to the FF 60 as a negative pulse, and its output inverts the output of the multivibrator 62 to output a track zero signal.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) This invention generally relates to magnetic disk memory systems;
In particular, it relates to servo indexing systems in magnetic disk memories.

(Prior Art and Problems) A magnetic disk memory includes a plurality of disks mounted in spaced parallel relationship on a common principal axis.

Data is magnetically stored along concentric tracks in a magnetic coating on the disk surface.

Data is recorded and accessed by a pickup head that moves across the full disk surface as the disk rotates.

Generally, one of the disk surfaces is dedicated for servo control of the pink-up head. Data is detected by dedicated servo-controlled pickup heads at the outer and outer limits of the data track, guard bands, data track zero,
and the data track of its bullion can be identified. recorded on multiple tracks. Additionally, pulses are provided that allow precise alignment of the pink-up head to each track.

The data within each track is arranged in frames. Generally, a first plurality of pulses within each frame is used to identify track conditions and a second plurality of pulses is used for pink-up head alignment. For example, the 18M3350 disk drive uses two sync pulses at the beginning of each frame to encode data bits and uses four additional pulses (Sig and Quad) for track alignment. The presence or absence of one of the two sync pulses sets the data bit to “1” or “
U.S. Pat. No. 4,495,533 discloses a similar configuration, but according to the description, it solves the problem of continuous erroneous data that occurs when the rotational speed of the disk changes. The system also uses a crystal clock oscillator to synchronize and control the circuit. Recognizing the problem of oscillator control when using a servo track, a circuit is disclosed that delays selected clock pulses to keep them synchronized with the data read from the servo track.

An object of the present invention is an improved servo indexing system.

Another object of the invention is a servo indexing system that does not require a crystal clock oscillator for timing and synchronization.

(Means for Solving the Problems) A feature of the present invention is the use of a timing circuit comprised of gates, flip-flops and one-shot multivibrators to provide synchronization and track identification.

In summary, two groups of one or more synchronization pulses are provided within each frame in the serve track to generate track alignment gate signals (Quad and Sig). Prohibition of generation of Quad or Sig gate signal once every predetermined number of frames is performed by guard band, track zero,
and all other data tracks can be identified.

In a preferred embodiment, each frame includes a first sync pulse that generates a Quad gate pulse, and second and third sync pulses that jointly generate a 51g gate pulse. The absence of either the second or third sync pulse inhibits generation of the 51g gate pulse.

Guard bands are identified by inhibiting one 51g gate pulse every 10 frames, and track zero is identified by inhibiting one 51g gate pulse every 30 frames. Importantly, track identification due to the absence of 51g gate pulses is accomplished by a timing circuit consisting of gates, flip-flops, and one-shot multivibrators.

The invention and its objects and features will become more readily apparent from the following detailed description, taken in conjunction with the drawings, and from the claims.

(Example) Referring to the drawings, FIG. 1 is a perspective view showing a part of a magnetic disk drive. The disk drive includes a plurality of disks 10, the surface of each disk 10 having a magnetic coating for recording data bits, such as "1's" and "0's." Data bits are recorded along concentric tracks on the disk surface, and the data is grouped into each frame of data words. Data bits are recorded and accessed by a magnetic head 12 that is driven across the surface of the disk 10 by a carriage assembly 14 as the disk 10 rotates.

As mentioned above, generally one surface of one disk is used for servo control of the carriage assembly 14 and for the pickup head 1.
It is used exclusively for the positioning of step 2. Magnetic pulses are recorded in each frame of the track on the servo surface so that the position of the pink-up head on the guard band or data track can be identified and proper positioning of the pickup head within the data track can be determined. As shown in FIG. 2, for example, the 18M3350 pulse format includes two synchronization pulses S1 and 82 followed by four position pulses W1-4 within each frame. The presence or absence of the first sync pulse S1 codes the data focus, and the bits of a plurality of consecutive frames determine guard bands, track zero, or other data tracks. The aforementioned U.S. Pat. No. 4,495.533 uses a similar pattern, but uses the presence or absence of a second sync pulse S2 to record data bits. The patent also states that following reception of the synchronization bit <track position bit W1
It also teaches the use of a crystal controlled oscillator to time the access to ~W4. However, in that patent, pulse discrimination problems arise if the oscillator is not synchronized to the rotational speed of the disk.

According to the invention, a unique bit pattern is used that does not require a crystal controlled oscillator and is accessible by unique circuitry. This circuit uses monostable one-shot multivibrators, flip-flops, and logic gates to identify track indicators, guard bands, and data tracks. As shown in FIG. 3A, the index frame at the beginning of each track is 22 segments long and includes a first sync pulse S1, followed by a <Quad pulse and four consecutive sync pulses 82-S5, and Both the Quad and Sig pulses are used to align the head within each track.

All other frames on the servo disk surface are 3B
It has a pattern as shown in the figure. In this pattern,
The first sync pulse S1 is followed by a Quad pulse, and the next two sync pulses S2, S3 are followed by a 53g pulse. In response to the sync pulse, circuitry is provided to generate a gate signal at the appropriate time after the sync pulse to sample both the Quad and Sig pulses recorded on the surface of the servo disk. Additionally, this circuit uses four consecutive synchronization pulses 82 to S in the index frame.
5 and the presence of the two synchronizing pulses S2 and S3 shown in FIG. 3 or the two synchronizing pulses S2 and S3
The guard band, track zero and other data tracks are recognized by the absence of one of them.

FIG. 4 shows Quad and Sig in response to a synchronization pulse.
In addition to generating both gate signals, the index, track zero,
FIG. 2 is a schematic diagram of an embodiment of a circuit for generating a guard band detection signal and a guard band detection signal. The detected synchronization pulse is applied to the B input of one-shot multivibrator 28 (4G) and the C input of flip-flop 34.38 (5F). Multi-by-break 28 (4G) one-shot output is 3o
The output of the charging circuit 3o is applied to the inputs of the differential amplifiers 32 and 36 (4F).

The output l of the amplifier 32 (4F) is output from the flip-flop 34.
(5F) is added to the D input of the flip-flop 34 (
The C output of 5F) becomes the index detection signal.

The output of the charging circuit 30 is also applied to the input of a differential amplifier 36 (4F), and the output cuff of the differential amplifier 36 is connected to the D input of a flip-flop 38.

The C output of flip-flop 38 is added to the output of NAND gate 40, and the C output of flip-flop 38 is
Each of AND gate 42 and NAND gate 44 - is added to the human power.

Another flip-flop 46 has a C input connected to the output of NAND gate 48, and the output of flip-flop 46 is connected to the input of NAND gate 40. N
The output of AND gate 40 is connected to the output of NAND gate 48, and the output of NAND gate 52 is connected to the A input of one-shot multivibrator 50. The C output of multivibrator 50 is connected to the A input of multivibrator 28 and the inputs of both NAND gates 42,48. The output of NAND gate 42 is connected to one output of NAND gate 52, and the outputs of both NAND gates 52 and 44 are cross-connected as shown.

The Sig gate signal is derived from the output of NAND gate 48 and the Load gate signal is derived from the output of NAND gate 42. The Sig gate signal is connected to the input of a one-shot multivibrator 60 and has a pulse duration on the order of 15 microseconds.

The C output of the one-shot multivibrator 6o is connected to the input of another one-shot multivibrator 62,
It has a pulse duration of approximately 240 microseconds. The C output of the multi-by-break 60 is also connected to the C input of the flip-flop processor 4 and the C input of the flip-flop 66. The output of one-shot multivibrator 62 is connected to the D input of flip-flop 64, and the C output of flip-flop 64 is connected to the D input of flip-flop 66. The track zero signal is obtained from the output of the one-shot multivibrator 62 once every 30 frames in response to the absence of one of the synchronization pulses S2 and S3, and the guard band detection signal is obtained once every 10 frames from the output of the one-shot multivibrator 62 when the synchronization pulse ζ of flip-flop 66 in response to the absence of S3
Obtained from the output. The presence of all three sync pulses S1, S2 and S3 during 30 frames indicates a data track other than track zero.

Next, consider the timing diagrams of FIGS. 5A-5C in conjunction with the circuit of FIG. 4. In FIG. 5A, the presence of four synchronization pulses 82-S5 in the index frame causes a positive voltage level to be applied to the D input of flip-flop 34 when synchronization pulse S5 is applied to the C input of flip-flop 34. As shown in the figure, the flip-flop 34 (5
Invert the output of F). 4 synchronization pulses 82~S5
If there is no ζ of flip-flop 34 (5F)
The output is at a positive voltage level.

FIG. 5B shows the inhibition of the 51g gate pulse due to the absence of synchronization pulse S3 in the format of FIG. 3B.

As shown, multivibrator 50 normally inverts in response to two synchronization pulses S2, S3. However, in the absence of synchronization pulse S3, multivibrator 50 does not invert, and accordingly, the output of flip-flop 38 remains high. When the ζ output of flip-flop 38 is high, the Sig gate signal at the output of the NAND gate is inhibited.

The Sig gate signal is monitored such that one absence of the Sig gate signal every 10 frames indicates a guard band and one absence of the Sig gate signal every 30 frames indicates a track band, as shown in Figures 50 and 5D. Indicates zero.

The presence of a Sig gate signal in every frame indicates that entire data track. In Figure 5C,
The inhibited Sig gate signal appears as a negative pulse that is applied to flip-flop 60 such that the output of flip-flop 60 is a 15 microsecond negative pulse as shown in FIG. 5C. flip flop 62 240
The microsecond output goes high and remains high in response to a negative pulse that repeats every 10 frames. The positive output of the multi-by-break 62 causes the output of the flip-flop 64 to go high, and the ζ output of the flip-flop 66 goes low, indicating guard band detection.

Referring to FIG. 5D, since the duration of the multi-by break 62, 240 microseconds, is shorter than the interval period of 330 microseconds between repeated negative 51 g gate pulses, the absence of one 51 g gate pulse every 30 frames causes the multi-by break 62 to is reversed. This inversion of multi-by-break 62 is detected as a track zero signal.

(Effects of the Invention) According to the present invention, detection of a unique servo pattern by a circuit using a monostable one-shot multivibrator, a flip-flop, and a gate circuit improves the precision and reliability of pulse detection in the servo pattern. let Synchronization of the oscillation circuit and the rotational speed of the magnetic disk is unnecessary. Although the invention has been described with reference to specific embodiments, the foregoing description is illustrative of the invention and should not be construed as limiting the invention. Various modifications and applications will occur to those skilled in the art without departing from the true spirit and scope of the invention as defined by the claims.

[Brief explanation of the drawing]

1 is a perspective view showing a magnetic disk drive; FIG. 2 is a view showing servo signals according to the prior art; FIGS. 3A and 3B are views showing servo signals according to an embodiment of the present invention; FIG. 4 is a view showing servo signals according to an embodiment of the present invention; Schematic diagram of a circuit for identifying track index, guard band, track zero, and all other data tracks in response to the servo signals of Figures 5A and 3B;
Figures C and 5D show sequences of 51g gate pulses that identify guard bands, track zero, and all other data tracks, respectively. DESCRIPTION OF SYMBOLS 10... Disk, 28... First one-shot multi-vibration break, 30... Charging circuit means, 38...
1st flip-flop circuit, 48... first logic gate means, 60. 62... one-shot multivibrator circuit.

Claims (1)

[Claims] 1. A plurality of data tracks and a guard band, each data track and guard band including a plurality of frames;
Each frame includes first and second groups of synchronization pulses each consisting of at least one group of synchronization pulses, the first group of synchronization pulses being followed by a first track alignment signal (Quad), and the second group of synchronization pulses being followed by a first track alignment signal (Quad); A servo disk in a magnetic disk drive followed by a second track alignment signal (Sig). 2. The servo disk of claim 1, wherein track identification is provided by selectively removing synchronization pulses of a plurality of frames. 3. The servo disk of claim 1, wherein guard bands are identified by removing one sync pulse every 10 frames and data track zero is identified by removing one sync pulse every 30 frames. 4. In a method for identifying guard band tracks and data track zero on a disk surface: applying a magnetic pulse to a plurality of frames and each track on the disk surface, each magnetic pulse in each frame being at least one synchronization pulse; The first group of synchronization pulses is followed by a first track alignment signal (Quad), and the second group of synchronization pulses is followed by a second track alignment signal (Quad). Sig) and selectively removing synchronization pulses in a plurality of frames of each track. 5. Said step of selectively removing synchronization pulses is performed for guard band identification.
5. The method of claim 4, comprising removing one sync pulse every 0 frames and removing one sync pulse every 30 frames for data track zero identification. 6. A magnetic disk including a servo disk surface having magnetic pulses arranged in a plurality of frames in concentric tracks, each frame including first and second groups of synchronization pulses each consisting of at least one synchronization pulse. In the drive, a circuit that generates a signal identifying a track in response to the synchronization pulse includes: a first monostable one-shot multivibrator that generates a pulse in response to the synchronization signal; responsive to a plurality of synchronization pulses in a group; charging circuit means for connecting said first monostable one-shot multivibrator to said charging circuit means; means connected to said charging circuit means for generating a first output signal in response to said trigger signal; a first flip-flop circuit for generating a Sig gate pulse; first logic gate means for generating a Sig gate pulse in response to the presence of the output signal; and means for identifying a track in response to the periodic generation of the Sig gate pulse;
circuit with. 7. said means responsive to periodic occurrences of said Sig gate pulses identifying a guard band in response to one loss of said Sig gate pulse during a first time period; 7. The circuit of claim 6 including a one-shot multivibrator circuit for indicating track zero in response to the loss of said Sig gate pulse.