JPH01253676A - Sonar phasing circuit - Google Patents

Sonar phasing circuit

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Publication number
JPH01253676A
JPH01253676A JP63080675A JP8067588A JPH01253676A JP H01253676 A JPH01253676 A JP H01253676A JP 63080675 A JP63080675 A JP 63080675A JP 8067588 A JP8067588 A JP 8067588A JP H01253676 A JPH01253676 A JP H01253676A
Authority
JP
Japan
Prior art keywords
phasing
channel
delay
azimuth
staves
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP63080675A
Other languages
Japanese (ja)
Other versions
JP2696898B2 (en
Inventor
Toshio Ishiyama
石山 敏夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP63080675A priority Critical patent/JP2696898B2/en
Publication of JPH01253676A publication Critical patent/JPH01253676A/en
Application granted granted Critical
Publication of JP2696898B2 publication Critical patent/JP2696898B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Abstract

PURPOSE:To perform a phasing to synthesize a desired wave receiving directivity in an azimuth range of l<0>, by arranging n channels of l<0> range delay phasing devices, phasing controllers, channel selectors and selection controllers. CONSTITUTION:N channels of l<0> range delay phasing devices 1(1-1-1-n) have (n) delay values for adjusting phase necessary for performing a phasing of (n) staves of transmitter/receivers arranged in a bearing of l<0> to be applied to a transmitting/receiving input. Receiving bearing information, a phasing controller 3 controls and sets the delay value for the phasing devices 1. Channel selectors 2(2-1-2-n) connect the delay phasing devices 1 to a cylinder array type transmitter/receiver being ready for phasing corresponding to a bearing to be directed to each of desired adjacent l<0>/n phase shifters. Receiving information on directivity bearing, selection controllers 4 connect the phasing devices 1 to adjacent (n) stave transmitters in an initialized azimuth range in the phasing within l<0> and when a turning is made in a bearing exceeding l<0>, the controllers do them to (n) staves of transmitter/receivers containing those shifted by one step in the direction of turning. This enables a sonar phasing with a simple switching construction.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明はソーナー整相回路に関し、特に円筒配列型〕ス
受波器を利用するソーナー整相回路に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a sonar phasing circuit, and more particularly to a sonar phasing circuit that utilizes a cylindrical array type space receiver.

〔従来の技術〕[Conventional technology]

円筒配列型)X受波器を利用し、所望の送受指向性を形
成するためのソーナー整相回路はよく知られている。
A sonar phasing circuit for forming a desired transmission/reception directivity using a cylindrical array (type) X receiver is well known.

第2図は従来のソーナー繋相回路の代表的t74成を示
すブロック図であり、走波指向性を形成する場合を例と
している。第2図に示すソーナー整相回路は、n個の、
C°/n幅遅延整相器5−1〜5−n、n個のチャンネ
ル切替器6−1〜6−n、整相制御器7、チャンネル切
替制御器8を備えて構成される。
FIG. 2 is a block diagram showing a typical t74 configuration of a conventional sonar phase connection circuit, taking as an example the case of forming a traveling wave directivity. The sonar phasing circuit shown in FIG.
It is comprised of C°/n width delay phasing devices 5-1 to 5-n, n channel switchers 6-1 to 6-n, a phasing controller 7, and a channel switching controller 8.

円筒形配列型の送波器から送出されるソーナー装置の送
信信号に対して所望の指向性を付与するには、整相処理
か基本的に利用される。この処理は、360°にわたっ
て円筒形配列したmステープの送波器のっし、整相対象
とするQoの方位角範囲におけるnステーフの送波器に
対して、配列条件による音波の伝搬行程差を無くし、恰
もnヂャンイ・ルの直線配列送波器と等価な送波状態を
形成するシェープインク(s b a c3 i n 
g ) 、ならびに所望の指向性を得るためにシェープ
インクにチャンネルことの重みっけを行なうフエーデイ
ング(f a d j、 ng )を含む整相量を遅延
量の調節によって付与することによって行なわれる。
In order to impart desired directivity to the transmission signals of the sonar device transmitted from the cylindrical array type transmitter, phasing processing is basically used. This process is based on the difference in the propagation path of the sound wave depending on the arrangement conditions for m-staple transmitters arranged in a cylindrical shape over 360° and n-staple transmitters in the azimuth range of Qo to be phased. Shape ink (sba c3 i n
g), and by adjusting the delay amount to apply a phasing amount including fading (f a d j, ng ) that weights the channel to the shape ink in order to obtain the desired directivity.

第4図は従来の整相の説明図である。第4図により、送
1スの場合を例として説明する。
FIG. 4 is an explanatory diagram of conventional phasing. Referring to FIG. 4, the case of one pass will be explained as an example.

第4図は全fflステーブのうちステー71からステー
ブ1〕のρ°の方位角範囲にわたる送波器に対して整相
処理による出力を印加し矢印方向に送信指向性を合成す
る場合を示している。
Figure 4 shows a case in which the output from the phasing process is applied to the transmitter over the azimuth angle range of ρ° from stay 71 to stave 1 among all the ffl staves, and the transmission directivity is synthesized in the direction of the arrow. There is.

このような整相によって形成される指向性の方位を変え
るには1.Q / n °内であらかしめ設定する刻み
度数の方位角シフトを整相回路て設定しうるようにし、
!2 / n ’を超える場合は送波器チャンネルシフ
トを行ないこれら2つの方位角設定の絹合せによって所
望の指向を行なわせている。
To change the direction of the directivity formed by such phasing, 1. It is possible to set the azimuth angle shift of the step number within Q / n ° by using a phasing circuit,
! If it exceeds 2/n', the transmitter channel is shifted and the desired pointing is achieved by matching these two azimuth angle settings.

第2図において、】〕個のρ、−’ n ’幅遅延整相
器5−1〜5−nは、所望方位を指定する整相方位信号
102を受けた整相制御器7によってρ/n°内の遅延
整相量分を分担するように制御され、チャンネル切替器
6−1〜6−1〕は、整相量がp/ r+°を超えると
き、送信信号を印加すべき送波器のステーブを1個づつ
歩進させるように切り替えるようにチャンネル切替制御
器8によって切り替えられる。この場合、チャンネル切
替器6−]]〜6−1は、全数mステーブの送波器から
相隣るnチャンネルを整相方位信号102の指定方位に
対応して選択するように切り替えられ、送信信号人力1
0]の整相出力を送波器に印加する。
In FIG. 2, ]] ρ, -'n' width delay phasers 5-1 to 5-n are controlled by a phasing controller 7 that receives a phasing azimuth signal 102 specifying a desired azimuth. The channel switchers 6-1 to 6-1] are controlled to share the delay phasing amount within n°, and when the phasing amount exceeds p/r+°, the channel switching devices The channel switching controller 8 switches the staves of the device so as to advance one by one. In this case, the channel switchers 6-]] to 6-1 are switched to select adjacent n channels from the transmitters of all m staves in accordance with the specified direction of the phasing direction signal 102, and transmit Signal power 1
0] is applied to the transmitter.

上述した内容は、送受信指向性の形成の場合を例といる
が、受信指向性形成の場合の整相についてもmステープ
の受波器から入力する条件で容易に実施できる。
The above description takes as an example the case of forming the transmitting and receiving directivity, but phasing in the case of forming the receiving directivity can also be easily carried out under the conditions of input from an m-staple receiver.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述した従来の整相回路は、整相方位に対して各チャン
ネルの整相量がρ/n°内の値に限定されるため、各整
相チャンネルを順次切り替えつつ逆整相方位を設定しな
ければならない。従って、チャンネル切替も複雑となり
、機械的もしくは電気的に切りM’えイ、いずれの場合
でも切替暢成か膨大化するという欠点かある。
In the conventional phasing circuit described above, the phasing amount of each channel is limited to a value within ρ/n° with respect to the phasing direction, so the inverse phasing direction is set while sequentially switching each phasing channel. There must be. Therefore, channel switching becomes complicated, and in either case, the number of switching operations becomes enormous.

本発明の目的は」二連しノと欠点を除去し、切イー)構
成を大幅に簡素化したソーナー整相回路を提供すること
にある。
It is an object of the present invention to provide a sonar phasing circuit which eliminates the disadvantages of double connection and greatly simplifies the configuration.

〔課題を解決するための手段〕[Means to solve the problem]

本発明の回路は、円筒配列型送受波器の相1(1接する
r〕ステーブ(s t a n1 e )の送受波器に
加わる送受信出力の位相を遅延調節してρ°の方位角範
囲に所望の送受波指向性を合成する整相を施すソーナー
整相回路において、 ρ°の方位角範囲に配列するnステーブの送受波器のそ
れぞれに施すべき整相に必要なn個の位相調節用の遅延
整相量のすべてを備えてそのいずれかを送受信入力に付
与する1〕ヂヤンネルのlo、幅遅延整相器と、整相に
よって指向すべき方位に関する情報を受りつつ前記nヂ
ャンネルのρ′幅遅延整相器のそれぞれに対し前記遅延
整相量を設定せしめるように制御する整相制御器と、前
記I〕チャンネルのp°幅遅延整相器を前記円筒配列型
送受波器の汗意の相隣接するnチャンネルの送受波器ス
テーブのそれぞれに指向すべき方位に対応して整相可能
な状態に切替接続するnチャンネルのチャンネル切替器
と、前記整相によって指向すべき方位に関する情報を受
けつつ前記l°以内の方位角範囲の整相にあっては前記
nチャンネルのρ°幅遅延塾相器を設定初期位置のρ°
幅遅延愁相器を設定初期位置のρ°の方位角範囲のnス
テーブの相隣接する送受波器と接続し前記loの方位角
範囲を超えて整相して指向方位を旋回シフトする場合に
は旋回シフト方向に対して1個ずつ歩進ぜしめた送受波
器を含むnステーブの送受波器と接続するように切り替
えを制御するヂャンネル切替制御器とを備えて構成され
る1、 〔実施例〕 次に、図面を参照して本発明の詳細な説明する。
The circuit of the present invention delay-adjusts the phase of the transmitting and receiving outputs applied to the transducer of the phase 1 (1 contact r) stave (stan1e) of the cylindrical array type transducer and adjusts the phase in the azimuth range of ρ°. In a sonar phasing circuit that performs phasing to synthesize the desired transmitting and receiving wave directivity, there are n phase adjustments necessary for phasing each of the n stave transducers arranged in the azimuth range of ρ°. 1) the lo of the channel, the width delay phasing device, and the ρ of the n channel while receiving information regarding the direction to be directed by phasing. a phasing controller that controls the delay phasing amount to be set for each of the width delay phasing devices; an n-channel channel switcher connected to each of the adjacent n-channel transducer staves so as to enable phasing in accordance with the azimuth to which the transducer staves should be oriented; and information regarding the azimuth to be oriented by said phasing. For phasing in the azimuth angle range within the above l° while receiving
When connecting the width delay phasing device to the adjacent transducer of the n staves in the azimuth range of ρ° at the initial position and phasing beyond the azimuth range of lo to rotationally shift the pointing azimuth. 1, which is configured with a channel switching controller that controls switching so as to be connected to n stave transducers including transducers that are stepped one by one in the turning shift direction. [Example 1] ] Next, the present invention will be described in detail with reference to the drawings.

第1図は本発明の一実施例の構成を示すブロック図°ζ
゛あり、送信整相の場合を例としρ°幅遅延整相−器1
−1〜1.−n 、チャンネル切替器2−1〜2−n 
、整相制御器3.チャンネル切替器4を備えてイ゛14
成される。
Figure 1 is a block diagram showing the configuration of an embodiment of the present invention.
゛, taking the case of transmission phasing as an example, ρ° width delay phasing unit 1
-1~1. -n, channel switch 2-1 to 2-n
, phasing controller 3. Equipped with a channel switcher 4 14
will be accomplished.

第1図にもとついて実施例の説明を行なうのに先立ち、
第3図によって不発明0)整相に−)いて3′A1、A
の場合を例として説明する7 Y1ステ−フ 逆波器1−nは第3図に示す設定所期位
置の方位角範囲ρ°にわたって隣接配j+’4:されて
おり、これらに付与するR延整相−h):は、I;Ii
来の−Q / +−幅の遅延整相量かnチ〜ンオ、ルの
Q。
Prior to explaining the embodiment based on FIG.
According to Fig. 3, 0) In the phasing -) 3'A1, A
The case of 7 Y1 step will be explained as an example. Extended phase-h): I; Ii
The delay phasing amount of the next -Q/+- width or the Q of n channels.

、、′I’1幅遅延整相器で提供されるようになってい
る。
, ,'I'1-width delay phaser.

本発明の場合はnヂャンネルのj?延l:雀相器の・で
れそれがρ°幅にわたー〉て整相するのに必要なn個の
遅延量をすべて提供できるものとしている。
In the case of the present invention, the j? of channel n? It is assumed that the phase shifter can provide all n delay amounts necessary for phasing over the ρ° width.

整相方位のシフトかQ / r+°を超える場合、tノ
゛c来は整相方位を中心としてチャンネル接続を一斉に
すべて切替えねばちなj−いか、不発明の場合は、第3
図において右廻つに1ステ一フ方位pノ、上をシフ1へ
させようとすると、ステーフコ送波2:;にイ・IIj
した遅延整相器はステーブr+ +]送波器に与えるよ
うにする6つよりステーブ2からステーブ■1]−1ま
でのQoかこの場合の整相角と在る。
If the shift in the phasing direction exceeds Q/r+°, all channel connections must be switched around the phasing direction at the same time, or in the case of uninventiveness, the third
In the figure, if you try to turn the clockwise direction by 1 step to shift 1, the step shift wave will be transmitted to 2:;
The delay phasing device has Qo from stave 2 to stave 1]-1, or the phasing angle in this case, from the six staves r++] to be applied to the transmitter.

この状態から再ひl / Tl °を超えてシフトしよ
うとするとステーブn + ]送波器に対する遅延整相
量従って遅延整相器との接続はそのままとし、ステ2フ
ri +l送波器にIWI接するステーブn −1−2
送波器に対しステーブ2送波器に付4 していた遅延整
相量が代って付与され、この場合はステーブ3送波器か
らステーブn−[2送波器のρ°が整相角となる。
If you try to shift beyond H / Tl ° again from this state, the amount of delay phasing for the stave n + ] transmitter. Contacting stave n -1-2
The delay phasing amount that was attached to the stave 2 transmitter is applied instead to the transmitter, and in this case, from the stave 3 transmitter to the stave n-[2 transmitter's ρ° is the phasing amount. It becomes a corner.

以後、この切替をくり返し、ステーブn送波器まて切替
えか及び、ステーブn送波器に付与していた遅延N−が
ステーブ2 nに切り替え付−リされた次に、ステーブ
n+1に付、すしていた遅延整相量はステーブ2 n 
+]送波器に切り替え提供される。
Thereafter, this switching is repeated, and the delay N- given to the stave n transmitter is switched to the stave n transmitter, and then the delay N- given to the stave n transmitter is switched to stave 2n, and then to stave n+1, The delay phasing amount that was being used is stave 2 n
+] Provided for switching to the transmitter.

いま、ρ°か120°であると仮定すると、当初ステー
ブ1送波器に1ζ1与していた遅延整相量は、ステーフ
Yl+1.ステーフ2 n + 1 、ステー71と3
回の切イ)・のみて切り+)え操作が済み、他の送波器
についても同様である。つまりヂャンネル切替はそれぞ
れのヂャンオ・ルごとに3回てよく、切替は大幅に簡素
化されることとなる。
Now, assuming that ρ° is 120°, the delay and phasing amount that was initially given to the stave 1 transmitter by 1ζ1 is the stave Yl+1. Stay 2 n + 1, Stay 71 and 3
The operations of turning off (a) and turning off (+) are completed, and the same goes for other transmitters. In other words, channel switching only needs to be performed three times for each channel, which greatly simplifies channel switching.

再び第1図に戻って実施例の説明を続行する。Returning again to FIG. 1, the description of the embodiment will be continued.

Q°幅遅延整相回路1−1・〜]−nは、0°がら−Q
 ’までの遅延整相を行うに足るシコーーテインク、フ
エージンク定数を有する整相回路である9また、整相制
御器3は、整相方位o°・〜ρ°に変換するへく次式の
変換を行なう。
Q° width delay phasing circuit 1-1.~]-n is 0° to -Q
The phasing circuit is a phasing circuit having sufficient phase delay and phasing constants to perform delayed phasing up to . Let's do it.

k=1.2.・・・、 n ここて、Xは′終用制御器3に入力する整相方位、yk
はそれぞれのl°幅遅延整相回路]−1〜1−r】に与
える変換方位である。又、関数Mo丁)(A、B)はA
をBて割った余りを求める関数であり、1(はρ°幅整
相回路1−−−1〜1−nのチャンネル数て1〜nの数
値である。
k=1.2. ..., n Here, X is the phasing direction input to the final controller 3, yk
is the conversion direction given to each l° width delay phasing circuit]-1 to 1-r. Also, the function Mo Ding) (A, B) is A
It is a function to find the remainder when divided by B, and 1( is a numerical value of 1 to n, which is the number of channels of the ρ° width phasing circuits 1--1 to 1-n.

チャンネル切替器2−1〜2−nは、各チ、〜・ンネル
ことに整相した出力を円周上のとのチャンネルに出力す
るかを選択するものであり、1−)α)人力信号を用/
mチャンネルの内のとれがl =、) 0)出力に接続
する。
The channel switchers 2-1 to 2-n select whether to output the phased output to the channel on the circumference of each channel, 1-) α) Human input signal /
Connect one of the m channels to the output.

−10−一一 チャンネル切替制御器8は、整相方位に対してI(チャ
ンネル(1−n)が1・〜1丁lのと′のチャンネルに
ならなければならないかを制御し、次式の変ここで関数
JNT(A/B)は、AをBで割った商の整数部を求め
る関数である。従って21(は1〜m/nの間の整数て
あり、各切替器に送られる。各切替器は、この信号を受
けてrn / n出力回路のZk番口の出力回路に信号
を出力する。
-10-11 The channel switching controller 8 controls whether or not I (channel (1-n) should be 1.~1 channel and ' for the phasing direction, and the following formula is used. Here, the function JNT(A/B) is a function that calculates the integer part of the quotient of A divided by B. Therefore, 21( is an integer between 1 and m/n, and is sent to each switch. Each switch receives this signal and outputs a signal to the Zk output circuit of the rn/n output circuit.

なお、上述した実施例では送信整相の場合を例として説
明しているか、受信整相の場合ても同様に実施しうるこ
とは明らかである。
It should be noted that although the above-mentioned embodiments have been explained using the case of transmission phasing as an example, it is clear that the same implementation is possible in the case of reception phasing as well.

〔発明の効果〕〔Effect of the invention〕

以上説明した様に本発明は、p°幅遅延整相回路nチA
・ンネlしのチャンネル切1をチャンネルn十1に、以
下同様にしてチャンネルDをチャンネル2 nに切り替
えて遅延整相するように制御することにより、整相チャ
ンネルを全チャンネルに対して順次切り替える必要がな
く、全周の特定チャンネルの切り替えのみでずむZ、)
、Inステーブの送受波器に刻してnl X n個必要
とするチャンネル切り替え器かrn / n X n即
ちn1個に削a&され、ハードウェア量が1./nとな
って装置の小型化か図れるとともに切替内容の大幅な簡
素化が図れるという効果かある。
As explained above, the present invention provides a p° width delay phasing circuit n-chi A
・Switch the phasing channel sequentially to all channels by controlling channel cut 1 to channel n11 and channel D to channel 2 n for delayed phasing. There is no need to do so, you can just switch specific channels all around the Z,)
, the channel switching device that requires nl x n in the transducer of the In stave is reduced to rn/n x n, that is, n1, and the amount of hardware is reduced to 1. /n, which has the effect of reducing the size of the device and greatly simplifying the switching contents.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例の構成を示すブロック図、第
2図は従来のソーナー整相回路の基本的構成を示すブロ
ック図、第37は本発明の詳細な説明図、第4図は従来
の整相の説明図である。 ]−1〜1−n・・・ρ°幅遅延整相器、2−1・〜2
−n、 5−1〜5−n・・−ρ/、n ”幅遅延整相
器、6−1〜6−n  ・チャンネルυノ替器、3,7
・・整相制御器、4.8・・・チャンネル切替器。 代理人 弁理士 内 原  n“1′
Fig. 1 is a block diagram showing the configuration of an embodiment of the present invention, Fig. 2 is a block diagram showing the basic configuration of a conventional sonar phasing circuit, Fig. 37 is a detailed explanatory diagram of the present invention, and Fig. 4 is an explanatory diagram of conventional phasing. ]-1~1-n...ρ° width delay phaser, 2-1~2
-n, 5-1~5-n...-ρ/, n'' width delay phasing device, 6-1~6-n Channel υ changer, 3,7
...Phase controller, 4.8...Channel switch. Agent Patent Attorney Uchihara n“1′

Claims (1)

【特許請求の範囲】 円筒配列型送受波器の相隣接するnステーブ(stab
e)の送受波器に加わる送受信出力の位相を遅延調節し
てl°の方位角範囲に所望の送受波指向性を合成する整
相を施すソーナー整相回路において、 l°の方位角範囲に配列するnステーブの送受波器のそ
れぞれに施すべき整相に必要なn個の位相調節用の遅延
整相量のすべてを備えてそのいずれかを送受信入力に付
与するnチャンネルのl°幅遅延整相器と、整相によっ
て指向すべき方位に関する情報を受けつつ前記nチャン
ネルのl°幅遅延整相器のそれぞれに対し前記遅延整相
量を設定せしめるように制御する整相制御器と、前記n
チャンネルのl°幅遅延整相器を前記円筒配列型送受波
器の任意の相隣接するnチャンネルの送受波器ステーブ
のそれぞれに指向すべき方位に対応して整相可能な状態
に切替接続するnチャンネルのチャンネル切替器と、前
記整相によって指向すべき方位に関する情報を受けつつ
前記l°以内の方位角範囲の整相にあっては前記nチャ
ンネルのl°幅遅延整相器を設定初期位置のl°幅遅延
整相器を設定初期位置のl°の方位角範囲のnステーブ
の相隣接する送受波器と接続し前記l°の方位角範囲を
超えて整相して指向方位を旋回シフトする場合には旋回
シフト方向に対して1個ずつ歩進せしめた送受波器を含
むnステーブの送受波器と接続するように切り替えを制
御するチャンネル切替制御器とを備えて成ることを特徴
とするソーナー整相回路。
[Claims] N staves (stabs) adjacent to each other in a cylindrical array type transducer
e) In the sonar phasing circuit that delays and adjusts the phase of the transmitting and receiving output applied to the transducer to synthesize desired transmitting and receiving wave directivity in the azimuth range of 1°, An n-channel 1° width delay that includes all of the n phase adjustment delay phasing amounts necessary for phasing each of the transducers of the n staves arranged, and applies any of them to the transmitting and receiving inputs. a phasing controller configured to control each of the n-channel 1° width delay phasing devices to set the delay phasing amount while receiving information regarding the azimuth to be directed by phasing; Said n
A channel l° width delay phasing device is switched and connected to each of the n-channel transducer staves adjacent to each other in the cylindrical array type transducer in such a manner that it can be phased in accordance with the direction to be directed. Initial setting of the n-channel channel switch and the n-channel 1° width delay phaser for phasing within the azimuth range of 1° while receiving information regarding the azimuth to be directed by the phasing. Set the l° width delay phasing device at the initial position, connect it to the adjacent transducer of the n staves in the azimuth range of l°, and set the pointing azimuth by phasing beyond the azimuth range of l°. In the case of rotational shift, the channel switching controller is provided to control switching so as to be connected to n stave transducers including transducers that are stepped one by one in the rotational shift direction. Characteristic sonar phasing circuit.
JP63080675A 1988-03-31 1988-03-31 Sonar phasing circuit Expired - Lifetime JP2696898B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63080675A JP2696898B2 (en) 1988-03-31 1988-03-31 Sonar phasing circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63080675A JP2696898B2 (en) 1988-03-31 1988-03-31 Sonar phasing circuit

Publications (2)

Publication Number Publication Date
JPH01253676A true JPH01253676A (en) 1989-10-09
JP2696898B2 JP2696898B2 (en) 1998-01-14

Family

ID=13724928

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63080675A Expired - Lifetime JP2696898B2 (en) 1988-03-31 1988-03-31 Sonar phasing circuit

Country Status (1)

Country Link
JP (1) JP2696898B2 (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS49116277A (en) * 1973-03-09 1974-11-06
JPS62259566A (en) * 1985-12-02 1987-11-11 Ikeuchi Tekkosho:Kk Apparatus for forming molded food from ground meat

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS49116277A (en) * 1973-03-09 1974-11-06
JPS62259566A (en) * 1985-12-02 1987-11-11 Ikeuchi Tekkosho:Kk Apparatus for forming molded food from ground meat

Also Published As

Publication number Publication date
JP2696898B2 (en) 1998-01-14

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