JPH01253204A - Laminate type chip thermistor - Google Patents

Laminate type chip thermistor

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Publication number
JPH01253204A
JPH01253204A JP8079088A JP8079088A JPH01253204A JP H01253204 A JPH01253204 A JP H01253204A JP 8079088 A JP8079088 A JP 8079088A JP 8079088 A JP8079088 A JP 8079088A JP H01253204 A JPH01253204 A JP H01253204A
Authority
JP
Japan
Prior art keywords
thermistor
electrodes
thermistors
laminate type
type chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8079088A
Other languages
Japanese (ja)
Inventor
Takuoki Hata
畑 拓興
Kaori Okamoto
岡本 香織
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP8079088A priority Critical patent/JPH01253204A/en
Publication of JPH01253204A publication Critical patent/JPH01253204A/en
Pending legal-status Critical Current

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  • Thermistors And Varistors (AREA)

Abstract

PURPOSE:To provide a laminate type chip thermistor capable of surface mounting without variations of characteristics by laminating unit thermistors of Mn- Ni-Cr based oxide spinel so that they are connected in series through internal electrodes, and employing external electrodes as terminal electrodes. CONSTITUTION:A unit thermistor 1 has a spinel structure which include three kinds of metal elements Mn, Ni and Cr in total 100atm%. Internal electrodes 2 are formed on such unit thermistors 1 which are then laminated. External electrodes 6 are led out such that the respective unit thermistors 1 are connected in parallel to each other. Hereby, there are structural features combined for the use and for lamination of a thermistor material possessing excellent thermistor characteristics. Thus, a laminate type chip thermistor capable of surface mounting without variations of the characteristics can be obtained.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、温度センサあるいは主に電気回路の温度補償
用として用いられている面実装用タイプの積層形チップ
サーミスタに関するものである。
DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a surface-mount type multilayer chip thermistor used as a temperature sensor or mainly for temperature compensation in an electric circuit.

従来の技術 近年、機器の軽薄短小化の技術動向に沿って、機器に組
み込まれる電子部品そのものの小型化が強く要望されて
きた。そして、積層セラミックコンデンサを始めとして
、チップ抵抗、チップコイルなどのいわゆるチップ部品
があらゆる分野で使用されるようになってきている。こ
れらのチップ部品は、面実装技術の進歩に伴い、自動挿
入機でもってテーピングされた状態から、プリント基板
へ直接挿入され、半田付けされる。そして、機器にはこ
のプリント基板を単位体として組み込まれるが、その技
術動向としては、さらに部品の小型化、高密度実装が要
望されている。
BACKGROUND OF THE INVENTION In recent years, in line with the technological trend of making devices lighter, thinner, and smaller, there has been a strong demand for miniaturization of the electronic components themselves incorporated into devices. So-called chip components such as multilayer ceramic capacitors, chip resistors, and chip coils have come to be used in all kinds of fields. With the advancement of surface mounting technology, these chip components are directly inserted into a printed circuit board from a taped state using an automatic insertion machine and soldered. This printed circuit board is then incorporated into equipment as a unit, and technological trends are demanding further miniaturization and high-density packaging of components.

このような部品の中にあって、特に温度補償用サーミス
タとしては、従来よりディスク形サーミスタが用いられ
ており、プリント基板への取付けも手作業で行われてい
るのが現状である。その上、サーミスタ特性も、従来は
コバルト、マンガン。
Among such parts, disk-shaped thermistors have traditionally been used, particularly as temperature-compensating thermistors, and are currently attached to printed circuit boards manually. Furthermore, the thermistor characteristics are conventionally cobalt and manganese.

銅およびニッケルの混合酸化物を主体としたサーミスタ
を用いているため、抵抗値のバラツキが±20%〜±1
5%と大きいものであった。また、積層セラミックコン
デンサのような積層化という考え方については、既に2
0年前に提案されている(特公昭150−11585号
公報)が、構成部材の安定性、特にサーミスタと内部電
極の反応に問題があシ、まだ現実には製品化できていな
いものである。
Since the thermistor is mainly made of a mixed oxide of copper and nickel, the variation in resistance value is between ±20% and ±1.
It was as large as 5%. Furthermore, the concept of lamination, such as multilayer ceramic capacitors, has already been
Although it was proposed 0 years ago (Japanese Patent Publication No. 150-11585), there are problems with the stability of the component parts, especially the reaction between the thermistor and the internal electrode, and it has not yet been commercialized. .

発明が解決しようとする課題 以上のように、従来のサーミスタでは、自動挿入機を使
用してプリント基板に実装することができず、機器の軽
薄短小化に対応できないという問題があった。また、特
性面においても、高精度化という要望に十分に対応でき
ないという問題があった。
Problems to be Solved by the Invention As described above, conventional thermistors have the problem that they cannot be mounted on a printed circuit board using an automatic insertion machine, and cannot respond to miniaturization of devices. Furthermore, in terms of characteristics, there was a problem in that it could not sufficiently meet the demand for higher precision.

本発明はこのような問題点を解決するもので、特性値の
バラツキが小さく、小型で面実装可能な積層形チップサ
ーミスタを提供することを目的とするものである。
The present invention is intended to solve these problems, and aims to provide a multilayer chip thermistor that has small variations in characteristic values, is small, and can be surface mounted.

課題を解決するための手段 このような課題を解決するために本発明の積層形チップ
サーミスタは、組成面および構造面から種々検討した結
果、安定なマンガン(Mn)−ニッケル(Ni)−クロ
ム(Or)系酸化物スピネルのサーミスタ単位体を内部
電極を介して並列接続になるよう積層し、外部電極を端
子電極としたものである。
Means for Solving the Problems In order to solve the above problems, the multilayer chip thermistor of the present invention was developed using a stable manganese (Mn)-nickel (Ni)-chromium ( Or) type oxide spinel thermistor units are stacked so as to be connected in parallel via internal electrodes, and the external electrodes are used as terminal electrodes.

作用 この構成により、優れたサーミスタ特性をもつサーミス
タ材料の使用と積層化という構造上の特徴を結びつける
ことによって、サーミスタの安定性の特徴を引き出すと
ともに、自動挿入機への搭載が可能な面実装用の積層形
チップサーミスタの提供ができることとなる。
This configuration combines the use of a thermistor material with excellent thermistor properties with the structural feature of lamination, thereby bringing out the stability characteristics of the thermistor, and making it suitable for surface mounting, allowing installation in automatic insertion machines. This makes it possible to provide a multilayer chip thermistor.

実施例 以下、本発明の一実施例について説明する。Example An embodiment of the present invention will be described below.

まず、市販の原料であるMnCO3、NiOおよびCr
2O5を、Mn : Ni : Or= 82.5 :
 12.5 : 5.0原子チになるように配合した。
First, commercially available raw materials MnCO3, NiO and Cr
2O5, Mn:Ni:Or=82.5:
12.5: Blend so as to have 5.0 atoms.

この配合組成物をボールミルで湿式混合し、得られたス
ラリーを乾燥後、800 ’Cで仮焼した。この仮焼物
を再びボールミルを用いて、湿式粉砕混合した。こうし
て得られたスラリーを乾燥後、所要量採って水溶性バイ
ンダーのメチルセルロースを加えて混合し、粘土状にし
た。次いで、これを真空土練機で十分に捏和し、坏土を
得た。次に、この坏土を真空押出成形機を用いて、15
0μmのシートを作成した。その後、上記シートを乾燥
後、適当な大きさに切断し、P(i電極を用いてパター
ン印刷した。次に、このシートを用いて、Pd電極が上
下両面にそれぞれ異なる一端部には達しないように設け
られた有効11!(450μm)と、その上下に設けら
れるように無効層(各150μm)を積層し、これをパ
ターンに則して、3.70 X 1.85ffの大きさ
に切断し、脱バインダー後、1250’Cの温度で焼成
した。こうして得られた焼結体の両端部に五g電極を設
け、さらにその上に電気メツキによりNi層。
This blended composition was wet mixed in a ball mill, and the resulting slurry was dried and then calcined at 800'C. This calcined product was wet-pulverized and mixed again using a ball mill. After drying the slurry thus obtained, a required amount was taken and a water-soluble binder, methylcellulose, was added and mixed to form a clay-like mixture. Next, this was sufficiently kneaded using a vacuum clay kneading machine to obtain clay. Next, this clay was molded using a vacuum extrusion molding machine for 15 minutes.
A 0 μm sheet was created. After drying, the sheet was cut into a suitable size and printed with a pattern using P(i) electrodes.Next, using this sheet, the Pd electrodes were formed on both the upper and lower surfaces, but did not reach one end where they were different. The effective layer 11! (450 μm) provided as shown in FIG. After removing the binder, it was fired at a temperature of 1250'C. 5g electrodes were provided at both ends of the sintered body thus obtained, and a Ni layer was further applied thereon by electroplating.

Sn層を設けた。このようにして得られた積層形チップ
サーミスタの外形寸法は、3.21X1.62XO56
1(t)ggで、XIムJ規格の3216タイプ(積層
セラミックコンデンサ)に相当する。
A Sn layer was provided. The outer dimensions of the multilayer chip thermistor obtained in this way are 3.21X1.62XO56
1(t)gg, which corresponds to the 3216 type (multilayer ceramic capacitor) of the XI MuJ standard.

第1図は上記実施例における積層形チップサーミスタを
示し、1はMn−Ni−Cr系酸化物スピネルのサーミ
スタ単位体、2はPd電極からなる内部電極、3はムg
x極、4はN1メツキ層、6はSnメツキ層で、6はこ
れらムg電1! 3 、 Niメツキ層4およびSnメ
ツキ層6から構成される外部電極である。
FIG. 1 shows a multilayer chip thermistor in the above embodiment, in which 1 is a thermistor unit made of Mn-Ni-Cr-based oxide spinel, 2 is an internal electrode made of a Pd electrode, and 3 is a Mug
x pole, 4 is the N1 plating layer, 6 is the Sn plating layer, and 6 is the Mg electrode 1! 3. An external electrode composed of a Ni plating layer 4 and a Sn plating layer 6.

そして、上記のようにして得られた素子の電気特性は、
R25=80にΩ±e、o% (n=1ooケ)で、サ
ーミスタ定数Bは、n=4045に+0.9係であった
。この抵抗値およびB定数は、材料特性に一致するもの
である。
The electrical characteristics of the device obtained as described above are
R25=80 and Ω±e, o% (n=1oo ke), and the thermistor constant B was +0.9 coefficient with n=4045. This resistance value and B constant match the material properties.

また、この素子を用いてテーピングし、自動挿入機を用
いてプリント基板に実装した結果、特性不良もなく、作
業性が著しくアップし、自動化が可能であることが確認
された。さらに、信頼性面でも160°C,1000時
間後の抵抗値変化率は、従来材料(Go、 Mn、 C
uおよびNi)ノ+3.6%に対し、+0.9%と変化
率が小さいものであった。
Furthermore, as a result of taping this element and mounting it on a printed circuit board using an automatic insertion machine, it was confirmed that there were no characteristic defects, workability was significantly improved, and automation was possible. Furthermore, in terms of reliability, the rate of change in resistance value after 1000 hours at 160°C is lower than that of conventional materials (Go, Mn, C
The change rate was small at +0.9% compared to +3.6% for u and Ni).

また、本発明の上記材料を用いてディスク形にした場合
、同一条件での抵抗値変化率は+1.7チであり、本発
明では積層化による効果、すなわち内部電極が外気と遮
断されているだめの効果が現れているのではないかと考
えられているが、このメカニズムについては現在解明中
である。
Furthermore, when the above material of the present invention is made into a disk shape, the rate of change in resistance value under the same conditions is +1.7 cm. In the present invention, the effect of lamination, that is, the internal electrodes are isolated from the outside air. It is thought that this may have a negative effect, but the mechanism is currently being elucidated.

ここで、上記実施例において、積層用シート作成につい
ては、ドクターブレード法のような湿式成形法でもよく
、特に限定されるものではない。
Here, in the above embodiments, the sheet for lamination may be produced by a wet molding method such as a doctor blade method, and is not particularly limited.

また、内部電極にpt電極を用いてもよく、さらには外
部電極の構造も上記実施例に限定されるものでないこと
は当然である。
Furthermore, it is natural that a PT electrode may be used as the internal electrode, and furthermore, the structure of the external electrode is not limited to the above embodiment.

また、本発明で用いるMn −Ni−Cjr系サーミス
タ材料としては、電気特性、特にB定数の点から、N1
は5.0〜35.0原子チ、Orは0.1〜10.0原
子チの範囲が好ましいことが実験により確認されている
。ここで、Crが10.0原子俤を超えると焼結性の点
でも若干の問題が発生する恐れがある。
In addition, the Mn-Ni-Cjr-based thermistor material used in the present invention has N1
It has been confirmed through experiments that the range of 5.0 to 35.0 atoms is preferable for , and the preferable range of 0.1 to 10.0 atoms for Or. Here, if Cr exceeds 10.0 atoms, some problems may occur in terms of sinterability.

発明の効果 以上のように本発明によれば、優れたサーミスタ特性を
もつサーミスタ材料の使用と積層化という構造上の特徴
を結びつけることによって、小型で高精度でさらに信頼
性にも優れるという特性上での相乗効果を発揮し、かつ
面実装化を可能にするものであるため、作業性の向上と
いう付帯効果をもたらすものである。
Effects of the Invention As described above, according to the present invention, by combining the use of a thermistor material with excellent thermistor characteristics with the structural feature of lamination, it is possible to achieve the characteristics of small size, high precision, and excellent reliability. Since it exhibits a synergistic effect and enables surface mounting, it has the additional effect of improving workability.

また、実施例では有効層1層のものについてのみ述べた
が、積層数を増すことと、内部電極のパター/を変える
ことにより、抵抗値を幅広く変更させることが可能であ
り、このだめB定数を基本とした材料の統合も図ること
が可能となり、その産業性は大なるものがある。
In addition, although only the single effective layer was described in the example, the resistance value can be varied over a wide range by increasing the number of laminated layers and changing the pattern of the internal electrodes. It is now possible to integrate materials based on , which has great industrial potential.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明による積層形チップサーミスタの一実施
例を示す一部を断面にて見た斜視図である。 1・・・・・・サーミスタ単位体、2・・・・・・内部
電極、3・・・・・・ムg電極、4・・パ・・・Niメ
ツキ層、5・・・・・・Snメツキ層、6・・・・・・
外部電極。
FIG. 1 is a partially sectional perspective view showing an embodiment of a multilayer chip thermistor according to the present invention. DESCRIPTION OF SYMBOLS 1...Thermistor unit, 2...Internal electrode, 3...Mug electrode, 4...Pa...Ni plating layer, 5...... Sn plating layer, 6...
external electrode.

Claims (1)

【特許請求の範囲】[Claims] 金属元素として、マンガン(Mn),ニッケル(Ni)
およびクロム(Cr)の3種を合計100原子%含み、
スピネル型結晶構造を持つサーミスタ単位体に内部電極
を付与して積層し、その各々が並列に接続されるよう外
部電極を取り出したことを特徴とする積層形チップサー
ミスタ。
Manganese (Mn), nickel (Ni) as metal elements
Contains a total of 100 atom% of three types of and chromium (Cr),
A multilayer chip thermistor characterized in that internal electrodes are provided and stacked on thermistor units having a spinel crystal structure, and external electrodes are taken out so that each of the thermistor units is connected in parallel.
JP8079088A 1988-03-31 1988-03-31 Laminate type chip thermistor Pending JPH01253204A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8079088A JPH01253204A (en) 1988-03-31 1988-03-31 Laminate type chip thermistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8079088A JPH01253204A (en) 1988-03-31 1988-03-31 Laminate type chip thermistor

Publications (1)

Publication Number Publication Date
JPH01253204A true JPH01253204A (en) 1989-10-09

Family

ID=13728246

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8079088A Pending JPH01253204A (en) 1988-03-31 1988-03-31 Laminate type chip thermistor

Country Status (1)

Country Link
JP (1) JPH01253204A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0798275A1 (en) * 1996-03-29 1997-10-01 Denso Corporation A method for manufacturing thermistor materials and thermistors
JP2003532284A (en) * 2000-04-25 2003-10-28 エプコス アクチエンゲゼルシャフト ELECTRICAL STRUCTURE ELEMENT, PROCESS FOR PRODUCING THE SAME AND USING THE STRUCTURE ELEMENT

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5749203A (en) * 1980-09-08 1982-03-23 Matsushita Electric Ind Co Ltd Thermistor
JPS62137804A (en) * 1985-12-12 1987-06-20 株式会社村田製作所 Laminated chip thermistor

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5749203A (en) * 1980-09-08 1982-03-23 Matsushita Electric Ind Co Ltd Thermistor
JPS62137804A (en) * 1985-12-12 1987-06-20 株式会社村田製作所 Laminated chip thermistor

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0798275A1 (en) * 1996-03-29 1997-10-01 Denso Corporation A method for manufacturing thermistor materials and thermistors
JP2003532284A (en) * 2000-04-25 2003-10-28 エプコス アクチエンゲゼルシャフト ELECTRICAL STRUCTURE ELEMENT, PROCESS FOR PRODUCING THE SAME AND USING THE STRUCTURE ELEMENT
JP2012064960A (en) * 2000-04-25 2012-03-29 Epcos Ag Electric structure element, its manufacturing method, and usage of structure element

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