JPH01248257A - Load distribution control system for input output to auxiliary storage device - Google Patents

Load distribution control system for input output to auxiliary storage device

Info

Publication number
JPH01248257A
JPH01248257A JP7481788A JP7481788A JPH01248257A JP H01248257 A JPH01248257 A JP H01248257A JP 7481788 A JP7481788 A JP 7481788A JP 7481788 A JP7481788 A JP 7481788A JP H01248257 A JPH01248257 A JP H01248257A
Authority
JP
Japan
Prior art keywords
input
auxiliary storage
output
storage device
output path
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP7481788A
Other languages
Japanese (ja)
Other versions
JP2591782B2 (en
Inventor
Akira Okamoto
明 岡本
Minoru Harada
稔 原田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
NEC Solution Innovators Ltd
Original Assignee
NEC Corp
NEC Solution Innovators Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, NEC Solution Innovators Ltd filed Critical NEC Corp
Priority to JP7481788A priority Critical patent/JP2591782B2/en
Publication of JPH01248257A publication Critical patent/JPH01248257A/en
Application granted granted Critical
Publication of JP2591782B2 publication Critical patent/JP2591782B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Abstract

PURPOSE:To efficiently execute a load distribution processing by reporting dynamically a buffer use rate in an auxiliary storage controller to a central processor at the time of determining an input/output path to a device to which a data transfer is executed asynchronously. CONSTITUTION:The title system is provided with an input means 1 for fetching an input/output path which has executed an input/output operation to an auxiliary storage from an input/output path drawback table 2, an output means 3 for executing an input/output request to the auxiliary storage 7, and a discriminating means 5 which is provided on an auxiliary storage controller 6 and executes an execution propriety check by the input/output path which has been requested by a buffer use state of the auxiliary storage controller 6 and a load state decision processing of the auxiliary storage controller 6. Also, said system is provided with an input/output path redetermining means 8 for executing a selection of an alternative path at the time when the execution has been decided to be unsuitable, and an input/output path selection result storage means 9 for storing the input/output path which has executed an input/output request to the auxiliary storage device 7, in the drawback table 2. In such a way, a high speed transfer processing of data can be executed.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、計算機システムの補助記憶装置に対する入出
力の負荷分散制御方式に関し、特に、データ高速転送処
理を行なうための緩衝バッファを有する補助記憶制御装
置を介して、補助記憶装置に対する。入出力要求を行う
経路の決定方法に関する。
Detailed Description of the Invention [Field of Industrial Application] The present invention relates to an input/output load distribution control method for an auxiliary storage device of a computer system, and particularly to an auxiliary storage device having a buffer for high-speed data transfer processing. to the auxiliary storage device via the control device. This invention relates to a method for determining a route for making an input/output request.

〔従来の技術〕[Conventional technology]

従来、補助記憶装置に対する入出力経路の決定は上位装
置である補助記憶制御装置毎に、当該補助記憶制御装置
の下位装置である複数の補助記憶装置に要求した入出力
回数を累積し、値の一番低い値を示す補助記憶制御装置
からの入出力経路を設定していた。
Conventionally, to determine the input/output path for an auxiliary storage device, for each auxiliary storage control device that is a higher-level device, the number of input/output requests to multiple auxiliary storage devices that are lower-level devices of the auxiliary storage control device is accumulated, and the value is calculated. The input/output path was set from the auxiliary storage controller that had the lowest value.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述した従来の補助記憶装置に対する入出力経路の決定
方式は、入出力動作が補助記憶制御装置と補助記憶装置
間で同期をとって行われる場合。
The conventional method for determining the input/output path for the auxiliary storage device described above is when input/output operations are performed synchronously between the auxiliary storage control device and the auxiliary storage device.

どの補助記憶制御装置を使用する経路で入出力を行うか
を決定する手段としては有効であった。しかしながら、
補助記憶制御装置が、データ高速転送処理を可能とする
為の緩衝バッファを有しており2個々のバッファが補助
記憶制御装置毎に存在している場合、入出力動作が補助
記憶制御装置と補助記憶装置間で非同期に行われる為、
どの補助記憶制御装置を使用するかを入出力に使用した
補助記憶制御装置の累積値から決定したのではデータの
高速転送処理が出来なくなる欠点がある。
This was effective as a means of determining which auxiliary storage control device should be used for input/output. however,
If the auxiliary storage controller has a buffer to enable high-speed data transfer processing, and two individual buffers exist for each auxiliary storage controller, input/output operations will be performed between the auxiliary storage controller and the auxiliary storage controller. Because it is performed asynchronously between storage devices,
If the auxiliary storage control device to be used is determined based on the cumulative value of the auxiliary storage control devices used for input/output, there is a drawback that high-speed data transfer processing cannot be performed.

本発明の課題は、上記欠点を除去し、入出力動作が補助
記憶制御装置と補助記憶装置との間で非同期に行なわれ
る場合に、データの高速転送処理が可能な、入出力装置
の負荷分散制御方式を提供することにある。
An object of the present invention is to eliminate the above-mentioned drawbacks and to distribute the load of input/output devices, which enables high-speed data transfer processing when input/output operations are performed asynchronously between the auxiliary storage control device and the auxiliary storage device. The objective is to provide a control method.

〔課題を解決するだめの手段〕[Failure to solve the problem]

本発明によれば、バッファリング機能を有する補助記憶
制御装置を介して補助記憶装置に対して。
According to the present invention, to the auxiliary storage device via the auxiliary storage control device having a buffering function.

入出力を行う際、その直前に当該補助記憶装置に対して
入出力動作を行った入出力経路を退避テーブルから取り
出す入力手段と、前記補助記憶装置に対して入出力要求
を行う出力手段と、前記補助記憶制御装置に設けられ、
要求された入出力経路での実行可否チェックを、該補助
記憶制御装置のバッファ使用状況及び該補助記憶制御装
置の負荷状態判断処理により行う判別手段と、実行不適
当と判断された時の代替経路の選択を行う入出力経路再
決定手段と、前記補助記憶装置に対して入出力要求を行
った入出力経路を前記退避テーブルに記憶する手段を具
備したことを特徴とする。補助記憶装置に対する入出力
の負荷分散制御方式が得られる。
When performing input/output, an input means for extracting from a save table an input/output route that has performed an input/output operation to the auxiliary storage device immediately before the input/output operation, and an output means for making an input/output request to the auxiliary storage device; provided in the auxiliary storage control device,
A determining means for checking whether execution is possible on a requested input/output route based on buffer usage status of the auxiliary storage control device and load state judgment processing of the auxiliary storage control device, and an alternative route when execution is determined to be inappropriate. The present invention is characterized by comprising input/output route re-determining means for making a selection, and means for storing in the save table the input/output route that has made an input/output request to the auxiliary storage device. A load distribution control method for input/output to the auxiliary storage device is obtained.

〔実施例〕〔Example〕

次に本発明の実施例について図面を参照して説明する。 Next, embodiments of the present invention will be described with reference to the drawings.

第1図を参照すると9本発明の一実施例による補助記憶
装置に対する入出力の負荷分散制御方式は、バッファリ
ング機能を有する補助記憶制御装置6を介して補助記憶
装置7に対して、入出力動作を行う際、その直前に当該
補助記憶装置7に対して入出力動作を行った入出力経路
を入出力経路退避テーブル2から取り出す入力手段1と
、前記補助記憶装置7に対して入出力要求を行う出力手
段3と、補助記憶制御装置6に設けられ、要求された入
出力経路での実行可否チェックを、該補助記憶制御装置
6のバッファ使用状況及び該補助記憶制御装置6の負荷
状態判断処理により行う判別手段5と、実行不適当と判
断された時の代替経路の選択を行う入出力経路再決定手
段8と、前記補助記憶装置7に対して入出力要求を行っ
た入出力経路を前記退避テーブル2に記憶する入出力経
路選択結果記憶手段9を具備したことを特徴とする。
Referring to FIG. 1, the input/output load distribution control method for the auxiliary storage device according to an embodiment of the present invention is to control input/output to the auxiliary storage device 7 via the auxiliary storage control device 6 having a buffering function. When performing an operation, an input means 1 retrieves from the input/output route saving table 2 an input/output route that has performed an input/output operation to the auxiliary storage device 7 immediately before, and makes an input/output request to the auxiliary storage device 7. The output means 3 is provided in the auxiliary storage control device 6, and the output means 3 is provided in the auxiliary storage control device 6 to check whether or not the requested input/output route can be executed, and to determine the buffer usage status of the auxiliary storage control device 6 and the load state of the auxiliary storage control device 6. an input/output route re-determining unit 8 that selects an alternative route when execution is determined to be inappropriate; It is characterized by comprising an input/output route selection result storage means 9 which is stored in the save table 2.

入力手段1.出力手段3.入出力経路再決定手段8.及
び入出力経路選択結果記憶手段9は、中央処理装置10
に設けられている。入出力経路退避テーブル2は主記憶
装置11に設けられている。
Input means 1. Output means 3. Input/output route re-determination means 8. and input/output route selection result storage means 9, central processing unit 10
It is set in. The input/output route saving table 2 is provided in the main storage device 11.

なお、第1図において、4はバッファ制御手段である。In addition, in FIG. 1, 4 is a buffer control means.

第2図を参照すると、補助記憶制御装置6(第1図)は
、一対の補助記憶制御装置12及び13からなる。補助
記憶制御装置12は、入出力動作を高速化する為のバッ
ファリング機能を可能とするためのバッファ12aを有
し、補助記憶装置7に対して読み取り、書き込みを制御
する。補助記憶制御装置13は、同様に、バッファ13
aを有し、補助記憶装置7に対して読み取り、書き込み
を制御する。
Referring to FIG. 2, the auxiliary storage control device 6 (FIG. 1) consists of a pair of auxiliary storage control devices 12 and 13. The auxiliary storage control device 12 has a buffer 12a to enable a buffering function to speed up input/output operations, and controls reading and writing to the auxiliary storage device 7. The auxiliary storage control device 13 similarly controls the buffer 13
a, and controls reading and writing to the auxiliary storage device 7.

第3図は、バッファリング機能を有する補助記憶制御装
置12.13下の補助記憶装置7に対する入出力経路を
決定する処理の一例を示す流れ図である。次に第3図に
より本実施例の動作を説明する。
FIG. 3 is a flowchart showing an example of a process for determining an input/output path to the auxiliary storage device 7 under the auxiliary storage control device 12, 13 having a buffering function. Next, the operation of this embodiment will be explained with reference to FIG.

補助記憶装置7に対する入出力経路を決定する時、直前
に同一装置に対して入出力動作が行われた経路を主記憶
装置11から取り込む(Sl)。
When determining the input/output path to the auxiliary storage device 7, the path on which the input/output operation was performed to the same device immediately before is fetched from the main storage device 11 (Sl).

取り込まれた経路より、補助記憶装置7に入出力要求を
行う(S2)。補助記憶装置7に対して出された入出力
要求は、補助記憶制御装置12を介して補助記憶装置7
に出される。
An input/output request is made to the auxiliary storage device 7 using the fetched route (S2). An input/output request issued to the auxiliary storage device 7 is sent to the auxiliary storage device 7 via the auxiliary storage control device 12.
Served on.

補助記憶制御装置12では、入出力要求された補助記憶
装置7に対する・ぐソファ12a内に、補助記憶装置7
への未書き込み分として残されている有効データが有る
か、または既に/?ツファ12aに先読み込みされた有
効データが有るか否かのチェックを行う(S3)。バッ
ファ12a内に有効データがある場合、補助記憶制御装
置12は、要求された入出力経路に従って補助記憶装置
7へ入出力動作を実行させる(SIO)。入出力の実行
は。
The auxiliary storage control device 12 stores the auxiliary storage device 7 in the sofa 12a for the auxiliary storage device 7 for which input/output is requested.
Is there valid data remaining as unwritten data, or is there already /? A check is made to see if there is valid data that has been preloaded into the buffer 12a (S3). If there is valid data in the buffer 12a, the auxiliary storage control device 12 causes the auxiliary storage device 7 to perform an input/output operation according to the requested input/output path (SIO). Execution of input/output.

主記憶装置11内のバッファ領域111Lと補助記憶制
御装置12内の/Jツファ12aとの間でのデータ転送
により完結させる。
The process is completed by data transfer between the buffer area 111L in the main storage device 11 and the /J buffer 12a in the auxiliary storage control device 12.

補助記憶制御装置12のバッファ12a内に有効データ
が存在しなかった時、補助記憶装置7の上位装置である
他の補助記憶制御装置13のバッファ13a内に補助記
憶装置7に対する有効データが存在するか否かのチェッ
クを行う(S4)。
When valid data does not exist in the buffer 12a of the auxiliary storage control device 12, valid data for the auxiliary storage device 7 exists in the buffer 13a of another auxiliary storage control device 13, which is a host device of the auxiliary storage device 7. A check is made as to whether or not (S4).

他の補助記憶制御装置13のバッファ13a内に補助記
憶装置7に対する有効データが存在する時。
When valid data for the auxiliary storage device 7 exists in the buffer 13a of another auxiliary storage control device 13.

代替入出力経路を設定するように中央処理装置10に対
し要求する(S6)。
A request is made to the central processing unit 10 to set an alternative input/output route (S6).

補助記憶装置7に関する有効データが、上位装置である
全ての補助記憶制御装置12及び13内のバッファに存
在しなかった時、補助記憶制御装置12は、他の配下の
補助記憶装置によるバッファの使用率を考慮し、自らが
高負荷状態にあるか否かを判断する(S5)。
When valid data regarding the auxiliary storage device 7 does not exist in the buffers in all the auxiliary storage control devices 12 and 13, which are higher-level devices, the auxiliary storage control device 12 prevents the use of the buffer by other subordinate auxiliary storage devices. It is determined whether or not it is in a high load state by considering the rate (S5).

自らが高負荷状態にあると判断した時2代替入出力経路
を設定するように中央処理装置10に対し要求する(S
6)。
When the central processing unit 10 determines that it is in a high load state, it requests the central processing unit 10 to set two alternative input/output paths (S
6).

自らが高負荷状態ではないと判断したとき、補助記憶制
御装置12は要求された入出力経路により補助記憶装置
7に対し、入出力動作の実行要求を行う(S13)。
When determining that it is not in a high load state, the auxiliary storage control device 12 requests the auxiliary storage device 7 to perform an input/output operation via the requested input/output path (S13).

代替入出力経路の設定要求に対して、補助記憶装置7に
至る全ての経路をチェックし2代替経路があるか否かの
判断を行う(S7)。
In response to the request for setting an alternative input/output route, all routes leading to the auxiliary storage device 7 are checked to determine whether there are two alternative routes (S7).

補助記憶装置7に至る補助記憶制御装置13が存在する
時、入出力経路の再設定を行い、再実行を試みる(S2
へ戻る)。
When the auxiliary storage control device 13 that reaches the auxiliary storage device 7 exists, the input/output path is reset and re-execution is attempted (S2
).

代替入出力経路の設定要求に対して、補助記憶装置7に
至る全ての経路をチェックし2代替経路がない時2強制
的に補助記憶装置7に対して入出力要求を行う(S9)
In response to a request to set an alternative input/output route, all routes leading to the auxiliary storage device 7 are checked, and when there is no alternative route, an input/output request is forcibly made to the auxiliary storage device 7 (S9).
.

なお2強制モード下では補助記憶制御装置12は負荷状
態のチェックを行わず、補助記憶装置7に対して入出力
動作を実行させる(SIO)。
Note that under the 2 forced mode, the auxiliary storage control device 12 does not check the load state and causes the auxiliary storage device 7 to perform input/output operations (SIO).

補助記憶装置7に対する入出力動作要求時、設定された
経路を主記憶装置11に記憶しておく。
When an input/output operation request is made to the auxiliary storage device 7, the set route is stored in the main storage device 11.

この記憶された経路は2次の補助記憶装置7に対する入
出力動作を行う際の経路として使用する。
This stored path is used as a path when performing input/output operations to the secondary auxiliary storage device 7.

当処理により、従来の中央処理装置から監視が出来ない
補助記憶制御装置内のバッファ使用率(補助記憶制御装
置の負荷状態)を動的に中央処理装置に報告される事に
より、効率の良い負荷分散処理が可能である。
This process dynamically reports to the central processing unit the buffer usage rate (the load status of the auxiliary storage control unit) in the auxiliary storage control unit, which cannot be monitored from the conventional central processing unit, thereby improving load efficiency. Distributed processing is possible.

〔発明の効果〕〔Effect of the invention〕

以上説明したように2本発明は、・ぐソファリング機能
を有する補助記憶制御装置のように、中央処理装置との
間でデータ転送が非同期に行われる装置に対する。入出
力経路決定の際に、補助記憶制御装置内のバッファ使用
率(補助記憶制御装置の負荷状態)を動的に中央処理装
置に報告される事により、効率の良い負荷分散処理が可
能となる。
As explained above, the present invention is directed to an apparatus in which data transfer is performed asynchronously with a central processing unit, such as an auxiliary storage control apparatus having a auxiliary storage function. When determining input/output routes, the buffer usage rate in the auxiliary storage control unit (load status of the auxiliary storage control unit) is dynamically reported to the central processing unit, enabling efficient load distribution processing. .

また、直前の入出力経路を主記憶装置上に記憶し、当経
路を再使用することによりバッファの連続使用が可能と
なり、効率の良いバッファ使用が実現できる。
Furthermore, by storing the immediately preceding input/output path on the main memory and reusing this path, the buffer can be used continuously, and efficient buffer use can be achieved.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明一実施例の機能を説明するだめの図、第
2図は本発明の実施例のブロック図、第3図は上記実施
例による処理の流れ図である。 図において。 1・・・入出力経路を退避テーブルから得る入力手段、
2・・・入出力経路の退避テーブル、3・・・補助記憶
制御装置に対する入出力動作を要求する出力手段、4・
・・補助記憶制御装置のバッファ制御手段(中央処理装
置とは非同期に補助記憶装置とデータノ転送ヲ行う)、
5・・・バッファの使用状況等のチェックを行う判別手
段、6・・・補助記憶制御装置。 7・・・補助記憶装置、8・・・入出力経路再決定手段
。 9・・・入出力経路選択結果記憶手段、10・・・中央
処理装置、11・・・主記憶装置、11a・・・主記憶
装置内の入出力用バッファ領域、12・・・補助記憶制
御装置、12a・・・補助記憶制御装置12内の緩衝バ
ッファ、13・・・補助記憶制御装置、13a・・・補
助記憶制御装置13内の緩衝バッファ。
FIG. 1 is a diagram for explaining the functions of one embodiment of the present invention, FIG. 2 is a block diagram of the embodiment of the present invention, and FIG. 3 is a flowchart of processing according to the above embodiment. In fig. 1... Input means for obtaining input/output routes from the evacuation table;
2. A save table for input/output paths, 3. An output means for requesting an input/output operation to the auxiliary storage control device, 4.
・Buffer control means of the auxiliary storage control device (transfers data to and from the auxiliary storage device asynchronously with the central processing unit),
5... Discrimination means for checking the usage status of the buffer, etc. 6... Auxiliary storage control device. 7... Auxiliary storage device, 8... Input/output route re-determining means. 9... Input/output route selection result storage means, 10... Central processing unit, 11... Main storage device, 11a... Input/output buffer area in main storage device, 12... Auxiliary storage control Device, 12a...Buffer buffer in auxiliary storage control device 12, 13...Auxiliary storage control device, 13a...Buffer buffer in auxiliary storage control device 13.

Claims (1)

【特許請求の範囲】[Claims] 1、バッファリング機能を有する補助記憶制御装置を介
して補助記憶装置に対して、入出力動作を行う際、その
直前に当該補助記憶装置に対して入出力動作を行った入
出力経路を退避テーブルから取り出す入力手段と、前記
補助記憶装置に対して入出力要求を行う出力手段と、前
記補助記憶制御装置に設けられ、要求された入出力経路
での実行可否チェックを、該補助記憶制御装置のバッフ
ァ使用状況及び該補助記憶制御装置の負荷状態判断処理
により行う判別手段と、実行不適当と判断された時の代
替経路の選択を行う入出力経路再決定手段と、前記補助
記憶装置に対して入出力要求を行った入出力経路を前記
退避テーブルに記憶する手段を具備したことを特徴とす
る、補助記憶装置に対する入出力の負荷分散制御方式。
1. When performing an input/output operation to an auxiliary storage device via an auxiliary storage control device with a buffering function, a save table stores the input/output path that was used for the input/output operation to the auxiliary storage device immediately before. an input means for making an input/output request to the auxiliary storage device; and an output means for making an input/output request to the auxiliary storage device; A determination means for determining the buffer usage status and the load state of the auxiliary storage control device; an input/output route re-determination means for selecting an alternative route when execution is determined to be inappropriate; and for the auxiliary storage device. 1. A load distribution control method for input/output to an auxiliary storage device, comprising means for storing an input/output route that has made an input/output request in the save table.
JP7481788A 1988-03-30 1988-03-30 I / O load distribution control method for auxiliary storage Expired - Fee Related JP2591782B2 (en)

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JP7481788A JP2591782B2 (en) 1988-03-30 1988-03-30 I / O load distribution control method for auxiliary storage

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Application Number Priority Date Filing Date Title
JP7481788A JP2591782B2 (en) 1988-03-30 1988-03-30 I / O load distribution control method for auxiliary storage

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JPH01248257A true JPH01248257A (en) 1989-10-03
JP2591782B2 JP2591782B2 (en) 1997-03-19

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7617330B2 (en) 2001-04-26 2009-11-10 The Boeing Company System and method for preloading a bus controller with command schedule

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7617330B2 (en) 2001-04-26 2009-11-10 The Boeing Company System and method for preloading a bus controller with command schedule

Also Published As

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JP2591782B2 (en) 1997-03-19

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