JPH01243683A - Method and device for mixing address code - Google Patents

Abstract

PURPOSE:To prevent unauthorized duplication by mixing an address code peculiarly assigned to a terminal equipment in a part other than a video signal in a television signal. CONSTITUTION:The video signal received by a TV tuner 1 is subject to the control of a descramble control circuit 4, and the video signal and a sound signal released from scramble are outputted respectively from a video signal descrambler 2 and a sound signal descrambler 3. Then, information related to the respective bits of the address code peculiar to the terminal stored in a ROM 16 is inserted in the part, other than the video signal, of a proper horizontal scanning period within one field of a composite video signal including a sync signal outputted from the video signal descrambler 2, for instance, in the phase of color burst. Accordingly, the detection and the separation of the address code comes difficult, and when unauthorized looking and listening is performed, its origin can be quickly found out. Thus, the unauthorized duplication can be prevented.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method and a device for mixing address needs in a receiving device, and particularly for preventing unauthorized copying by a receiving and reproducing device for a terminal for paid information such as paid broadcasting. The present invention relates to an address code mixing method and a mixing device that contribute to preventing address code mixing.

[Prior Art J] Currently, information provision services using paid communication systems are being provided, such as paid broadcasting by satellite broadcasting, CATV, etc., and provision of paid information using other personal computer communications. In these communication systems, only members who have paid a predetermined fee are provided with a terminal receiving device unique to the communication system that allows information to be provided, so that information is not available to anyone other than the member. ing.

However, in the above case, the information obtained by a legitimate member may actually be provided to a third party by the member using a playback device, and it is important not to allow such unauthorized use to occur. It is clear that this will result in a major economic loss for pay-TV operators.

Therefore, in the past, measures such as inserting a copy prohibition code into the information data or including a screen displaying the unique address number assigned to the terminal in the video signal were taken to prevent the copying of paid information. I was trying to prevent it.

[Problem to be solved by the invention 1 However, the above-mentioned conventional means for preventing copying,
- Technically easy to remove into the shell. That is, by using an easily available device such as an oscilloscope, it is possible to relatively easily remove the screen containing the copy prohibition code signal and the address number of the terminal.

An object of the present invention is to mix an address code uniquely assigned to a terminal device into a portion of a television signal other than a video signal, and to make this address code inseparable and difficult to detect, thereby preventing unauthorized viewing. To provide an address code mixing method and a mixing device that can quickly and easily discover a terminal device on which illegal copying has been performed, thereby preventing illegal copying.

[Means for Solving the Problems 1] The address code mixing method according to the present invention changes a part of the television signal other than the video signal, and makes each bit of the address code correspond to the change. .

The address code mixing device according to the present invention selects a plurality of fields into which each bit of an address code is inserted using a field counter/control means while synchronizing with a vertical synchronization signal and a horizontal synchronization signal of a television signal. , further comprising an address code generating means for outputting each bit of the address code from the address ROM in synchronization with the field, and further comprising an address code generating means for outputting each bit of the address code from the address ROM in synchronization with the field; The scanning period is determined pseudo-randomly, and the address code mixing means changes part of the portion other than the video signal in the horizontal scanning period to insert the respective bit information.

[Example] Embodiments of the present invention will be described below based on the accompanying drawings.

FIG. 1 shows a terminal receiving device including an address code mixing device according to the present invention, and this terminal receiving device is a receiving device for a terminal device that receives a pay broadcast signal.

As shown in Figure 1, 1 is VHFlUHF or SHF (7
) A TV tuner that receives, amplifies, and detects a television signal; 2 is a video signal descrambler; 3 is an audio signal descrambler; 4 is a television signal that is received from pay broadcasting, and is a video signal and an audio signal. When the signal is scrambled and transmitted, the information for descrambling is extracted from the broadcast signal, and this information is used to control the operations of the video signal descrambler 2 and the audio signal descrambler 3. This is a scramble control circuit.

An audio signal is output from the audio signal descrambler 3.

Further, the video signal descrambler 2 is housed in a circuit 5 indicated by a broken line. This circuit 5 is a video processing circuit integrally formed including an address mixing circuit according to the present invention. 6 is a video signal buffer amplifier, and the video signal is taken out to this output terminal.

In the video processing circuit 5, a normal television signal is output from the video signal descrambler 2, and this signal is processed by an FSC reproducing circuit 7 for extracting a color subcarrier (hereinafter referred to as FSC), and horizontal and vertical synchronization from the television signal. The signal is supplied to a synchronization signal separation circuit 8 that separates the signals. In the fsc reproducing circuit 7, the phase and frequency are generally matched to the transmission signal by AFPC. fs output from fsc regeneration circuit 7
c is given to a phase delay circuit 9 and a phase advance circuit 10. The phase delay circuit 9 has the function of delaying fsc by 90 degrees, and the phase advance circuit 10 has the function of advancing fsc by 90 degrees. Further, the horizontal synchronization signal (hereinafter referred to as H pulse) output from the synchronization signal separation circuit 8 is generated by the fsc regeneration circuit 7, the phase shift gate pulse generation circuit 11, and the PN code (psudo noise c).
ode) generation circuit 12, and a vertical synchronization signal (hereinafter referred to as a pulse) is supplied to a field counter/control circuit 13 and an address signal generation circuit 14. The PN code generation circuit 12 is a circuit for pseudo-randomly determining the horizontal scanning period in which each bit of the address code is mixed in each field, and includes a shift register that generates a 2B-1 m-sequence PN code, and can have an arbitrary initial value. After setting, clock the shift register once per field with ■ pulse, and
A number between .about.255 is generated pseudo-randomly, and then H pulses are counted from, for example, ILH-th of the vertical retrace interval VBI. The detailed configuration of the PN code generation circuit 12 will be described later. The gate pulse Φ3 (see FIG. 3) outputted from the phase shift gate pulse generation circuit 11 and the PN code Φ! outputted from the PN code generation circuit 12. (see FIG. 3) is input to the two-man NAND gate 15, where the AND of Φ3 and Φwork is calculated. On the other hand, the field counter
The control circuit 13 outputs a V pulse for, for example, 66 fields, supplies this V pulse to the PN code generation circuit 12 and the address signal generation circuit 14, and stops outputting the V pulse for the next 100 fields. works. This operation is repeatedly performed in the field counter/control circuit 13. Circuits that perform such operations include counters,
Since it can be easily made by combining gates and flip-flops, a detailed explanation of the configuration will be omitted. The address signal generation circuit 14 is a circuit that generates an address signal for outputting the contents of the ROM 16 that stores an address code.
Specify up to 5.

After output is made from address "65", it returns to address rOJ again. The ROM 16 stores, for example, a 64-bit unique address code assigned to the terminal device,
Addresses are sequentially designated and stored in each bit of the address code. Therefore, from the address signal generation circuit 14, V
When addresses are sequentially output in synchronization with the pulses, each bit of the address code is output from the output end of the ROM 16 in correspondence with the address. In addition, the addresses "0" and "
1 is written as a start bit and a stop bit in addresses ``65'' and 64-bit terminal address code is written in addresses ``1'' to ``64'', respectively.

In the video processing circuit 5, there are also four analog AND gates (17, 18, 19, 20, 2 analog OR gates) 21, 22. and 2 NOT circuits 23, 24, each for aligning the DC levels. Two buffer amplifiers 25 and 26 including clamps are included. The output of the phase delay circuit 9 is connected to one input terminal of the AND gate 17.
The outputs of the phase advancing circuits 10 are input to one input terminal of the gate 18, and the address code output from the ROM 16 is input to the other input terminal of the AND gate 17.1B. However, the address code signal input to the AND gate 17 is inverted by the NOT circuit 23. Also, one input terminal of the AND gate 19 has an AND
Game) OR to take the logical sum for Riki Ryokawa in 17.18
The output of the gate 21 is input through a buffer amplifier 25, and one input terminal of the AND gate 20 receives the video signal output from the video signal descrambler 2, and a buffer amplifier fixes the pedestal level of the video signal to a constant DC level. 26, AND gates 19 and 20
The output of the NAND gate 15 is input to the other input terminal. However, the NA input to the AND gate 19
The output signal of the ND gate 15 is inverted by the NOT circuit 24. After that, the output of AND game) 19.20 is O
The R gate 22 performs a logical sum, and the buffer amplifier 6
supplied to

Next, the configuration of the PN code generating circuit 12 will be explained in detail with reference to FIG. In FIG. 2, 101 is an m-series P consisting of an 8-bit shift register and an EX-OR gate.
N code generator; 102 is an H pulseless counter that counts the 11th H pulse as 1; 103 is a counter control circuit that uses V pulses to start the operation of the H pulse counter 101 from IIH; 104 is a first comparison When the m-sequence PN code generator 103 indicates rxJ and the output of the H pulse counter 102 reaches rxJ, the output becomes high level. The outputs of the m-sequence PN code generator 103 and the H pulse counter 102 are both 8 bits. Reference numeral 105 denotes an OR gate, which normally only transmits the V pulse to the m-sequence PN code generator 101. When the output of the PN code generator 101 becomes 262-10 = 252, the output of the comparator 104 becomes high level during the vertical blanking interval (VBI), so there is no color burst, and φ□, φ2 as described below
Since data cannot be loaded in the form of
06 and the memory 107, and if the output is 262 or more, a shift pulse is generated in the shift pulse generation circuit 108, and the PN code generator 101 is shifted by the output of the shift pulse generation circuit 108 via the OR gate 105.

The output of the PN code generator 101 changes, resulting in 251
If it is not below, the shift pulse is outputted from the shift pulse generation circuit 108 again. Therefore, comparator 104
The output Φ of is at a high level in the IH width that includes the period of one cycle during the color burst from IIH to 261H.

Next, the operation of the receiving device having the above configuration will be explained. In this explanation of the operation, reference will be made to FIG. 1 and FIGS. 3 to 5. Figure 3 shows color burst (fsc) Φ0
FIG. 4 is a waveform diagram showing an example in which the phase of one cycle of is changed according to the bit of the address code. FIG. 5 is a waveform diagram showing various insertion methods, and shows a television signal divided into fields, and also shows an example of the insertion position of the address code in each field.

A composite video and audio signal (television signal) received by the W tuner 1 is supplied to a video signal descrambler 2, an audio signal descrambler 3, and a descrambling control circuit 4. Under the control of the descrambling control circuit 4, the video signal descrambler 2 and audio signal descrambler 3 output descrambled video and audio signals, respectively. The signal output from the video signal descrambler 2 is a composite video signal including a synchronization signal, and is then converted into a part other than the video signal in an appropriate horizontal scanning period within one field of this composite video signal, for example, in the phase of a color burst. Information related to each bit of the Natres code unique to this terminal stored in the ROM 16 will be inserted.

The fsc reproducing circuit 7 extracts fscΦ0 from the composite video signal, and on the one hand, this fscΦ0 is shifted in phase by 190 degrees in the phase delay circuit 9 and supplied to the AND gate 17, and on the other hand, the phase is shifted by +90 degrees in the phase advance circuit 10. is supplied to the AND gate 18. Further, the synchronization signal separation circuit 8 extracts the H pulse and the V pulse from the composite video signal, and the phase shift gate pulse generation circuit 11 outputs the gate pulse Φ3 as shown in FIG. 3 in synchronization with the H pulse.
255 is supplied to one input of the AND gate 15, and the PN code generating circuit 12 has a 255 bit, in which each bit is synchronized with the H pulse.
A PN code φ8 consisting of a bit string of bits is output, and NA
It is supplied to the other input of the ND gate 15. The NAND gate 15 takes the logical product of Φ3 and φ8 and outputs M■Age-19,
Give 20. The field counter/control circuit 13 is V
Inputting a pulse, counting fields, outputting a V pulse for 66 fields, and then stopping outputting the V pulse for <100 fields is repeated. The address signal generation circuit 14 inputs the V pulse from the synchronization signal separation circuit 8 and synchronizes the generation of its output with this, and also generates an address corresponding to the 66 V pulses output from the field counter/control circuit 13. Address signals from "0" to "65" are sequentially supplied to the ROM 16. ROM 16
C. In synchronization with the 66 v pulses, each bit of the 64-bit address code corresponding to addresses "0" to "65" and the two bits before and after it are output. Further, the 66 V pulses outputted by the field counter/control circuit 13 are also given to the PN code generation circuit 12, and the PN code generation circuit 12 generates the aforementioned P pulses corresponding to the predetermined 66 fields.
Generate N codes.

When 66-bit data is output from the ROM 16 in synchronization with the predetermined 66 fields by the actions of each circuit as described above, the contents of each data, i.e. A phase-advanced fsc or a phase-lag fsc is selected corresponding to “1” or “0”, level-adjusted by the buffer amplifier 25, and input to the AND gate 19. Further, a normal composite video signal whose level has been adjusted by a buffer amplifier 26 is input to the AND gate 20 . Since the output of the NAND gate 15 is normally in the "1" state, the composite video signal passes through the AND gate 20, passes through the OR gate 22, and is supplied to the buffer amplifier 6. and,
When the gate pulse Φ3 and "1" in the PN code Φ are generated simultaneously, the output of the AND gate 15 becomes rOJ from t0 determined by Φ3, and as a result, the AND gate 19
．． 20 and NOTOR gate 21, the composite video signal output to the output of OR gate 22 contains one cycle of color burst of 66 consecutive fields (
(determined by the gate pulse Φ3) includes a phase signal corresponding to the data read out from the ROM 16. That is, as shown in Figures 1, 3, and 4A, the normal fs
cΦ. On the other hand, when the data read from the ROM 16 is "0", a slow phase fscΦ0 occurs, and when it is [1], a fast phase fscΦ2 occurs in the horizontal scanning period X of each predetermined field. In this way, the start bit, address code, and stop bit sequentially read out from the ROM 16 are mixed into the color burst portion of one horizontal scanning period of 66 consecutive fields as shown in FIG. However, the horizontal scanning period X during which data is mixed in each field differs from field to field, and this is PN
It is determined pseudo-randomly with code φ8.

Next, another embodiment of the address code mixing device according to the present invention will be described with reference to FIG. In this embodiment, the address code is mixed in by deleting the synchronizing signal as shown in FIG. 4B. In FIG. 6, the same elements as those shown in FIG. 1 are designated by the same reference numerals, and their explanations will be omitted.

30 is a synchronization signal deletion gate pulse generation circuit, as shown in Fig. 7B.
A gate pulse of Φ3B shown in is generated. Φ3B and Φ8
The logical product of is output from the NAND gate 15. NA
In this case, the ND gate 15 is a three-man powered NAND gate.
Only when the output of ROM16 is "1", a negative pulse (7th
φ3B in FIG. B is output, the analog AND gate 20 is cut off, the output of the NOT circuit 24 becomes high level, and the analog AND gate 19 becomes conductive. 31, the DC level of its output is the buffer amplifier 26
This is a DC level matching circuit that becomes equal to the pedestal level of the output of the ROM 16, so there is no problem even if the output of the ROM 16 is not added. Even if one synchronization signal is missing in one field, it does not affect the TV screen, and address code detection is easy because it is sufficient to monitor the state of the synchronization separation output. If synchronization signal loss corresponds to "1" and synchronization signal presence corresponds to "0", one survey period signal is always missing somewhere in each field of start bit and stop bit, so the horizontal synchronization signal in between It is easy to see that the presence or absence of the terminal corresponds to the address code of the terminal.

If the color burst is missing, check the address code data “1”.
In this case, the synchronizing signal deletion gate pulse generation circuit 30 in Figure 6 is changed to a color burst deletion gate pulse generation circuit, and φ3B is replaced by φ3B in Figure 7C.
You can set it to 3o. In addition, when narrowing the width of the synchronization signal to mix an address code, change the synchronization signal deletion gate pulse generation circuit 30 in Figure 6 to a synchronization signal width change gate pulse generation circuit, and replace Φ3B with Φ3D in Figure 7. Just do it. Furthermore, by changing the pedestal level only when the output of the ROM 16 is 1, it is possible to make the presence or absence of a change in the pedestal level correspond to the address code. In this case, if the AND gate 20 in Figure 6 is omitted, Φ3 in Figure 7
The DC level of the part o, that is, a part of the pedestal level changes.

Note that B, C, and D in Figure 7 are B, C, and D in Figure 4.
It corresponds to

As mentioned above, according to the present invention, an address code can be mixed into a television signal. By putting the video processing circuit 5 shown in FIG. 1 into one chip or physically into one package, when the scrambled composite video signal is descrambled and output, the address code will always be the same as the composite video signal. The address code is mixed into the signal, and when the video signal is viewed on a normal television receiver, the address code is not noticed. In particular, Figure 4A
In the case of , it is a phase change of the color burst, which cannot be detected without using a special detector (phase detector), and it is extremely difficult to remove the address code from the output signal of the video processing circuit 5 and record it on the VTR. It is.

[Effect of the Invention 1] As is clear from the above explanation, according to the present invention, an address code uniquely assigned to a terminal is mixed into a part of the television signal other than the video signal. It becomes difficult to detect and separate the information, and when unauthorized viewing occurs, the source can be quickly discovered, thereby making it possible to prevent unauthorized copying and unauthorized viewing. In particular, since the location where the address code is mixed is a special location other than the video signal of the television signal, it is more difficult to detect and separate it, and the effectiveness of preventing unauthorized copying is high. Further, according to the address code mixing device of the present invention, the horizontal scanning period in which each bit of the address code in the field is inserted is pseudo-randomly changed using a PN code generation circuit, so that the difficulty in detecting the bit is changed in a pseudo-random manner. become higher.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing a first embodiment of the address code mixing device according to the present invention, Fig. 2 is a basic circuit diagram of a PN code generation circuit, and Fig. 3 is a block diagram showing a first embodiment of an address code mixing device according to the present invention. 4 is a waveform diagram showing a color burst, FIG. 4 is a partial waveform diagram of a television signal to explain various methods of inserting address code information, FIG. 5 is an explanatory diagram showing a television signal divided into fields, FIG. 6 is a block diagram showing another embodiment of the address code mixing device according to the present invention, and FIG. 7 is a waveform diagram showing various address code insertion methods. [Description of symbols] 1...TV tuner 2...Video signal descrambler 7...FSC reproducing circuit 8...Synchronizing signal separation circuit 9...Lagging phase circuit 10...Advancing phase circuit 11... ...Transfer gate pulse generation circuit 12...PN code generation circuit 13...Field counter/control circuit 14...Address signal generation circuit 16...ROM

Claims (6)

[Claims] (1) An address code mixing method in which a part of the television signal other than the video signal is changed and each bit of the address code is made to correspond to the change. (2) The address code mixing method according to claim (1), wherein the phase of a part of the burst signal of the television signal is changed. (3) The address code mixing method according to claim (1), wherein the width of the horizontal synchronizing signal of the television signal is varied. (4) The address code mixing method according to claim (1), wherein the amplitude of the horizontal synchronizing signal of the television signal is changed. (5) The address code mixing method according to claim (1), wherein the pedestal level of the television signal is changed. (6) A terminal receiving device that outputs a television signal, comprising: storage means for storing an address code assigned to the terminal receiving device; and synchronization signal separation means for extracting a vertical synchronization signal and a horizontal synchronization signal from the television signal. , field counter/control means for counting the vertical synchronization signals and generating the predetermined number of pulses corresponding to each of the predetermined number of vertical synchronization signals; accessing the storage means based on each of the pulses; address code generating means that generates each bit in synchronization with the vertical synchronization signal of the television signal; a PN code generation means that generates a PN code in synchronization with the vertical synchronization signal based on each of the pulses; For each of a predetermined number of fields specified by a number of pulses, the P
An address code mixing device which changes a part other than a video signal in a horizontal scanning period designated by an N code and inserts the content of each bit of the address code.