JPH01243291A - Memory circuit - Google Patents

Abstract

PURPOSE:To detect the partial disconnection of a bit line by connecting between neighboring bit lines by a MOS transistor in a memory array including a memory cell. CONSTITUTION:In case of evaluating the bit lines the inverse of BL1 and BL2, information is inputted setting BL0, the inverse of BL1, the inverse of BL2, BL3, and the inverse of BLN at VCC and the inverse of BL0, BL1, BL2, the inverse of BL3, and BLN at VSS. A test signal TBL is inputted as the VCC. When the partial disconnection is generated in the center of the inverse of the bit line BL1, a sense amplifier SA near to the center of the inverse of BL1 is set at VCC, however, a right part of the center is set at the VSS by a FETM2 and a sense amplifier SA2. It is possible to decide a defect by operating a word line WL at the part since the defect is generated at the part. Since the continuity resistance of the FETM2 is set sufficiently larger than the operating resistance of the sense amplifier and the resistance of the bit line, a sample in which no partial disconnection is generated is operated normally, and the defect is generated when the incidental resistance of the part where the partial disconnection is generated becomes larger than the operating resistance of the FET, thereby, the partial disconnection can be decided.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a MOS memory LSI, and is particularly effective for an LSI having a memory cell consisting of one transistor and one capacitor.

[Prior Art] In a conventional memory array, if a line from pin 1 is disconnected due to a process defect, that bit line becomes malfunctioning.
I was able to sort it out. For example, Japanese Patent Application Laid-open No. 77946/1983 describes a redundant circuit that provides a spare memory array to repair defective addresses.

[Problems to be Solved by the Invention] However, if the wire is half-broken (R=1 to 100KΩ), it will operate electrically, resulting in a non-defective product.

If such a sample is operated for a certain period of time, it will break due to migration, become defective on the market, and must be removed as soon as possible. However, with current memory arrays,
I can't do this.

Means for Solving the Problems] An object of the present invention is to provide a method for detecting the aforementioned half-broken bit line and removing it by sorting before shipping.

[Operation] Adjacent bit lines are connected using MOS transistors, and during pre-shipment sorting, the operation is examined while operating this MOS.

The operating resistance of this MOS is the operating resistance of the sense amplifier,
By designing the resistance of the bit line to be sufficiently large, samples with no half-wire breaks will operate normally. However, if there is a half-disconnection and the parasitic resistance of the half-disconnection becomes greater than the operating resistance of the MOS, it can be determined to be defective.

Embodiment FIG. 1 is a circuit diagram showing a memory array according to an embodiment of the present invention.

In normal operation, bit line test signal TBL is set to Vcc, and M
The O8FETM1 to Mn are made conductive to perform a memory operation.

To evaluate bit lines BLI and BL2, bit line B
LO, BLI, BL2. Set BL3 and -BL below to Vcc and bit lines BLO, BLI, BL2 . Bf] and BLN to V
Enter the data as SS.

MO3FETMI, M3. The voltages across M4- and - are at the same potential, and MO8FETMI, M3. No current flows through Mn. The voltages across MO8FETM2 are different, and current flows. This current flows through the sense amplifier SA,1, the bit line BT-1, MO3FETM2, the bit line BL2, and the sense amplifier SA2.

The conduction resistance of MO8FETM2 is sense amplifier SA1.2
The bit line BLI is sufficiently larger than the conduction resistance of the bit line BLI and the parasitic resistance of the bit lines BLI and BL2.

Although the potential of BL2 changes slightly, it can operate normally. Consider what would happen if there was a half-break in the bit lines BLI and BL2. Suppose now that the center of the bit line BLI is partially disconnected. The bit line BLI to the left of the center (sense amplifier SA side) is at Vcc level, but to the right of the center is set to Vss by MO3FETM2 and sense amplifier SA2.
It becomes. If you select the memory cells in this part (
If the word line is in operation, this will be defective and can be determined.

[Effects of the Invention] According to the present invention, half-broken bit lines can be quickly removed, and the reliability of LSI can be improved.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a memory array according to an embodiment of the present invention. 5AO-N...Sense amplifier O-N, BL○~BWT=
...word line, Ilo...read/write signal line, T
E L...Bit line test signal, YDEC...Y
Decoder Figure 1 Eno θ

Claims (1)

[Claims] 1, a memory cell consisting of a transistor and a capacitor coupled to one electrode of the transistor; a word line connected to the gate of the transistor; and a memory cell coupled to the other electrode of the transistor; A memory circuit characterized in that, in a memory array including bit lines and a plurality of the memory cells described above, half-disconnection of a bit line is detected by adding a transistor that connects adjacent bit lines.