JPH01243149A - Non-volatile storage device - Google Patents

Abstract

PURPOSE:To prevent a dishonest security releasing inhibiting the output of protection information, which a non-volatile storage element for a security has, by means of a signal from a pressure detecting circuit when a power voltage outside a specification is impressed. CONSTITUTION:A transistor 21 for detecting a power voltage is made into an off-condition when a power voltage Vcc is at a specification maximum value or below, and it is changed from the off-condition to an on-condition by a voltage higher than the specification maximum value and lower than the voltage at which a transistor 11 for a security in a writing condition is made conductive. Consequently, when the power voltage Vcc is raised to the specification maximum value or above, the transistor 21 for detecting the power voltage before the transistor 11 for the security in the writing condition is made conductive, and a transistor 54 for a switch is turned off. Thus, the reading of storage information to an external part can be inhibited, and the security can be prevented from being dishonestly released.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory technology and a technology that is particularly effective when applied to the security protection of data stored in a non-volatile storage device. EFROM (erasable and programmable read-only)
It relates to effective technology that can be used for memory (memory).

[Conventional technology]

LS with built-in memory, such as a single-chip microcomputer (hereinafter referred to as a single-chip microcomputer)
In some cases, it is desired to protect the confidentiality of data written in a non-volatile memory element such as an EPROM built into a chip, that is, to prevent a third party from acquiring inappropriate data.

As a method for protecting data stored in a non-volatile memory device, for example, a storage register made of non-volatile memory elements is installed separately from a group of memory elements (memory cell array) for normal data storage. There is a system that prohibits external access to a group of storage elements depending on the state of a specific bit of this register (19).
Published March 3, 1983, [Electronic Design (E
electronic Design) J-Ppl
23-pp 128).

[Problems to be Solved by the Invention] However, in the case of non-volatile memory elements that store stored information as changes in threshold voltage, due to their characteristics, a power supply voltage higher than the standard value cannot be applied. As a result, the inventor's studies have revealed that there is a 5% chance that the transistor for the sequin tea will not operate properly and the above-mentioned protection will not be carried out.

The reason for this will be explained below.

FIG. 7 shows a FAMO8 (floating gate avalanche injection) as an example of an electrically programmable nonvolatile memory element that constitutes an EFROM.
The cross-sectional structure of a MOS transistor (MOS transistor) is shown.

In FIG. 7, 110 is a floating gate;
1 is a control gate, 112 is a source, and 113 is a drain.

Floating gate 110-, control game) 1
The source 11 is made of polycrystalline silicon, for example.
2. The drains 113 are each a P-type silicon substrate 100
An N-type region formed above.

Floating gate 110, source 112, drain 113, and substrate 100 are separated by an insulating film, and floating gate 110 and control gate 111 are also separated by an insulating film. The floating gate 110 is completely surrounded by an insulating film, is not in contact with anything, and has a floating potential.

The following table shows the voltages applied to the electrodes in each operation of the memory element shown in FIG. By applying voltage conditions as shown in Table 1 to each electrode of the memory element, writing and reading of ``0'' or 1'' is performed.

Table 1 First, the '0' write operation is performed on the substrate 100 and the source 11.
2 is connected to the ground point, and a high voltage Vpp (12.5 for flJ) is applied to the drain 113 and control gate 111.
This is done by giving V). At this time, source 112
A potential gradient is generated between the control gate 111 and the drain 113, and the electrons are accelerated by this electric field and have enough energy to overcome the energy barrier of the gate insulating film. Jump into 110. In the 70-ring gate 110, electrons are surrounded by an energy barrier of an insulating film and exist stably.

In the @1" sinking operation, the substrate 100 and the source 112 are connected to the ground, the drain 113 is applied with a high voltage vpp, and the control gate 111 is applied with a power supply voltage Vcc (for example, 5 V). In this case, Since the potential of the control gate 111 is low, electrons do not jump into the floating gate 1110, and the same state as before the floating operation is maintained.

Although not particularly limited, hereinafter, the state in which the floating gate 110 stores electrons will be referred to as 0'', and the state in which it does not store electrons will be referred to as 11''.

By the way, erasure of stored information is performed by ultraviolet irradiation. The electrons in the control gate 110 gain energy from the ultraviolet rays and jump out of the control gate, and the storage element enters the @1'' state.

Further, for reading, the substrate 100 and the source 112 are connected to the ground point, and the control gate 111 is connected to the power supply voltage VCC.
This is done by giving Under this voltage condition, data is output to the drain 113.

FIG. 8 is a basic characteristic diagram of the memory element shown in FIG. 7. Va
is the input voltage of the control gate 111, and I8D is the voltage between the source and drain.

The memory element in the 11″ state has a VQ of approximately IV and an Isn
begins to flow, whereas the memory element in the “0” state is
I8D does not flow unless it is shifted by the negative voltage of the electrons stored in the floating gate 11o and becomes about 7V to 10V. Therefore, when reading, the control gate 11
If the voltage VG applied to 1 is 5V, the memory element in the 1'' (unwritten) state is conductive (turned on), but the memory element in the '0''< i included) state is non-conductive (off). Can read stored information.

However, if the voltage applied to the control gate 111 is sufficiently high (for example, 10V), it will become conductive (turned on) regardless of the 1'' or '0'' state of the storage element.

FIG. 9 shows an example of a nonvolatile memory device that is secured using the nonvolatile memory element shown in FIG. 7. The circuit shown in FIG. 9 is a circuit constructed and studied by the inventor prior to the present invention.

In FIG. 9, 51 is a group of nonvolatile memory elements arranged in a matrix, 52 is an input/output circuit, 53 is an external input/output terminal, 54 is an N-channel MOS transistor for switching, and 11 is a security nonvolatile memory element. (transistor), 12 is a resistor, and 13 is an inverter.

When security protection for the nonvolatile memory element group 51 is required, writing is performed on the security transistor 11 using the method described above, and the transistor is brought into the 0'' (written) state. The input becomes a high level "H", and the switch transistor 5
The gate input of No. 4 becomes low level "L", and the switch (54) is turned off. As a result, input/output of data to/from the outside is prohibited.

On the other hand, when security protection is not required, the security transistor 11 is set to 1'' (unwritten) state. In this case, the input of the inverter 13 is L'', and the gate input of the reswitching transistor 54 is I Hn and the switch is turned on. This makes it possible to input and output data between the nonvolatile memory element group 51 and the outside via the external input/output terminal 53.

In the security system shown in FIG. 9, if the power supply voltage is higher than the standard maximum value, the security transistor 11 becomes conductive (turned on) even in the write state as described above, so data cannot be exchanged with the outside. There is a problem that input/output becomes possible and security cannot be protected. The above-mentioned problems were discovered as a result of studies conducted by the inventor prior to the present invention.

An object of the present invention is to effectively prevent unauthorized release of security protection due to application of a non-standard power supply voltage in a non-volatile storage device having a security protection function for stored information. be.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A summary of typical inventions disclosed in this application is as follows.

That is, a non-volatile memory element for security and a power supply voltage detection circuit are provided, protection information is stored in the non-volatile memory element for security, and when a non-standard power supply voltage is applied, the power supply voltage is A signal from the detection circuit is used to perform controls such as prohibiting the output of protection information that the security nonvolatile memory element is waiting for, or preventing the application of a non-standard power supply voltage to the control terminal of the security nonvolatile memory element. It is something.

[Effect]

According to the above-mentioned means, even if a non-standard power supply voltage is applied, the information stored in the security non-volatile memory element can be used correctly, thereby increasing the confidentiality of the non-volatile memory device having a security protection function. Able to achieve purpose.

〔Example〕

FIG. 1 shows an embodiment in which the present invention is applied to an EFROM.

In FIG. 1, 21 is an N-channel MO for power supply voltage detection.
The S transistor 23 is a logic gate consisting of a two-way AND circuit, and the power supply voltage Vcc is applied to the gate terminal of the transistor 21. The power supply voltage detection transistor 21 is turned off when the power supply voltage VCC is below the specified maximum value, and is turned off when the power supply voltage VCC is higher than the specified maximum value (lower than the voltage at which the security transistor in the write state becomes conductive). , and is configured to change from an off state to an on state.

In other words, as shown in the two-dimensional diagram showing the characteristics of the power supply voltage detection transistor 21 and the security transistor 11, the threshold voltage of the power supply voltage detection transistor 21 is greater than the standard maximum value of the power supply voltage, and the It is set smaller than the minimum value of the threshold voltage of the write state of No. 11. Security transistor 1
The power supply voltage ■co is also applied to the control gate terminal of No. 1.

Therefore, in this embodiment, if the power supply voltage VOO satisfies the standard, the power supply voltage detection transistor 21 always
is turned off. As a result, the transistor 21
The potential of the connection node between and the resistor 22 becomes vcc level, and one input of the logic gate 23 becomes @H". In this state, if the security transistor 11 is not written, the transistor 11 is turned on, transistor 1
The potential of the connection node between the resistor 1 and the resistor 12 becomes the ground potential (low level). As a result, the output of the logic gate 23 is 'H
", and the switching transistor 54 is turned on. On the other hand, if the security transistor 11 is in the write state (secure protection state), the transistor 11 is turned off and the two inputs of the logic gate 23 are both "". H”
The gate input of the switch transistor 54 is
L'', the switch is turned off, and data input/output between the nonvolatile memory element group 51 and the external input/output terminal 53 is blocked.

On the other hand, when the power supply voltage VCC is increased above the standard maximum value, the power supply voltage detection transistor 21 becomes conductive (turned on) before the security transistor 11 in the writing state, and one input of the logic gate 23 is always " The output of the logic gate 23 becomes L'' regardless of the other input, and the switching transistor 54 is turned off.As a result, when the power supply voltage cc becomes higher than the standard, the security transistor 11 Reading of the stored information to the outside is prohibited regardless of whether it is written or unwritten, and it is possible to prevent unauthorized release of security protection.

FIG. 3 is a block diagram showing another embodiment of the EFROM according to the present invention.

In Fig. 3, 31 is a load MO8) transistor, 32
1.322 is the resistance. The load MOS transistor 31 is configured as a P-channel type, and is always turned on by connecting its drain terminal and gate terminal. Transistor 31 and resistors 321 and 332 are Ve
It is connected in series between C and the ground point to form a resistive voltage divider circuit.

331.332 is the voltage divided by this resistance Vn4, Vn
, and 34.35 is a logic gate consisting of an AND circuit that receives the output signal of the inverter as input.

The inverters 331 and 332 detect the specified minimum and maximum values of the power supply voltage VCC, respectively, and set the output signal of the logic gate 34 to become H'' only when the power supply voltage v0° satisfies the specified value. Constants for each element are set.

FIG. 4 shows the characteristics of the inverters 331 and 332.

As the power supply voltage Vcc changes, the inverter 331.33
It shows the characteristics of 2.

Power supply voltage V. With the change in C, the inverter 331.33
The logic threshold of 2 also changes, and if the input voltage of the inverter is below the logic threshold, 'H' is output, and if it is above the logic threshold, 'L' is output.

Here, the inverter 3310 input voltage is the power supply voltage VC
C is the value obtained by subtracting the voltage drop caused by the load transistor 31, and the inverter 3320 input voltage becomes the value obtained by further subtracting the voltage drop caused by the resistor 321. Power supply voltage ■. As C increases, the divided voltage generated in the resistor voltage divider circuit also becomes high and the input voltage of the inverter increases.
The input voltage of the inverter 331 reaches the logic threshold, and the output of the inverter 331 changes from @Hn to "L".

When the power supply voltage vcc is further increased, the inverter 332
The 0 input voltage reaches the logic threshold and the output of inverter 332 changes from 'H' to @L'.

Moreover, the input voltage of the inverters 331, 332 can be freely set depending on the characteristics of the load transistor 31 and the resistance value of the resistor 321, 322. In this embodiment, the input voltage of the inverters 331, 332 is The values (logical thresholds) are matched with the standard minimum value and maximum value of the power supply voltage VCC, respectively. Therefore, if the power supply voltage VCC satisfies the standard value, the inverter 3
The outputs of 31 and 332 are ``L'' and ``H'', respectively, and a 1H'' level signal is output from the logic gate 34 to one input terminal of the logic gate 35.

Therefore, as in the above embodiment, depending on the state of the security transistor 11, if it is in the written state "0", the input/output blocking transistor 54 is turned off, and if it is in the unwritten state 11", the transistor 54 is turned on. It is determined whether security i1! (input/output blocking) is performed or not.

On the other hand, the power supply voltage Va. is below the standard minimum value, the outputs of inverters 331 and 332 are both set to 'H' level, and when the power supply voltage V0° is above the standard maximum value,
The outputs of the inverters 331 and 332 are both 'L'.However, in both cases, the output of the logic gate 34 is 'L', and the output of the logic gate 35 is forced to 'L'.
Since the voltage is set to "L", the transistor 54 is turned off and security protection is performed regardless of the state of the security transistor 11 as in the previous embodiment, and there is no attempt to illegally release the security protection by applying a voltage other than the standard. Attempts to do so are prevented.

FIG. 5 is a block diagram showing a third embodiment of an EPROM according to the present invention.

In Fig. 5, 411 is a P-channel type load MO8)
412 is an N-channel type load MO8) transistor, 421 and 422 are resistors, and 43 is an on/off transistor.

Although the conductivity types of the transistors 411 and 412 are different, their gate and drain terminals are connected to each other so that they act as a resistor.
11 is connected in series with a resistor 422 to form a resistive voltage divider circuit. Further, a load MO8) transistor 412 and a resistor 422 are connected in series between the drain terminal of the transistor 43 and VeC to form a voltage clamp circuit.

Then, the voltage generated by this voltage clamp circuit is applied to the gate terminal of the security transistor 11,
The gate voltage is prevented from rising above a certain value.

FIG. 6 shows the characteristics of the output voltage of the voltage clamp circuit input to the gate terminal of the security transistor 11.

The gate input voltage of the on/off transistor 43 is the power supply voltage ■. It is the value obtained by subtracting the voltage drop caused by the load transistor 411 from C. When the power supply voltage Vcc is sufficiently low, the on/off transistor 43 is in the off state,
No current flows through the resistor 422, the voltage drop across the resistor 422 is zero, and the gate input voltage of the security transistor 11 is equal to the power supply voltage Vcc. When the wL source voltage Vcc rises, the gate input voltage of the on/off transistor 43 also rises in proportion to this, and when the threshold voltage of the on/off transistor 43 is reached, the on/off transistor 43 becomes conductive (turned on). and current flows.

The gate input voltage of the security transistor 11 at this time is determined by the voltage held by the load transistor 412 and the on/off transistor 43, and is a constant value independent of the power supply voltage Vcc. The constant value can be arbitrarily set depending on the characteristics of the load transistor 412 and the on/off transistor 43, and in this embodiment, the threshold voltage value Vth■ of the security transistor 11 in the written state or less, the unwritten state The state threshold voltage value VthL or higher is set.

Therefore, even if the power supply voltage vec is increased above the standard,
Gate input voltage of security transistor 11 ″+
Hn does not rise above a certain level, and conduction does not occur regardless of the write state.

In this way, unauthorized release of security protection by setting the power supply voltage Vco above the standard is prevented.

As explained above, the above embodiment includes a security nonvolatile memory element and a power supply voltage detection circuit, stores protection information in the security nonvolatile memory element, and
When a non-standard power supply voltage is applied, a signal from the power supply voltage detection circuit prohibits the output of the protection information of the non-volatile memory element for security, or the control terminal of the non-volatile memory element for security. As a result, even if a non-standard power supply voltage is applied, the information stored in the security non-volatile memory element can be used correctly. This has the effect of improving security in a nonvolatile storage device having a security function.

FIG. 10 shows a block diagram of an embodiment of a one-chip microcomputer to which the present invention is applied.

In the figure, the part surrounded by the broken line is an integrated circuit LSI, and each circuit block formed here constitutes a 1-chip microcomputer as a whole, and is made of silicon using known semiconductor integrated circuit manufacturing technology. Like 1
formed on a single semiconductor substrate.

The symbol CPU is a microprocessor, and its main constituent blocks are illustrated as a representative example.

A is accumulator, X is index register, CC
is the condition code register, SP is the stack pointer, PCH and PCL are the program counters, and CPU-
C0NT is a CPU controller, and ALU is an arithmetic and logic operation unit.

The configuration of such a microprocessor CPU is well known, for example, from ``Fundamentals of Microcombinator'', written by Mitsuharu Yada, published by Ohmsha on April 10, 1978, so a detailed explanation thereof will be omitted. .

Denoted by symbol I10 is an input/output boat,
It contains a data transmission direction register therein. Also, the symbol shown is an input-only port.

A switch circuit SW for blocking input/output is provided on the signal line connected to the input/output capo (input/output capo) Ilo. The switch circuit SW includes an input/output blocking transistor 54 as shown in FIG. The input/output blocking switch circuit SW is controlled by a circuit according to the present invention as shown in FIGS. 1, 3, and 5. Note that an input/output blocking circuit having the same function as the switch circuit SW may be provided in the input/output capacitor I10 and controlled by the circuit according to the present invention. In this case, input/output capo) I10100 operations will be controlled.

What is indicated by the symbol O8C is an oscillation circuit, which forms a highly accurate reference frequency signal using an externally attached crystal resonator Xtal, although it is not particularly limited. This reference frequency signal forms the clock pulses required in the microprocessor CPU. Further, the reference frequency signal is also used as a reference time pulse of a timer.

This timer includes counter C0UT, grease scaler PR
and a controller CONT.

The symbol RAM is a random access
It is a memory and is mainly used as a temporary data storage circuit.

The symbol EPROM indicates electrical
It is a programmable read-only memory in which programs for various information processing are written.

The above circuit blocks are connected to each other by a bus BUS, with the microprocessor CPU as the center. This bus BUS includes a data bus and an address bus. It should be noted that the address bus ADD of the bus BUS is coupled to external terminals for write operations to the EPROM and the like.

In the micro combinator of this embodiment, the above E
Since FROM is used, the control circuit W for writing etc.
CON is established. Although not particularly limited, this control circuit WCON identifies the voltage level supplied from the external terminal VPP, controls the write/read operation mode, and supplies the write high voltage to the EFROM. For example, when a relatively low voltage (5■) such as the internal power supply voltage Vcc or a circuit ground potential is supplied from the external terminal Vl)p, a low-level identification signal is generated by the built-in voltage level detection circuit. This low level signal is used, for example, to set the EFROM to a read operation mode when the CPU selects the EFROM. On the other hand, when a high voltage (for example, about 12 V) for writing into the EPROM is supplied from the external terminal Vpp, a high-level identification signal is generated by the voltage level detection circuit. This high-level signal, for example, activates the data input buffer of the EFROM and, in accordance with the information supplied from the data bus, uses the high voltage Vl) to write a logic "0" high. Process and form the level signal,
Logic ``0'' is written into the selected memory cell (a nonvolatile memory element with a stacked gate structure having a control gate and a 70-ring gate). Note that at this time, the address signal is directly supplied to the EFROM from the outside.

Further, the integrated circuit LSI of this embodiment is, for example, entirely sealed in a plastic package or the like. Therefore, after the above packaging is done, the built-in EFR
The OM is disabled from its erase operation.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, the specific circuit for detecting the power supply voltage is not limited to the above embodiment (
Any device may be used as long as it performs the same operation as the above embodiment. The specific circuit of each circuit block may be any circuit that performs the same operation as the circuit in the above embodiment.

Furthermore, as shown in FIG. 10, it is also possible to form a nonvolatile memory device and a circuit device having other functions on the same semiconductor substrate. In this case, the form of confidentiality is
As shown in the figure, data input/output to and from circuit devices on the same board may be permitted, but input/output to the outside may be prohibited.

In the above explanation, the invention made by the present inventor was mainly applied to an EPROM device, which is the background field of application, but the present invention is not limited thereto. FROM) devices and other volatile storage devices in general.

[Brief explanation of the drawing]

FIG. 1 is a circuit configuration diagram showing a first embodiment when the present invention is applied to an EPROM, FIG. 2 is a graph showing the characteristics of the power supply voltage detection means of the first embodiment, and FIG. , a circuit configuration diagram showing a second embodiment of the EPROM according to the present invention, FIG. 4 is a graph showing the characteristics of the power supply voltage detection circuit of the second embodiment, and FIG. 6 is a graph showing the characteristics of the power supply voltage detection circuit of the third embodiment; FIG. 7 is a sectional view of a nonvolatile memory element constituting an EPROM; FIG. 8 is a graph showing the characteristics of a non-volatile memory element, FIG. 9 is a circuit configuration diagram of a non-volatile memory device having a security memory element proposed by the inventor prior to the present invention, and FIG. 10. 1 is a diagram of a built-in gPROM microcomputer to which the present invention is applied. Ilo...input/output port, SW...switch circuit,
O20...Oscillation circuit, ■...Input-only boat, Xt
al...Crystal resonator, C0UT...Counter, PR
... Grease scaler, C0NT... Controller, A
DD address bus OON...control circuit, A...
・Accumulator, X...index register, C
C...Condition code register, SP...Stack pointer, PCH, PCL...Program counter, CPU-C0NT...Controller, ALU-
Arithmetic logic unit. λya Ichicho - ('Jff [(T) [Kyouq taste]

Claims (1)

[Claims] 1. A plurality of external terminals, a plurality of nonvolatile memory elements, and a power supply voltage level detection means for detecting the voltage level of a power supply voltage supplied to a part of the plurality of external terminals. , read prohibition means for prohibiting information written in some of the plurality of nonvolatile memory elements from being read out to other parts of the plurality of external terminals, the read prohibition means , a nonvolatile memory device characterized in that it is controlled based on read control information obtained from another part of the plurality of nonvolatile memory elements and voltage level information obtained from the power supply voltage level detection means. 2. The non-volatile device according to claim 1, wherein the read prohibition means prohibits read regardless of the content of the read control information when the voltage level is higher than a predetermined voltage. Sexual memory. 3. The plurality of nonvolatile memory elements are configured by stacked gate transistors whose threshold voltages are changed depending on whether or not charge is accumulated under the control gate. A nonvolatile storage device according to claim 2. 4. The nonvolatile memory device according to claim 3, wherein a voltage at a power supply voltage level is supplied to the control gate of the nonvolatile memory element having the read control information. 5. Claim 4, characterized in that the read prohibition means is a switch means provided between a part of the plurality of nonvolatile memory elements and a part of the plurality of external terminals. Non-volatile storage device as described. 6. A plurality of external terminals, a plurality of stacked gate nonvolatile memory elements whose threshold voltages are changed depending on whether or not charge is accumulated under the control gate, and a plurality of the external terminals. power supply voltage level control means for controlling the voltage level of a power supply voltage supplied to some of the plurality of nonvolatile memory elements to a predetermined level or less; read prohibition means for prohibiting reading by another part of the plurality of nonvolatile memory elements, and the read prohibition means is a part of the other part of the plurality of nonvolatile memory elements, and the control gate thereof is connected to the power supply voltage. A nonvolatile memory device characterized in that it is controlled by read control information obtained from a nonvolatile memory element to which an output voltage of a level control means is supplied. 7. Claim 6, characterized in that the read prohibition means is a switch means provided between a part of the plurality of nonvolatile memory elements and a part of the plurality of external terminals. Non-volatile storage device as described. 8. A plurality of external terminals, a plurality of nonvolatile memory elements, a power supply voltage level detection means for detecting a voltage level of a power supply voltage supplied to a part of the plurality of external terminals, and a plurality of nonvolatile memory elements. read prohibition means for prohibiting information written in a part of the storage element from being read out to other parts of the plurality of external terminals; A microcomputer characterized in that the microcomputer is controlled based on read control information obtained from another part of the storage element and voltage level information obtained from the power supply voltage level detection means. 9. The microcomputer according to claim 8, wherein the read prohibition means prohibits read regardless of the content of the read control information when the voltage level is higher than a predetermined voltage. Computer. 10. The plurality of nonvolatile memory elements are configured by stacked gate transistors whose threshold voltages are changed depending on whether or not charge is accumulated under the control gate. A microcomputer according to claim 9. 11. The microcomputer according to claim 10, wherein a voltage at a power supply voltage level is supplied to the control gate of the nonvolatile memory element having the read control information. 12. Claim 11, characterized in that the read prohibition means is a switch means provided between a part of the plurality of nonvolatile memory elements and a part of the plurality of external terminals. The microcomputer described.