JPH01241160A - Compound semiconductor device - Google Patents

Abstract

PURPOSE:To obtain the structure of a small area memory cell which is suitable for high integration and is equipped with performance which is able to withstand alpharays, by depositing low resistive materials at a part of high resistive elements which are provided so as to form high resistance load, thereby forming low resistive electrodes. CONSTITUTION:A flip-flop is composed of a transistor consisting of gate electrodes 1 and 2 as well as high resistance elements 20 and 21. With the intention of causing the flip-flop to be equipped with performance which is able to withstand alpha rays, this device makes a part of high resistance elements 20 and 21 low resistive and causes them to act as one side of the electrodes 30 of a capacitance for withstanding the alpha rays and then, the second power source 100 serves for the other electrode of the capacitance. The low resistive electrodes 30 and 31 are formed by depositing low resistive materials to the part of the high resistance elements 20 and 21 which are provided so as to form high resistance load of the flip-flop; besides, the foregoing electrodes are made up on a transistor region. Thus, a small area memory cell equipped with performance which is hole to withstand the alpha rays without making manufacturing processes complicated.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a structure of a small area memory cell of a compound semiconductor memory device, and particularly to a structure of a memory cell suitable for increasing the degree of integration of a compound semiconductor integrated device.

[Conventional technology]

The structure of a conventional general memory cell is described in Proceedings of the 1985 National Conference of the Institute of Electronics and Communication Engineers, Optical and Radio Division, 1゜p. 181-p.
182 rGaAs High Density LSI Wiring Technology”
It is described in. FIG. 5 shows the memory cell pattern described in the above-mentioned manuscript collection.

A first source transistor consisting of a gate electrode 1, a source electrode 15, and a drain electrode 7; a second transistor input consisting of a gate electrode 2, a source electrode 15, and a drain electrode 8; a gate electrode 3, a source electrode 7, and a drain electrode; 11, a third transistor consisting of a gate electrode 4 and a source electrode 8
and a drain electrode 12, a fifth transistor consisting of a gate electrode 5, a source electrode 7, and a drain electrode 13, and a sixth transistor consisting of a gate electrode 6, a source electrode 8, and a drain electrode 14.
The gates of the first transistor and the second transistor are formed in the first wiring layers 101 and 102.

A flip-flop circuit is constructed by cross-wiring the drain electrodes 1.2, 7.8.

Furthermore, the source electrodes 7.8 of the third and fourth transistors for writing information to and reading information from the flip-flop are the drain electrode 7 of the first transistor and the drain electrode of the second transistor, respectively. It is shared with 8. The drain electrode 11 of the third transistor and the drain electrode 12 of the fourth transistor are connected to the data line pair 105, 106 via the first wiring layer 108, 109 and through holes 200, 201. Note that the wiring 104 formed of the first layer wiring is a signal line for memory cell selection, and the third. Fourth
It is connected to the gate electrode 3.4 of the transistor.

As a load of the flip-flop, the source electrodes 7 and 8 of the fifth and sixth transistors are shared with the drain electrodes 7 and 8 of the first and second transistors, respectively. The gate electrodes 5, 6 and the source electrodes 7, 8 are commonly connected by first layer wirings 101, 102. The first power source 103 formed by the first layer wiring is connected to the drain electrodes 13 and 14 of the fifth and sixth transistors in common, and the second power source 103 is formed by the second layer wiring. A power source 100 is connected to a common source electrode 15 of the first and second transistors via a first layer wiring 107. The above memory cell is
Although this structure is commonly used in GaAs storage devices, no consideration is given to malfunctions caused by alpha rays, resulting in the following inconveniences. In order to provide a memory cell with α-ray resistance, as shown in the equivalent circuit shown in FIG. FIG. 6 shows an example of a cell pattern diagram of a memory cell that is generally connected to the second power supply 100 and has the above-mentioned resistance in the fifth memory cell. As electrodes for α-ray resistant capacitors, low resistance electrodes with good high frequency characteristics are required, so the first and second layer wiring shown in Figure 6, which usually has a sheet resistance of several tens of mΩ, are used as electrodes. It is possible that In FIG. 6, electrodes 30 and 31 are one electrode of an α-ray resistant capacitor formed of the first layer wiring layer, and the other electrode of the capacitor is formed of the second layer wiring 100. . As can be seen from FIG. 6, if an attempt is made to add a capacitor for α-ray resistance to the conventional memory cell structure using the same manufacturing process, an increase in the cell area will inevitably occur. In addition,
40 and 41 are through holes for forming a high dielectric insulating layer between the electrodes of the capacitor.

Another option is to add a wiring layer and form a capacitor on the transistor that constitutes the memory cell, but adding a wiring layer would complicate the manufacturing process, so it is not an efficient method. That's hard to say.

[Problem to be solved by the invention]

The above conventional technology has the problem of increasing the memory cell area because no consideration is given to reducing the memory cell area when trying to realize a memory cell with α-ray resistance in a small area suitable for high integration. Ta.

An object of the present invention is to obtain a small-area memory cell structure that is suitable for high integration and has α-ray resistance.

[Means for Solving Problem 1111] The above object is to reduce the resistance by depositing a low resistance material on a part of a high resistance element for forming a high resistance load. This is achieved by forming poles.

[Effect]

By depositing molybdenum metal or the like on a part of the high-resistance element, it is possible to reduce the sheet resistance of the part of the high-resistance element to several hundred mΩ or less. This makes it possible to form a low-resistance electrode with good high-frequency characteristics and a capacitance for α-rays in a part of the high-resistance element. The low-resistance electrode can be formed at the same time as creating the high-resistance element, and can also be formed on the top of the transistor element area, so it can be formed in a small area with α-ray resistance without adding an additional wiring layer. It becomes possible to realize memory cells.

〔Example〕

An embodiment of the present invention will be described below with reference to a planar pattern diagram of FIG. In FIG. 1, the arrangement of the transistor made up of gate electrodes 1 to 4 is the same as that of gate electrodes 1 to 4 in FIG.
The arrangement is the same as that of the transistor made up of four transistors. In the conventional example shown in FIG. 5, a transistor consisting of gate electrodes 5 and 6 was used as a load transistor of a flip-flop, but in the embodiment shown in FIG. The reason for using a high resistance element in this example is that silicon SRAM
etc., a high resistance element is formed on the transistor element region,
A method of reducing the cell area is generally taken, and Ga
This is because, considering future high integration in AsLSI, it is thought that there will be a trend toward using high-resistance elements as loads for flip-flops. The main structure of FIG. 1 is shown below. The flip-flop is composed of a transistor consisting of a gate f[il,2, and high resistance elements 20 and 21. In order to provide the flip-flop with α-ray resistance, a part of the high-resistance element is made to have a low resistance and serves as one electrode 30, 31 of the α-ray resistance capacitor, and the second power supply 100 also serves as the other electrode of the capacitor. ing. The memory cell selection 1iA 104 and the data line pair 105 and 106 are connected to a flip-flop through an information read/write transistor formed of gate electrodes 3 and 4. In the present invention, the low-resistance electrodes 30 and 31 can be formed by depositing a low-resistance material on a part of the high-resistance purple potatoes 20 and 21 for forming the load of the flip-flop, and also on the transistor region. Since it is configurable, it is possible to reduce the area of the memory cell.

In addition, the low resistance electrodes 30.31 are the high resistance elements 20°21
It can be formed by simply depositing a low-resistance material on the transistor area, and is more effective in terms of simplifying the manufacturing process than the method of increasing the number of wiring layers and forming the capacitor electrode on the transistor area. be.

This example will be described in detail below. In FIG. 1, high-resistance elements 20.21 are formed of, for example, cermet, and one electrode of 20.21 is connected to a through-hole 20.
The other electrode is connected to the first power supply 103 formed of the first wiring layer through the gate electrodes 1 and 205.
The first part consists of Drain electrode of the second transistor! The gate and drain electrodes 1, 2, 7, and 8 of the first and second transistors are connected to the wiring layers 101 and 102 through the wiring layers 102 and 204 of the first and second transistors, respectively. 101 and 102 are cross-connected to form a flip-flop. One electrode 30.31 of the α-ray resistant capacitor is connected to the high resistance element 20.2.
By depositing a metal such as molybdenum on a part of 1, the resistance is lowered.

Furthermore, 30.31 is the first. It is connected to the drain electrodes 7 and 8 of the second transistor via through holes 202 and 204. On the other hand, the other electrode of the α-ray resistant capacitor is connected to the second electrode.
A portion of the wiring layer 100 is formed of the first wiring layer 100.
'The shared source electrode 15 of the second transistor is connected to the first wiring layer 107 via a through hole 212.

Between the ffi poles of the α-ray resistant capacitor, through holes 40 and 41 are provided to form a high dielectric constant aWi to increase the capacitance per unit area. Third, the gate electrodes 3 and 4 were purchased. The fourth transistor is
The source electrodes 7 and 8 are the first. The gate electrodes 3 and 4 are commonly connected to the memory cell selection line 104 formed by the first M wiring, and the drain electrodes 11 and 12 are common to the drain electrodes 7 and 8 of the second transistor. It is connected to the data line pair 105° and 106 formed by the second layer wiring through layer wiring 108 and 109 and through holes 200 and 201, and functions as a switch for writing and reading information into the memory cell. doing. Figure 2 is the first
The figure shows a cross-sectional structure taken along line A-A' in the plane pattern diagram, and 61 indicates N corresponding to the transistor channel layer.
type impurity layer, 1 is a transistor gate electrode layer, 20 is an adhesion layer for forming a high resistance element, 30 is a low resistance layer for reducing the resistance of a part of the high resistance element adhesion layer, 42 is a high dielectric constant Insulating layers 101, 102, 103, and 104 are first wiring layers for connecting the electrodes of each transistor, each resistive element, and each capacitive element, 100 is a second wiring layer, 62 is an insulating film layer, 60 is a semi-insulating GaAs substrate. The adhesive layer 20 for forming a high-resistance element is formed of, for example, cermet (Cr-S i 02) having a J height of 1,000 to 5,000, and its sheet resistance is approximately several hundred ohms.

Further, one electrode 3o of the alpha ray resistant capacitor formed of a low resistance layer for lowering the resistance of a part of the high resistance element is formed by applying, for example, molybdenum metal or the like to a part of the high resistance element adhesion layer. It is formed by depositing several thousand layers, and its sheet resistance value is about several hundred mΩ. The high dielectric constant insulation R442 is formed, for example, by depositing silicon nitride (SiN) tr=8t or tantalum oxide (Tazo a) ε=24, etc. to a thickness of several hundred. The second power supply 100 formed of the wiring layer also serves as the other electrode of the α-ray resistant capacitor, and the high dielectric constant insulating layer 42
A parallel plate capacitor is formed with the other electrode 3o via the electrode 3o.

As described above, according to this embodiment, a low-resistance electrode can be formed by depositing a low-resistance material on a part of a high-resistance element, and the low-resistance electrode can also be formed on a transistor region. By using one electrode of the possible α-ray resistant capacitor, it becomes possible to realize a small-area memory cell with α-ray resistant performance without complicating the manufacturing process.

FIGS. 3 and 4 show a planar pattern diagram and a sectional structural diagram of another embodiment of the present invention. In this example.

Unlike the embodiments described in FIG. 1 and FIG.
, 109, an insulating film layer 62 is formed between them. Third
In the figure, contact through holes 210, 211, 2
13, 214 connect the electrodes 1, 2, 7.8 of the transistor and the first wiring layer 101, 102, and the through hole 20'2, 204 connects one electrode of the high resistance element with the above and the first wiring layer 101, 102. The wiring layers 101 and 102 are connected, and further,
The through holes 212 and 216 connect the common source electrode 15 of the transistor and the power supply 100 to form a flip-flop. Through hole 200, 2
01, 206, 207 are transistor electrodes 11.1
2 and the data line pair 105° 106 in the first wiring layer 108,
109, and through holes 208,
209, transistor electrodes 3, 4 and memory selection line 10;
4 are connected to form a section for writing and reading information into memory cells. FIG. 4 shows a cross-sectional structure taken along line A-A' in the plane pattern diagram of FIG.
The first wiring layer 250 is a contact electrode for connecting the first layer wiring 101 and the gate electrode layer 1 of the transistor, and 62 is an interlayer insulating film layer between the first wiring layer and the transistor electrode layer.

Providing an insulating film layer between the electrode layer of the transistor and the first wiring layer as described above makes it possible to form the first wiring layer in the upper layer of the transistor region, and as shown in FIGS.
Compared to the embodiment described in the figures, it is possible to obtain the effect that the degree of freedom of the first wiring layer is improved.

[Effects of the Invention] According to the present invention, an α-ray resistant capacitor can be formed on the transistor region without complicating the manufacturing process, and the electrodes, 8...
An electrode in which the drain electrode of the first transistor and the source electrode of the third transistor are shared, or an electrode in which the sixth transistor electrode is also shared, 11...Drain electrode of the third transistor, 12... Drain electrode of the fourth transistor, 13... Drain electrode of the fifth transistor, 14... Drain electrode of the sixth transistor, 15... Common source electrode of the first and second transistors , 20.21...first high resistance element,
30.31...One electrode of the α-ray resistant capacitor, 40.4
1...Through hole for forming capacitance for α-ray resistance, 42...
High dielectric constant insulating layer for forming capacitance for alpha rays, 60...Ga
A s substrate, 61...transistor active layer, 62...
...Interlayer insulating layer, 100... Also serves as one electrode of the α-ray resistant capacitor in the second power supply. 101, 102, 107, 1
08°109...First layer wiring layer, 103...First
power supply.

104...Memory cell detection signal line, 105, 106
...Data wire, 200-216...Through hole for contact, 250...Contact electrode, Cx, C
z... Capacitor for α-ray resistance, Ji to J8... Transistor.

Therefore, it is possible to realize a small-area memory cell for highly integrated devices with α-ray resistance that can reduce the memory cell area by several tens of percent compared to the conventional memory cell.

[Brief explanation of the drawing]

FIG. 1 is a planar pattern diagram of a memory cell showing one embodiment of the present invention, FIG. 2 is a sectional view taken along line A-A' in FIG. 1, and FIG. 3 is a memory cell showing another embodiment of the present invention. Figure 4 is a cross-sectional view taken along line A-A' in Figure 3. Figure 5 is a diagram of a conventional memory cell plane pattern. Figure 6 is a diagram of a conventional memory with α-ray resistant capacity. A cell pattern plan view, FIG. 7, is a diagram showing a conventional memory cell equivalent circuit.

Claims (1)

[Claims] 1. The gate electrode of the first transistor and the drain electrode of the second transistor are connected, the gate electrode of the second transistor and the drain electrode of the first transistor are connected, and the first One electrode of the first high-resistance element is connected to the drain electrode of the transistor, one electrode of the second high-resistance element is connected to the drain electrode of the second transistor, and the first and second transistor The other two electrodes of the second high resistance element are commonly connected to a first power source, and both source electrodes of the first and second transistors are commonly connected to the second power source. . A compound semiconductor device comprising a region having low resistance by depositing a low resistance metal layer on parts of the first and second high resistance elements. 2. One electrode of the first and second alpha ray resistant capacitors is commonly connected to the second power supply, and one of the first alpha ray resistant capacitors is connected to the gate electrode of the first transistor. one electrode of the second alpha ray resistant capacitor is connected to the gate electrode of the second transistor, and one electrode of the first and second alpha ray resistant capacitor is connected to the low resistance capacitor. 2. The compound semiconductor device according to claim 1, wherein the compound semiconductor device is comprised of a region. 3. One electrode of the first and second α-ray resistant capacitors is commonly connected to the first power supply, and one of the first α-ray resistant capacitors is connected to the gate electrode of the first transistor. one electrode of the second α-ray resistant capacitor is connected to the gate electrode of the second transistor, and the first and second α-ray resistant capacitors are connected to each other.
2. The compound semiconductor device according to claim 1, wherein one electrode of the line capacitance is comprised of the low resistance region.