JPH01241096A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To reduce the power consumption of a semiconductor memory by providing a refreshing period control circuit which controls the refreshing period of a refreshing period generating circuit based on the output of a memory cell for decision. CONSTITUTION:A sense amplifier 9 for decision amplifies a very weak signal from a memory cell 8 for decision to a usually used level and a refreshing period control circuit 10 changes the refreshing period of a refreshing period generating circuit 11 in accordance with the output of the sense amplifier 9. A refresh mode selector 12 switches refreshing operations between the refreshing operation to be performed in response to a refresh signal REF from the outside and the refreshing operation to be performed in response to the output of the refreshing period generating circuit 11 based on a refresh mode signal RFM. Since the refreshing period is controlled to a value close to the storage holding time of the memory cell 8 for decision, the electric power consumed by the refreshing operation can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory used in an information processing device, and more particularly to a semiconductor memory using dynamic memory cells that require a refresh operation for memory retention. .

[Conventional technology]

Conventionally, this type of semiconductor memory is a MOS as shown in Figure 2.
A dynamic memory cell consisting of a transistor 20 and a capacitor 21 is used. In the figure, the MOS transistor 2o is turned on by setting the word line 23 to a high level when writing or reading information to the capacitor 21, and the gauge is set.

The information on the digit line 24 is written to the capacitor 21, but the information from the capacitor 21 is read to the digit line 24. In such a dynamic memory cell, since information is stored in the capacitor 21, the information is lost after a certain period of time due to leakage current of the MOS transistor 20 or the like. In order to avoid this, a so-called refresh operation is performed in which the information in the capacitor 21 is read out and then rewritten at fixed intervals, that is, every memory cell retention time. A semiconductor memory using such a dynamic memory cell has a structure as shown in FIG. In FIG. 3, an address selector 1 outputs either an external address signal ADD or a refresh address signal from a refresh address counter 5, and a row address decoder 2 is composed of a plurality of dynamic memory cells for rows and columns. The column address decoder 4 selects one of the plurality of rows of the dynamic memory array 3 arranged in a matrix, the column address decoder 4 selects one of the plurality of columns, and the sense amplifier 6 amplifies the minute signal from the dynamic memory cell array 3, and the human output buffer 7 provides write data from the outside to the sense amplifier 6 during writing, and transmits read information from the dynamic memory cell array 3 through the sense amplifier 6 during reading. This is a bidirectional buffer circuit that reads data to the outside. The refresh address counter 5 is a binary counter having a number of bits corresponding to the number of rows in the dynamic memory cell array 3 (for example, 9 bits when the number of rows is 512), and receives an external refresh signal REF. Counts up by +1 each time.

In the conventional semiconductor memory described above, it is necessary to refresh all the memory cells forming the dynamic memory cell 3 within the memory retention time of the dynamic memory cell, and the dynamic memory cell array 3 needs to be refreshed within the memory retention time of the dynamic memory cell. The time multiplied by the number of rows is made to be within the memory retention time of the dynamic memory cell.

For example, if the memory retention time is 8 ms and the number of rows is 512, 15
．． It will be within 6 μS.

In general, the memory N1 time of a dynamic memory cell varies greatly for each individual semiconductor memory due to manufacturing variations, and it is stipulated that the refresh operation should be performed within the memory retention time allowed for the manufactured product. Ta. Therefore, most semiconductor memories have a longer memory retention time than the above value, and refresh operations are performed in a much shorter period than the actual value of dynamic memory cells. Furthermore, although the memory retention time varies greatly depending on the temperature in use, changing the refresh operation cycle from the outside in response to changes in temperature requires a complicated circuit, so it has not been used.

[Problem to be solved by the invention]

In the conventional semiconductor memory described above, the refresh operation cycle is constant, so the refresh operation is performed at a cycle that is significantly shorter than the actual value of the memory retention time of the dynamic memory cell in each semiconductor memory. For this reason, there is a drawback in that power consumption is significantly large, especially when performing only a memory retention operation.

In the conventional semiconductor memory described above, the refresh period was fixed, but in the present invention, a memory cell for judgment, a sense amplifier for judgment, and a refresh control circuit are added to refresh the memory according to the memory retention time of the memory cell for judgment. The difference is that the refresh period of the period generating circuit is configured to be automatically changed.

[Means for solving problems]

The semiconductor memory of the present invention includes a plurality of dynamic type memories that store information, at least one determination memory cell whose memory retention time is shorter by a predetermined percentage than the dynamic type memory cells, and an internal refresh operation. The refresh cycle generation circuit includes a refresh cycle generation circuit for performing the determination, and a refresh cycle control circuit that controls the refresh cycle of the refresh cycle generation circuit based on the output from the determination memory cell.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a diagram showing an embodiment of the present invention. In FIG. 1, circuits that perform the same functions and operations as those in FIG. 2 are given the same numbers, and their explanations will be omitted.

In FIG. 1, the determination memory cell 8 is constructed by, for example, reducing the capacitance of the capacitor so that the memory retention time is shorter than the memory retention time of the dynamic memory cell array 3 that stores information by the amount of characteristic variation within the semiconductor memory. The judgment sense amplifier 9 amplifies the minute signal from the judgment memory cell 8 to a normally used level.
The refresh period control circuit 10 includes a judgment sense amplifier 9
The refresh cycle of the refresh cycle generating circuit 11 is changed according to the output of the refresh cycle generating circuit 11, and the refresh cycle of the refresh cycle generating circuit 11 is changed according to the output of
is provided to switch based on the refresh mode signal RFM whether the refresh operation is performed in response to the external refresh signal REF or in response to the output of the refresh cycle generation circuit. Each time a refresh operation is performed, previous information is read into the determination memory cell 8, and a predetermined level, for example, a high level, is written. Therefore, in each refresh operation, the determining sense amplifier 9 and the refresh cycle control circuit 10 determine whether or not the previously written high level can be read without error, thereby controlling the refresh cycle of the refresh cycle generating circuit 11.

If the information read from the judgment memory cell 8 is incorrect, the refresh cycle is shortened, and if the information read from the judgment memory cell 8 is correct, the refresh cycle is controlled to be shortened. Through such control, the refresh cycle of the refresh cycle generation circuit 11 is always controlled to match the memory retention time of the determination memory cell 8.

FIG. 4 is a diagram showing a part of another embodiment of the semiconductor memory of the present invention. In the figure, the memory cell for determination 8
4 sense amplifiers for judgment are used.
1, and any one of the plurality of determination memory cells
If the read information is incorrect, the logic circuit 42 determines that the read information is incorrect and outputs it to the refresh control circuit. By using a plurality of determination memory cells 8 in this way, the accuracy of the memory retention time in the semiconductor memory is improved.

From the above, since the refresh period is always controlled to a value close to the memory retention time of the determination memory cell, it changes depending on the actual value of the memory retention time of the dynamic memory cell inside the semiconductor memory.

〔Effect of the invention〕

As explained above, the present invention is configured to automatically change the refresh cycle according to the actual performance value of the dynamic memory cell in the semiconductor memory, so that the refresh cycle is significantly longer than the predetermined refresh cycle. This has the effect of significantly reducing the current consumption required for refresh operations.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the semiconductor memory of the present invention, and FIG.
FIG. 3 is a circuit diagram of a dynamic memory cell, FIG. 3 is a block diagram of a conventional semiconductor memory, and FIG. 4 is a partially modified block diagram of another embodiment of the semiconductor memory of the present invention. 1... Address selector, 2... Row address selector, 3... Dynamic memory cell, 4... Column address decoder, 5...
...Refresh address counter, 6...
...Sense amplifier, 7...Human output huffer, 8
... Group memory cell for judgment, 9.41... sense amplifier for judgment, 10... Refresh cycle control circuit, 11... Refresh cycle generation circuit, 12...
...Refresh mode selector, 20...
・MOS) transistor, 21...Electricity storage L23,
43...mark/word line, 24...dan/digit) L42
......AND circuit, ADD...address signal, REF...refresh signal, RFM...group refresh mode signal, DATA...data signal. Agent Patent Attorney Uchihara Otoshi 2nd grade

Claims (1)

[Claims] In a semiconductor memory using dynamic memory cells that require a refresh operation for memory retention, there are a plurality of dynamic memory cells that store information, and the memory retention time is increased by a predetermined percentage from the dynamic memory cells. A short memory cell for at least 11 determinations, a refresh cycle generation circuit for performing an internal refresh operation, and a refresh cycle control circuit that controls the refresh cycle of the refresh cycle generation circuit based on the output from the determination memory cell. Semiconductor memory including.