JPH0123807B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a full adder, and provides a full adder whose circuit configuration is simplified by using multivalued logic, and which is high speed, has low power consumption, and can be highly integrated. In general, a full adder has three inputs (each
Let A, B, C _i . ) and two outputs (sum output S,
Let Co be the carry output. )have. Input A,
Between B, C _i and the outputs S, Co, there are 2 as shown in Table 1.
It has the relationship shown by the truth table of values.

[Table] If the above truth table is expressed using a pool equation, it can be expressed as shown in the following equation. S=A・B・C _i +A・・_i +・B・_i +・・C _i (1) C ₀ =A・B・C _i +A・B・_i +A・・C _i +・B・C _i (2) Figure 1 shows a conventional example in which a full adder is configured with AND and OR binary logic gates. In Figure 1, 1, 2...6 are AND gates,
7, 8, and 9 are NOR gates. However, 1,
One of the input terminals of AND gates 2, 4, and 6 is an inverting input. If the full adder is configured with binary logic, six gates are required in FIG. 1. Furthermore, when a circuit is actually constructed using transistors, resistors, etc., the number of elements becomes considerably large. In addition, it is generally used as a logic gate to increase speed.
It is necessary to use ECL logic gates, but since ECL logic gates are of a differential type, the circuit becomes very complex and the number of elements increases. Full adders are commonly used in large numbers as basic building blocks such as adder multipliers. To configure a 16-bit adder, 16 full adders are required. Therefore, if the full adder has a large number of elements, it is extremely disadvantageous when integrated into semiconductors due to problems such as chip size limitations and power consumption. The present invention provides a full adder that solves the problems of the conventional full adder described above. That is,
By using multi-value logic for signal processing inside the full adder, the circuit is simplified and the number of elements is reduced. The circuit according to the present invention adds three binary inputs A, B, and C _i to obtain four values, and compares the four-value signals with two voltage comparators. It is the one that obtains the force Co. FIG. 2 shows and describes the basic configuration of a full adder according to an embodiment of the present invention. 11 is an adder, 1
2 is a first voltage comparator, 13 is a second voltage comparator, and 14 is a fundamental voltage generation circuit. 2 each
Inputs A, B, and C _i having value signals are added by an adder 11 and converted into a four-value signal V _IN having four voltage levels of V ₀ , V ₁ , V ₂ , and V ₃ . Table 2 shows a correspondence table between the inputs A, B, C _i , the outputs S, C ₀ and the 4-value signal V _IN .

[Table] Here, the voltages of V ₀ , V ₁ , V ₂ , and V ₃ are as follows: V ₀ > V ₁ > V ₂ > V ₃ (or V ₀ < V ₁ < V ₂ < V ₃ ) (3) have. Next, the four-value signal V _IN is compared by two voltage comparators to obtain outputs S and C ₀ . Repeat this action in the third
This will be explained using figures. FIG. 3 illustrates the relationship among the four-value signal V _IN , the outputs S and C ₀ , and the reference voltages Va _, V _b , and V _c of the voltage comparators. As is clear from the truth table in Table 2, the carry output C ₀ is output when the 4-level signal V _IN is V ₂ or
Since this is the time when the voltage level reaches V ₃ , the reference voltage V _a of the first voltage comparator 2 is compared as V ₁ > V _a > V ₂ (or V ₁ < V _a < V ₂ ) (4) Then, you can obtain the carry up force C ₀ . Further, the sum output S is output when V _IN has a voltage level of V ₁ or V ₃ . Now, looking at the relationship between the carry output C ₀ , the sum output S, and the 4-value signal V _IN , when C ₀ is not output (set to ₀ in Figure 3), the sum output S is output. teeth
The sum output S is output when V _IN has a voltage level of V ₁ and C ₀ is output when V _IN is V ₃
when it has a voltage level of . Therefore, when C ₀ is not output, the reference voltage V _B of the second voltage comparator 3 is set as V _b V ₀ > V _b > V ₁ (or V ₀ < V _b < V ₁ ) (5), When compared with V _IN , when C ₀ is output, V _c V ₂ > V _c > V ₃ (or V ₂ < V _c < V ₃ ) (6) If compared with V _IN , the output output S can be obtained. In FIG. 2, the reference voltage generating circuit 4 generates the reference voltage _Vb or _Vc in accordance with the output of the first comparator, that is, the carry signal _C0 , as described above. Here, in the present invention shown in FIG. 2, by setting the input as a current input, the configuration of the adder 11 is as follows.
It is also possible to configure it with one resistor. Furthermore, by making the output a current output and making the input and output current values the same, an interface between the input and output can be established, which is very advantageous when integrating the present full adder. Next, the specific configuration of the first embodiment of the present invention will be explained in the fourth section.
As shown in the figure. In FIG. 4, circuits corresponding to the blocks in FIG. 2 are shown by broken lines and will be explained. Here, T ₁
~ _T5 is a transistor, _R1 to _R3 are resistors, _I1 and _I2 are constant current sources, and _Vcc and _Va are constant voltage sources. In FIG. 4, the adder 11 is formed by a resistor R ₁ to which three current inputs having a binary state are applied to one terminal and the other terminal is connected to a DC voltage source _Vcc , and outputs a four-value signal. obtain. The voltage comparator 12 consists of a differential switch consisting of a transistor T ₂ with a reference voltage source _{V a} connected to the base of the transistor T ₁ and a current source I ₁ , and the four-value signal is applied to the base of the transistor T ₁ . The configuration is such that a carry signal _C0 is obtained from the collector of the transistor _T2 . The voltage comparator 13 consists of transistors T ₄ , T ₅ and a current source I ₂ .The four-value signal is applied to the transistor T ₅ , and a sum output is generated from the collector of the transistor T ₄ , whose base connects the resistor R ₃ . It is grounded through. The reference voltage generation circuit 14 includes a resistor R ₂ , a transistor T ₃ , and a DC voltage source V _a . A second embodiment of the invention is shown in FIG. The circuit shown in FIG. 5 has diodes in the voltage comparators indicated by broken lines 12 and 13 in the circuit shown in FIG.
By adding D ₁ and D ₂ , the saturation operation of the transistor is eliminated and the operation speed is increased. As described above, in the full adder of the present invention,
The circuit configuration is greatly simplified compared to conventional full adders, and the delay time between input and output is only the delay time of two stages of differential amplifiers, so the number of logic gates is small.
It is possible to increase the speed. Further, the full adder of the present invention can operate even if the power supply voltage is reduced,
It is possible to configure a low power consumption circuit. Further, when a semiconductor integrated circuit is constructed using the full adder of the present invention, the circuit configuration is simplified and power consumption can be reduced, so that high integration can be achieved.

[Brief explanation of drawings]

Fig. 1 is a logic circuit diagram of a full adder using conventional binary logic, Fig. 2 is a block diagram of the full adder of the present invention, Fig. 3 is an explanatory diagram of the operation of the full adder of the present invention, and Fig. 4 5 is a circuit diagram of a first embodiment of the full adder of the present invention, and FIG. 5 is a circuit diagram of a second embodiment of the full adder of the present invention. 11... Adder, 12, 13... Voltage comparator,
14...Reference voltage generation circuit, A, B, C _i ...Current input, _C0 ...Carry output, S...Sum output, _R1 ,
R ₂ , R ₃ ... Resistance, V _cc , _Va ... Voltage source, T ₁ to _{T 5}
...transistor, D ₁ , D ₂ ...diode.

Claims (1)

[Claims] 1. Three current inputs each having a binary state are input to a first resistor, are converted into a voltage signal having a four-value state, and the four-value voltage signal is subjected to a first comparison. The 4-value voltage signal is compared with the first reference voltage to obtain a carry current output and a voltage output, and the 4-value voltage signal is compared with the first reference voltage.
The comparator controls the carry voltage output of the first comparator to obtain a sum current output by comparing it with either the second or third reference voltage, and the carry voltage output of the first comparator is controlled to obtain a sum current output. A full adder characterized in that the current values of the sum current output and the sum current output are configured to be equal. 2 Three current inputs each having a binary state are respectively connected to the other end of a first resistor whose end is connected to a DC voltage source, and the other end of the resistor is connected to a first resistor whose collector is connected to a DC voltage source. The emitter of the first transistor is connected to the emitters of second and third transistors whose bases are connected to the same reference voltage source, and the first constant current source, and the emitter of the first transistor is connected to the first constant current source. A carry current output is obtained from the collector of the second transistor, and the collector of the third transistor is connected to a fourth transistor connected to a DC voltage source through a second resistor and grounded through a third resistor. The emitter of the fourth transistor connected to the base of the transistor is connected to the emitter of a fifth transistor whose collector is connected to a DC voltage source and whose base is connected to the connection point of the first resistor and the three current inputs. A full adder connected to a second constant current source and obtaining a sum current output from the collector of the fourth transistor. 3 The emitter of the first transistor is connected to the emitters of the second and third transistors and the first constant current source via the first diode, and the emitter of the fifth transistor is connected via the second diode. 3. The full adder according to claim 2, wherein the full adder is connected to the emitter of the fourth transistor and the second constant current source.