JPH01236747A - System for generating adaptive level deciding voltage - Google Patents

Abstract

PURPOSE:To perform level decision free from the variance in level of an input signal by providing a deciding voltage generating circuit to generate a discrimi nating voltage adapted to the level of the input signal. CONSTITUTION:A positive, negative, or zero deciding voltage having one or plural levels is generated as the deciding voltage in a deciding voltage generat ing circuit 25 based on the mean level of levels held in capacitors 15 and 18. A discriminating circuit 28 decides the level of the input signal based on digital signals from analog comparators 25 and 27 at the time of the leading edge of a regenerated clock signal. When this level is maximum or minimum, a sampling pulse is applied to a corresponding switch 14 or 17 to correct the level, and the difference from a reference voltage is held in capacitors 15 and 18. This reference voltage is selected from deciding voltages in accordance with the input signal level and allowed to pass an LPF 35 and follows up the variance of the center level. Since the voltage adapted to the level of the input signal is generated in this manner, level decision free from variance in level of the input signal is performed.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an adaptive level determination voltage generation system used for demodulating a digital signal that has passed through a transmission system in which the low frequency band is cut off.

(Prior Art) In recent years, there has been a demand for wireless transmission of digital signals. Single channel, especially for mobile radio, 4-
Carrier (Single Channel per Ca)
rrier ) method involves direct FM modulation with a binary digital signal, or a method in which the binary digital signal is passed through a low pass filter (hereinafter referred to as LPF) and then KFM modulated in order to narrow the transmission bandwidth. etc. have been adopted. Previous H
The method using a Gaussian filter as 6LPF' is GMS.
K (Gaussian Filter Manipul
Minimum 5hift Keying
) and is a modulation method with an extremely narrow band. Also, after converting a binary dinotal signal into a multivalued signal, for example, a four-valued signal, the LP
There is also a method of FM modulation through F.

As described above, any modulation method can be considered as a binary or multi-value frequency modulated wave. Since these frequency modulated waves contain DC components as is clear from their generation process, the DC component must be taken into consideration throughout the modulation process, transmission process, and demodulation process. However, transmission of this DC component is extremely difficult for the following two reasons.

(b) The transmitting frequency and receiving frequency depend on environmental conditions such as temperature.
The relative deviations appear as deviations in the DC potential upon demodulation.

In order to prevent this deviation in DC potential, a DC 1 cutoff circuit is often installed on the output side of the frequency discriminator of the receiver.

Naka) Frequency synthesizers have recently been used to generate carrier waves due to the need to switch the transmission frequency, but when applying FM modulation to this, the circuit becomes hidden and complicated if even the DC component is taken into consideration. .

For the above reasons, a system that does not transmit the DC component is desired, but if the DC component is not transmitted, the center voltage of the demodulated signal may fluctuate on the receiving side, which may cause an error in code determination. One possible way to completely solve this problem is to regenerate the DC component on the receiving side. FIG. 2 is a block diagram showing an example of a DC regeneration method, which uses a decision feedback method (for example, IEICE Technical Report 751:51).
) (1975-6-25) Institute of Electronics and Communication Engineers 1)-93-9
4). In Fig. 2A, 1 is an input terminal, 2 is a forward filter, 3 is an adder circuit, 4 is an identification circuit, 5 is a feedback filter,
6 is an output terminal. Assuming that the forward filter 2 is a high-pass filter with a frequency characteristic of A(jω), and the feedback filter 5 is a low-pass filter with a frequency characteristic of B(jω), the equation (1) is expressed between these filters. The following relationship holds true, and the low frequency components lost in the forward filter 2 are compensated by the output of the feedback filter 5.

A(jω) 1 B(jω)=1 ・・・・・・
(1) Here, if the forward filter 2 is a first-order high-pass filter, its frequency characteristic A(jω)Fi can be expressed by the equation (2).

However, S=jω, ω-2πf0, where fo is the transmission lock frequency and α is f. is the ratio of the cutoff frequency of the high-pass filter to .

Therefore, equation (3) can be obtained from equations (4) and (2).

That is, B(jω)=1-A(jω) The feedback filter 5 has the same cutoff frequency at as the forward filter 2.
- becomes a first-order low-frequency P-wave device.

Figure 3 shows the waveforms of each part of the block diagram shown in Figure 2, where (a) (b) is the waveform of the input signal applied to the input terminal l, (a) (b) The output waveform of the forward filter 2, (b) is the output waveform of the discrimination circuit 4, (b)
) is the output waveform of the feedback filter. Addition circuit 3
The output waveform of is a total summation of the output waveform of the forward filter 2 (a) and the output waveform of the feedback filter 5), but this is the same as the waveform of the input signal shown in (7) of (a). However, a signal having the same waveform as the input signal is inputted to the identification circuit 4, which is not affected by the characteristics of the front filter 2.

In other words, even if a high-frequency wave characteristic exists in the transmission process including the modulation process, and the DC component is lost, the DC component is regenerated and demodulated using the method described above, the center voltage of the signal is fixed, and the level is determined without error. be able to.

Also, (3) in Fig. 3(,) shows the center level of the output waveform (a) of the front filter 2 shown in Fig. 2, and the level judgment can be performed using the same judgment level voltage as this center level. For example, error-free determination can be made without being affected by fluctuations in the center level. 3(b) is the inverted version of the output waveform of the feedback filter 5, and (a)
It is the same as the waveform of the center voltage of the output of the front filter 2 shown in (4). Therefore, if the output of this feedback filter 5 is inverted and used as the determination level 1 voltage, error-free rail determination can be performed without being affected by center level fluctuations.

(Problem to be Solved by the Invention) However, in the above DC regeneration method, as shown in equation (1), it is necessary to always make the amplitude of the input signal equal to the output amplitude of the discrimination circuit 4. Considering that the amplitude normally varies, it is necessary to provide an automatic gain control (AGC) circuit to suppress amplitude variations. Moreover, since the AGC circuit described above must be able to linearly adjust the amplitude, it has the disadvantage that it cannot be applied to cases where the circuit is 'a', throat, or where the input signal is multi-valued. was there.

The present invention eliminates these drawbacks and easily changes the input signal! It is an object of the present invention to provide an adaptive level determination voltage generation circuit that responds to latent fluctuations and generates a determination voltage that follows fluctuations in the center voltage of an input signal.

(Means for Solving the Problems) The present invention is an adaptive level judgment voltage generation method that generates a judgment voltage as a reference for level judgment of digital input/picture symbol. A voltage holding circuit corresponding to the level value is selected to hold the difference between the input signal and the reference voltage, and an absolute direct average level of the voltage held in each voltage holding circuit is calculated based on the average level. i or a plurality of levels of positive and negative voltages and zero voltage are generated, one of which is selected according to the level value, passed through a low-pass filter to become the reference voltage, and held in the voltage holding circuit. This is an adaptive level judgment voltage generation method characterized in that a judgment voltage adapted to an input signal is generated based on the voltage being set and the reference voltage.

(Function) The present invention generates a reference voltage that follows fluctuations in the center level of a digital signal, and uses the digital signal and the reference voltage to generate a judgment voltage that adapts to fluctuations in the digital signal. , it is possible to stably perform level determination without malfunctioning even when the digital signal fluctuates.

(Embodiment) FIG. 1 is a block diagram showing an embodiment of the present invention.
1 is an input terminal, 12 is a high-pass filter as a forward filter, 13.16, 19.36 is an operational amplifier as a voltage follower, 14.17 is a switch, 15.18 is a capacitor,
22.33 is an inverting amplifier with a gain of 10, 23.24 is a resistor with the same resistance value for averaging, 25 is a judgment voltage generation circuit, 26.27, 311d analog controller or regulator, 28 is a discrimination circuit, 29 30 is a logic circuit, 30 is an output terminal, 32 is a clock regeneration/timing generation circuit, 34 is a discrimination circuit, quantization level selection circuit selects a quantization level opposite to the discrimination result of 28, and 35 is a high-frequency wave filter 12. This is a low-pass door filter as a rear filter with the same cut-off frequency.

GM of Bb-T≠0.25 to input terminal 1 - example
Assume that the SK signal is added. However, Bb is the bandwidth of the filter used during modulation, and T is the reciprocal of the bit rate of the digital signal. This GMSK signal has the characteristics shown in Figure 4(,), and each nT
(where n is an integer and T is the reciprocal of the bit rate), take three level values, L2 and L3, these,
, t, 2 and L3 are determined by the judgment voltage generation circuit 25,
This is executed by the analog controllers 26, 27 and the discrimination circuit 28 as follows.

First, the judgment voltage generation circuit 25 selects the highest level L of the input signal,
(the output level of the operational amplifier 16) and the center level L2 (the output level of the operational amplifier 36), generates a voltage LaJ- at the center of Ll and L2, and generates a voltage LaJ- at the center of the input signal L2.
A voltage L5 at the center of L2 and L3 is generated based on the lowest level Ls (output level of the operational amplifier 19).

FIG. 6 shows an embodiment of the judgment voltage generation circuit 25, and the terminals 25-1.25-5.25-9 are connected to the respective output sides of the operational amplifiers 16, 19.36 shown in FIG. and level L, , L3. The voltages of L2 are respectively input. Terminals 25-3 and 25-7 are connected to analog comparators 26 and 27 shown in FIG. 1, respectively, and judgment voltages La and Lb are output. Resistor 25-2.25-
4.25-6.25-8 both have the same resistance @R, so the judgment voltages La and Lb are the voltage at the center of levels L1 and L2, and the voltage at the center of levels L2 and Lb, respectively. . Therefore, the determination voltages La, Lb are based on the input signal levels L, , L2 . It will change according to L.

The analog converter 26 outputs a digital signal "1" when the input signal exceeds LafI as the Lat-judgment voltage, and a digital signal "0" when it does not exceed LafI.
i Output. On the other hand, the analog converter 22 uses the Lb as a determination voltage and outputs a digital signal "1" when the input signal exceeds Lb, and outputs a digital signal "0" when the input signal does not exceed Lb. The discrimination circuit 28 determines the level of the input signal based on the combination of the digital signals output from the analog commutators 26 and 27. L2 or Lb
Determine which of the following applies. For example, analog controller
If the output from regulator 26 is @0" and the output from regulator 27 is "1", the level of the input signal corresponds to L2. Based on the determination result of determination circuit 28, logic circuit 29 , when the input signal is Ll, it outputs "l", when it is Lb, it outputs 0'', and when it is L2, it determines whether it is "1" or '0'' from the past level transition and outputs it to the output terminal 30.

On the other hand, the voltage of level L2 output from the operational amplifier 36 is given to the analog comparator 3 as a judgment voltage, and when an input signal is applied, when the input signal exceeds L2, the digital signal "1"k is exceeded. If not, the full output signal @0# is output. The clock regeneration/timing generation circuit 32 receives the output of the analog comparator 31 and generates a regenerated clock signal as shown in FIG. A sampling/4' pulse 1-1 is generated delayed by a time t. As shown in FIG. 4, this sampling pulse is approximately synchronized with the portion where the input signal's three values of eye and tongue are concentrated. The discrimination circuit 28 detects that the input signal level increases based on the digital signals from the analog comparators 26 and 27 at the rising edge of the reproduced clock signal shown in FIG. 4(b). L2. It is determined which of Lb it corresponds to, and when it corresponds to Ll, the sampling pulse is added to switch 1411C, and when it corresponds to Lb, switch 17 is added.
In addition, when it corresponds to Lb, it is not applied to any of the switches 14 and 17. The reason why the sampling clock is delayed by the time t from the rising edge of the recovered clock signal as shown in FIG. 4(c) is to take into account the time required for the discrimination circuit 28 to perform the discrimination operation. It is. Therefore, the capacitor 15 holds the voltage difference between the level L1 of the input signal and the level L2 of the output from the operational amplifier 36, and the capacitor 18 holds the voltage difference between the level L3 of the input signal and the level L2. The voltages held by capacitors 15 and 18 are superimposed on the output voltage from operational amplifier 36 and input to operational amplifiers 16 and 19, respectively. The output of operational amplifier 16.19 is connected to inverting amplifier 22 and resistor 2.
3 and 24, and is applied to terminal a of the quantization level selection circuit 34, as well as to terminal A via the inverting amplifier 33. Therefore, on the input side of the quantization level selection circuit 34, the highest level of the input signal level,
A voltage that is the difference between the input signal level L1 and the lowest value L3 will be applied, but this voltage corresponds to the voltage difference between the input signal levels L1 and L2 and the difference between L2 and Lb, and the level fluctuation of the input signal fluctuates according to.

Based on the instruction from the discrimination circuit 28, the quantization level selection circuit 34 sets the contact A when the discrimination circuit 28 discriminates that the level of the input signal is above, and the contact a when the discrimination circuit 28 discriminates that the level of the input signal is Lb.
If it is determined to be 2, contact cf is selected and connected to the output side. Note that the reed point C is connected to ground. The output of the quantization level selection circuit 34 is applied to one end of the capacitor 15, 18, the decision value generation circuit 25, and the analog comparator 31 via a low-pass filter 35 and an operational amplifier 36't-. The above operation is shown in FIG. When the input signal shown in (7) of FIG. 5(a) is applied to the input terminal 1, the center level of (a) is output from the high frequency door amplifier 12.
Waveforms (a) and (a) that fluctuate as shown are output. On the other hand, the quantization level selection circuit 34 outputs 4 quantized voltages and zero voltages having 34 JtL, which is the difference between levels L1 and Lb (+1 voltage, ←), corresponding to the input signal level. , the waveform is as shown in FIG. 5(b). The output of the quantization level selection circuit 34 is input to a low-pass filter 35, and the output from the low-pass filter 35 is as shown in FIG.
A voltage having the waveform shown in (3) of b) is output. (3) of the output waveform (b) of the low-pass filter 35 coincides with the center level (a) of the output of the high-pass filter 12, regardless of fluctuations in the level of the input signal. Used as a reference voltage when generating voltage. As explained above, according to this embodiment, the determination voltage that follows the amplitude fluctuation and center level fluctuation of the input signal is generated, and the level is determined.
Accurate level determination can be performed without going through the GC circuit.

In this embodiment, the low frequency characteristics including the transmission system are the same as that of the high frequency door waver 12.
In this example, the high-pass filter 12 is omitted and the cut-off frequency a of the low-pass filter 35 is determined by
The same effect as that of this embodiment can be obtained even when is determined in accordance with the high-frequency p-wave characteristics of the transmission system.

Furthermore, this embodiment can be similarly applied to the case where the digital signal is multi-valued, such as binary or three-valued or more.

(Effects of the Invention) As explained in detail above, according to the present invention, in determining the level of a 7' digital signal whose low frequency components are cut off, a determination voltage is generated in accordance with the level of the input signal. Therefore, there is no need to use an AGC circuit, and it is possible to perform a level judgment without being affected by the level fluctuations of the input signal and the center level fluctuations.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a conventional level determination method, FIG. 3 is a waveform diagram of each part of the signals in FIG. 2, and FIG. 4 is an explanatory diagram of the timing signal in FIG. 1. M5 diagram is the first
FIG. 6 is a diagram of signal waveforms at various parts in the figure, and FIG. 6 is a diagram of a judgment voltage generation circuit. 11...Input terminal, 12...High-pass filter, 13°1
6.19.36...Operation amplifier, 14.17...Switch, 15.18...Capacitor, 23.33.-
・Inverting amplifier, 23.24...Resistor, 25...Judgment voltage generation circuit, 26, 27.31...Analog converter/4'lator, 28...Discrimination circuit, 29...Logic circuit , 30... Output terminal, 32... Clock regeneration/timing generation circuit, 34... Quantization level selection circuit,
35...Low pass filter. Patent applicant: Oki Electric Industry Co., Ltd. Saotsu 154 Kochi 2 12 Teyashi Figure 3 Figure 3 Reiden 7i Transferable Tomata Figure 6

Claims (1)

[Claims] 1. In an adaptive level judgment voltage generation method that generates a judgment voltage as a reference for level judgment of a digital input signal, the level value of the input signal is judged by a reproduced clock signal, and the level value corresponding to the level value is determined. Select a voltage holding circuit to hold the difference between the input signal and the reference voltage, calculate the average level of the absolute value of the voltage held in each voltage holding circuit, and calculate i or multiple levels based on the average level. A positive voltage, a negative voltage, and a zero voltage are generated, and one of them is selected according to the level value, and the voltage is passed through a low-pass filter to be the reference voltage, and the voltage held in the voltage holding circuit and the voltage are An adaptive level judgment voltage generation method characterized by generating a judgment voltage adapted to an input signal based on a reference voltage. 2. The adaptive level determination voltage generation system according to claim 1, further comprising a high-pass filter having the same cutoff frequency as the low-pass P-wave filter on the input side. 3. Claim 1, characterized in that the cut-off frequency of the low-pass filter is made to match the cut-off frequency of the high-pass filter characteristic of the transmission system.
The adaptive level determination voltage generation method described.