JPH01235872A - Fault simulation method for integrated circuit - Google Patents

Abstract

PURPOSE:To facilitate the fault simulation which reflects device structures and process defects by subjecting the fault samples extracted randomly at the frequency corresponding to the degeneration fault incidence probability of gate levels to simulation. CONSTITUTION:The probability of the incidence of the 0-degeneration fault of the output node of an inverter circuit is designated as P0 at the time of shorting of an n-type transistor. The probability of the incidence of the 1-degeneration fault is designated as P1 at the time of shorting of a p-type transistor. The 0-degeneration fault incidence probability of the output node in a 2-input NOR circuit is 2P0 in probability at which one of 2 pieces of the n-type transistors shorts and the 1-degeneration fault incidence probability is P1<2> in probability at which both the two p-type transistors short. Further, the 0-degeneration fault incidence probability of the output node in a 2-input NAND circuit is P0<2>, and the 1-degeneration fault incidence probability is 2P1. The faults are grouped in order of the magnitudes of the fault incidence probabilities calculated in such a manner. The faults are extracted at the frequencies corresponding to said fault incidence probability by each of the groups at the time of sampling the faults randomly.

Description

[Detailed description of the invention] [Purpose of the invention] (Industrial application field) This invention relates to fault simulation of integrated circuits.

(Prior art) A fault model for fault simulation and its
A stuck-at fault of the input/output bin of the gate is used, but this fault simulation was originally performed using TTL on the printed circuit board.
This is because the target is a logic circuit obtained by arranging and wiring the gates of . In this case, the stuck-at fault of the input/output pin of the gate corresponds well to the physical entity. However, even for entities that are physically different from printed circuit boards, such as integrated circuits, the same fault model and fault simulator are often used because the logic circuits are the same.

On the other hand, there are some failures that cannot be expressed as stuck-at faults, such as open transistor failures in CMO8 circuits, and although failures in integrated circuits are caused by defects in the manufacturing process, failure models are based on the structure of the device. I2
It has also begun to be recognized that it is strange that there is no tolerance for defects in the manufacturing process.

Furthermore, since the time required for fault simulation depends on the square to the third power of the circuit scale, it has become impractical to perform fault simulation for all stuck-at faults as the scale of one circuit increases.

The main purpose of fault simulation is to find the fault coverage rate for a given test pattern, but by randomly extracting sample faults from all stuck-at faults and performing fault simulation only on these sample faults, There are also known methods for estimating fault coverage using a realistic calculation time.

(Problems to be Solved by the Invention) The purpose of the present invention is to incorporate device and process dependence, which were lacking in conventional failure simulation, and to obtain an estimated value of failure coverage in a realistic calculation time.

[Structure of the invention]

(Means for Solving the Problems) This invention focuses on the fact that the probability of occurrence of a stuck-at fault at an input/output node of a gate differs depending on the structure of the device constituting the gate, and calculates this probability of occurrence from the circuit structure. By extracting sample faults based on this, the fault simulation is made device and process dependent.

(Function) For example, a stuck-at fault at the output node of a gate is calculated using the number of transistors between the output node and the ground line and the yield, which is an index for process defects. Similarly, the 1-stuck-at-home fault at the output node of the gate is calculated using the number and yield of transistors between the output node and the power supply line. The number of transistors between the output node and the ground line or power supply line can be calculated from the circuit structure for each gate in the logic library. For the yield rate, the value measured for each production line is used. After determining the probability of occurrence of all stuck-at faults in this manner, sampling of faults is performed at a frequency corresponding to the probability of occurrence, and a fault simulation is performed on the obtained fault samples.

(Embodiment) FIG. 1 shows a flowchart of the present invention for failure simulation of an integrated circuit. FIG. 3 shows an example of a method for calculating the probability of failure occurrence. In the inverter circuit of FIG. 3(a), a stuck-at fault at the output node occurs when the N-type transistor is short-circuited, and the probability of this is P. shall be. Similarly, a 1-stuck at output node fault occurs when a P-type transistor is short-circuited, and the probability thereof is defined as P. PotPl is calculated from the yield measured for each production line in Figure 2.
It can be estimated using the following relationship. Figure 3(b)
is a two-person powered NOR circuit, and the probability of occurrence of a 0-stuck-at fault at its output node is 2P, which is the probability that at least one of the two N-type transistors will be shorted, and 1
- The probability of occurrence of a stuck-at fault is P1', which is the probability that two P-type transistors will be shorted together. Figure 3(c)
is a two-person NAND circuit, but its output node 〇-
The degeneracy probability is P. ', 1 - the degeneracy probability becomes 2P1. The calculations for other gates are similar.

Faults are divided into groups in the order of the magnitude of the probability of failure occurrence calculated as described above, and when randomly sampling failures, each group is extracted at a frequency according to the probability of failure occurrence. For example, the frequency of extraction from a group with a probability of 2Po is P.

This is twice the case for a group with a probability of .

〔Effect of the invention〕

By calculating the probability of gate-level stuck-at fault occurrence using circuit connection data, logic libraries, and production line yield data, and performing simulations on randomly selected fault samples at a frequency corresponding to the probability of occurrence. , failure simulation of integrated circuits that reflects device structure and process defects becomes possible in a realistic calculation time.

[Brief explanation of the drawing]

Fig. 1 is a diagram showing the flow of the present invention for failure simulation of integrated circuits, Fig. 2 is a diagram showing the relationship between the failure probability of an inverter output node and the yield, and Fig. 3 is a diagram showing the relationship between the failure occurrence probability and yield of an inverter output node.
It is a diagram showing the failure probability of the O5 inverter circuit and output node, the failure probability of the 0MO3 two-man NOR circuit and the output node, and the failure probability of the CMO5 two-man NAND circuit and the output node. Figure 1 Figure 2 Figure 8

Claims (3)

[Claims] (1) An integrated circuit characterized in that the probability of occurrence of a gate-level stuck-at fault is calculated according to the structure of the devices constituting the integrated circuit, and a fault simulation is performed on randomly selected fault samples according to the probability of occurrence. failure simulation method. 2. The integrated circuit failure simulation method according to claim 1, wherein the probability of failure occurrence is calculated based on defects in the manufacturing process of the integrated circuit by a specific device. (3) The integrated circuit fault simulation method according to claim 1, characterized in that a fixed number of faults are randomly extracted according to the probability of occurrence for each Maxel or functional block.