JPH01235418A - Dc offset removing circuit - Google Patents
Dc offset removing circuitInfo
- Publication number
- JPH01235418A JPH01235418A JP6267088A JP6267088A JPH01235418A JP H01235418 A JPH01235418 A JP H01235418A JP 6267088 A JP6267088 A JP 6267088A JP 6267088 A JP6267088 A JP 6267088A JP H01235418 A JPH01235418 A JP H01235418A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- capacitor
- offset
- high frequency
- lsi
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000003990 capacitor Substances 0.000 claims abstract description 12
- 230000004069 differentiation Effects 0.000 claims abstract description 7
- 230000000694 effects Effects 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 6
- 238000007796 conventional method Methods 0.000 description 2
- 238000005070 sampling Methods 0.000 description 2
Abstract
Description
【発明の詳細な説明】
〈産業上の利用分野〉
本発明は、モデム等の通信システムで使用され〈従来の
技術〉
アナログ・フロント・エンド・プロセッサ受侶ヤパシタ
・フィルタ、ｆｌ−数１００ＫＨｚ Ｋてサンプリング
）、３はＡＡＦ （Ａｎｔｉ Ａ１１ａｓＦｉｌｔｅ
ｒ、ＬＰＦで発生した周波数ｆ８のノイズを除去するた
めのアナログＬＰＦ ）、４はＡＧＣ（Ａｕｔｏｍａｔ
ｉｃ Ｇａ１ｎ Ｃｏｎｔｒｏｌ ）回路、５はＡ／Ｄ
コンバータ、６はディジタル出力である。DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention is used in communication systems such as modems. <Prior Art> sampling), 3 is AAF (Anti A11asFilter
r, an analog LPF for removing the noise of frequency f8 generated in the LPF), 4 is an AGC (Automatic
ic Galn Control) circuit, 5 is A/D
Converter 6 is a digital output.
ＡＧＣ入力へのＤＣオフセット除去回路として外付けＣ
Ｒ微分回路７が付加されている。ＡＧＣ回路４はアナロ
グ入力を増幅しＡ／Ｄコンバータ５への入力とするＤＣ
アンプであり、ＡＧＣ回路４への入力はＤＣオフセット
を極度に抑える必要があるため、上記の様に、外付けＣ
Ｒ微分回路７が前置される。なお、ｆ２はサンプリング
周波数であり、音声帯域では通常７〜１ＯＫＨｚである
。External C as DC offset removal circuit to AGC input
An R differentiation circuit 7 is added. The AGC circuit 4 is a DC converter that amplifies the analog input and inputs it to the A/D converter 5.
Since it is an amplifier and the input to the AGC circuit 4 needs to suppress the DC offset to the extreme, an external C
An R differentiation circuit 7 is placed in front. Note that f2 is a sampling frequency, which is usually 7 to 1 OKHz in the audio band.
〈発明が解決しようとする課題〉
従来方式では、第４図に示す観測点■に於けるゲイン−
周波数特性に於いて高周波領域でのゲインが増加し、特
性が悪化してふ・す、そのためにＬＳＩ内部で発生する
クロック等の高周波ノイズが除去できないという問題点
かあまた。<Problem to be solved by the invention> In the conventional method, the gain at the observation point ■ shown in Fig. 4 -
In terms of frequency characteristics, the gain increases in the high frequency region, causing the characteristics to deteriorate, which often causes problems such as the inability to remove high frequency noise such as clocks generated inside the LSI.
本発明は上記問題点を解決することを目的としているも
のである。The present invention aims to solve the above problems.
く課題を解決するための手段〉
通常ＯＣＲ微分回路に並列に小容量のコンデンサを付加
してＤＣオフセット除去回路を構成する。Means for Solving the Problem> Normally, a DC offset removal circuit is constructed by adding a small capacitance capacitor in parallel to the OCR differentiation circuit.
〈作 用〉
上記構成とすることにより、ＬＳＩ内部からの高周波ノ
イズをカットすることができ、ＤＣオフセットを低減す
ることができる。<Function> With the above configuration, high frequency noise from inside the LSI can be cut and DC offset can be reduced.
〈実施例〉
第１図は本発明に係るＤＣオフセット除去回路の回路構
成図である。通常ＯＣＲ微分回路１１に並列に小容量の
コンデンサ１２が付加されている１、コンデンサ１２の
容量値Ｃ′は微分回路１１を構成するコンデンサの容量
値Ｃの約琵程度である。<Embodiment> FIG. 1 is a circuit configuration diagram of a DC offset removal circuit according to the present invention. Usually, a capacitor 12 of small capacity is added in parallel to the OCR differentiating circuit 11. The capacitance value C' of the capacitor 12 is about 1,000 times the capacitance value C of the capacitor constituting the differentiating circuit 11.
第２図は観測点■に於けるゲイン−周波数特注を両者で
比較しｔものである。従来方式では高層波頭域でのゲイ
ンが増加し、特性が悪化しており、そのためにＬＳＩ内
部で発生するクロック等の高周波ノイズが除去できない
。一方、本発明ではコンデンサ１２によって高域除去効
果をもたせることにより、高周波ノイズを低減している
。Figure 2 compares the gain-frequency custom orders at observation point (2). In the conventional method, the gain increases in the high wave front region and the characteristics deteriorate, and therefore high frequency noise such as clocks generated inside the LSI cannot be removed. On the other hand, in the present invention, high frequency noise is reduced by providing a high frequency removal effect using the capacitor 12.
第３図は本回路の最終目標である％出力におけるＤＣオ
フセットの特性を示したものであり、高域ノイズをカプ
トすることによってＤＣオフセットも大きく低減してい
ることがわかる。FIG. 3 shows the characteristics of DC offset at % output, which is the ultimate goal of this circuit, and it can be seen that the DC offset is greatly reduced by cutting out high-frequency noise.
〈発明の効果〉
以上のように本発明によれば、ＬＳＩ内部からの高周波
ノイズをカットすることができ、ＤＣオフセットを大き
く低減することができるものである。<Effects of the Invention> As described above, according to the present invention, high frequency noise from inside an LSI can be cut, and DC offset can be significantly reduced.
第１図は本発明に係るＤＣオフセット除去回路の回路構
成図、第２図は第４図に於ける観測点［株］に於けるゲ
イン−周波数特性を示す図、第３図はへ出力における設
定ゲイン−ＤＣオフセット特性を示す図、第４図はアナ
ログ・フロント・エンド・プロセッサ受信側の従来回路
を示すプロ・ツク図である。
符号の説明
１１：通常ＯＣＲ微分回路、１２：小容量のコンデンサ
。Fig. 1 is a circuit configuration diagram of the DC offset removal circuit according to the present invention, Fig. 2 is a diagram showing the gain-frequency characteristics at the observation point [stock] in Fig. 4, and Fig. 3 is a diagram showing the gain-frequency characteristics at the output to FIG. 4 is a diagram showing a set gain-DC offset characteristic, and is a block diagram showing a conventional circuit on the receiving side of an analog front end processor. Explanation of symbols 11: Normal OCR differentiation circuit, 12: Small capacitor.
Claims (1)
ロント・エンド・プロセッサのＤＣオフセット除去回路
に於いて、通常のＣＲ微分回路に並列に小容量のコンデ
ンサを付加したことを特徴とするＤＣオフセット除去回
路。1. A DC offset removal circuit for analog front end processors used in communication systems such as modems, which is characterized by adding a small-capacity capacitor in parallel to a normal CR differentiation circuit. circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6267088A JPH01235418A (en) | 1988-03-15 | 1988-03-15 | Dc offset removing circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6267088A JPH01235418A (en) | 1988-03-15 | 1988-03-15 | Dc offset removing circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01235418A true JPH01235418A (en) | 1989-09-20 |
Family
ID=13206959
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6267088A Pending JPH01235418A (en) | 1988-03-15 | 1988-03-15 | Dc offset removing circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01235418A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH048007A (en) * | 1990-04-26 | 1992-01-13 | Oki Electric Ind Co Ltd | Automatic gain control circuit |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS507445A (en) * | 1973-05-18 | 1975-01-25 | ||
| JPS5333029A (en) * | 1976-09-09 | 1978-03-28 | Nec Corp | Cut-off frequency variable filter |
-
1988
- 1988-03-15 JP JP6267088A patent/JPH01235418A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS507445A (en) * | 1973-05-18 | 1975-01-25 | ||
| JPS5333029A (en) * | 1976-09-09 | 1978-03-28 | Nec Corp | Cut-off frequency variable filter |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH048007A (en) * | 1990-04-26 | 1992-01-13 | Oki Electric Ind Co Ltd | Automatic gain control circuit |
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