JPH01235244A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH01235244A
JPH01235244A JP6147888A JP6147888A JPH01235244A JP H01235244 A JPH01235244 A JP H01235244A JP 6147888 A JP6147888 A JP 6147888A JP 6147888 A JP6147888 A JP 6147888A JP H01235244 A JPH01235244 A JP H01235244A
Authority
JP
Japan
Prior art keywords
contact hole
sample
current image
aperture
opening
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6147888A
Other languages
Japanese (ja)
Inventor
Koichi Hashimoto
浩一 橋本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP6147888A priority Critical patent/JPH01235244A/en
Publication of JPH01235244A publication Critical patent/JPH01235244A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To enable conditions of a fine aperture formed in an insulating film to be inspected non-destructively, by forming a second aperture simultaneously with formation of a first aperture such that the second aperture has substantially the same configurations as those of the first one and reaches a semiconductor substrate or a second conducting layer electrically connected with the semiconductor substrate, and scanning the surface of the second aperture with an electron beam for observing a current image of the sample. CONSTITUTION:When an N-channel MOS transistor is to be inspected, a dummy MOS transistor having the same configurations as those of said N-channel MOS transistor under test is provided on an N-type semiconductor substrate 1 beside said transistor to be tested, through the same processes as those of said transistor to be tested. A proper contact hole 12 and a monitoring contact hole 13 are formed simultaneously so as to have the same configurations. When a current image of the sample is observed by means of a conventional SEM, a desirable current image of the sample can be obtained in the monitoring contact hole 13.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置の製造方法に関し、特に半導体装置
の製造工程において絶縁膜に形成された微細窓の、形成
状at検査可能とする製造方法に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for manufacturing a semiconductor device that enables inspection of the formation state of fine windows formed in an insulating film in the manufacturing process of a semiconductor device. Regarding.

近年、半導体装置のうち特に半導体集積回路の規模は急
速に増大しており、集積度の同上が強く望まれている。
In recent years, the scale of semiconductor devices, especially semiconductor integrated circuits, has been rapidly increasing, and higher integration is strongly desired.

そのためフォトリソグラフィーを中心とする微細加工技
術のm&を的な開発が行われている。そして、半導体装
置の最小部分の寸法が1μm以下のものも実用化される
に至っている。
For this reason, microfabrication techniques, mainly photolithography, are being developed. Semiconductor devices whose smallest part has a dimension of 1 μm or less have also come into practical use.

これに伴って、製造工程における加工状態の検査は、従
来の光学顕微鏡にかわって、より高分解能のSEM(S
canning Electron Microsco
pe )などの電子顕微鏡を用いないと困−な状態にな
ってきた・ 〔従来の技術〕 従来、半導体装置の製造工程における加工状態の検査に
は、SEMの2久電子儂観察による方法が広く用いられ
ている。しかし、SEMで絶縁膜に形成したコンタクト
ホールなどの開口部の形状を観察しようとすると、絶g
&膜が電子によってマイナスに帯電して、いわゆるチャ
ージアップを生じ、このため、コンタクトホールなどの
開口部の内部からの2次電子の放出が妨げられ、その結
果良好な2次電子像が得られなくなり、その形状検査が
困峻になるという問題がある。そこで、このチャージア
ップを少くするよう、従来は、SEM観察すべき半導体
ウェハを入射−久電子線に対して傾斜させたり、−久電
子線の加速エネルギーを低くするなどの方法がとられて
いる。
Along with this, the inspection of processing conditions during the manufacturing process has been replaced by a higher resolution SEM (SEM), replacing the conventional optical microscope.
canning Electron Microsco
[Conventional technology] Conventionally, the method of inspecting the processing state in the manufacturing process of semiconductor devices has been widely used by SEM (secondary electron observation). It is used. However, when trying to observe the shape of an opening such as a contact hole formed in an insulating film using a SEM, the
& The film is negatively charged by electrons, resulting in so-called charge-up, which prevents the emission of secondary electrons from inside openings such as contact holes, and as a result, good secondary electron images cannot be obtained. There is a problem that the shape is difficult to inspect. Therefore, conventional methods have been used to reduce this charge-up, such as tilting the semiconductor wafer to be observed with the SEM with respect to the incident electron beam, or lowering the acceleration energy of the electron beam. .

半導体ウェハーを傾斜させる方法では、コンタクトホー
ルの微細化がすすみ、その開口部のさしわたしの寸法に
対する深さの比、即ちアスペクト比が大きくなってくる
と、半導体ウェハを傾斜させると、その底部が観察でき
なくなるという問題点があり、又、−久電子のエネルギ
ーを低くする方法では、このエネルギーを低くすると、
半導体ウェハから放出される2次電子の絶対鎗が減少し
て観察が次第に困難になるのと、分解能が低下するので
、おのずと限界があった。
In the method of tilting a semiconductor wafer, as contact holes become finer and the ratio of the depth to the width of the opening, that is, the aspect ratio, increases, tilting the semiconductor wafer causes the bottom of the contact hole to become smaller. There is a problem that it becomes impossible to observe, and in addition, in the method of lowering the energy of -kudenshi, when this energy is lowered,
There was a natural limit because the absolute number of secondary electrons emitted from semiconductor wafers decreased, making observation gradually more difficult, and the resolution decreased.

’72ペクト比の大きいコンタクトホールの形状を検査
する方法としては、半導体ウエノ・をヘキ関するなどし
て破壊して、そのウエノS断面をSEMで観察するとい
う方法がある。しかし、この方法では、ヘキ開などの工
程が不可欠で検査に時間がかかる上、破壊検査であるの
で半導体ウエノ・のロスを生ずることから、製造の量産
ラインにおいては、現実には用いることができない。
A method of inspecting the shape of a contact hole with a large aspect ratio is to destroy a semiconductor wafer by cutting it, etc., and observe the cross section of the wafer with an SEM. However, this method requires processes such as cleavage, which takes time, and since it is a destructive test, it causes loss of semiconductor wafer, so it cannot be used in reality on mass production lines. .

そこで、量産ラインにおいて、コンタクトホールなどの
形成状態を検査する方法として、SEMを用いて検査す
べき半導体ウエノ1に、加速エネルギーの低い電子線を
走査して照射し、電子線を照射し九部分から半導体ウニ
/S中を流れる電流を検出し、試料電fi儂を得、この
試料’を流偉を観察する方法が提案されている。
Therefore, in a mass production line, as a method of inspecting the formation state of contact holes, etc., the semiconductor wafer 1 to be inspected is scanned and irradiated with an electron beam of low acceleration energy using an SEM, and nine parts are irradiated with the electron beam. A method has been proposed in which the current flowing through the semiconductor U/S is detected, the sample electric current is obtained, and the flow of this sample is observed.

〔発明が屏決しようとする問題点〕[Problems that the invention attempts to resolve]

前述のSEMによって試料電流像を観察することによ、
9n型もしくはp型半導体基板や、p型半導体基板上に
形成されたn型半導体領域の表面、あるいは、これらと
電気的に接続する電極部に達するようなコンタクトホー
ルなどの開口部の形状の検査はできるのであるが、検査
すべき開口部が、n!tl半導体領域に囲まれたp型半
導体領域の表面、もしくは、このp型半導体領域に電気
的に接続する導電層上に形成されていると、その検査が
できないという問題点があった。
By observing the sample current image using the SEM described above,
9 Inspection of the shape of openings such as contact holes that reach the surfaces of n-type or p-type semiconductor substrates, n-type semiconductor regions formed on p-type semiconductor substrates, or electrodes that are electrically connected to these. However, the opening to be inspected is n! If it is formed on the surface of a p-type semiconductor region surrounded by a tl semiconductor region or on a conductive layer electrically connected to this p-type semiconductor region, there is a problem that it cannot be inspected.

第2図は、この試料電流像観察の問題点を説明する図で
、この図は、絶縁膜30にn基板21に形成されたn+
拡散層25に達するコンタクトホール34.n基板21
上のpウェハ22内に形成されたp+拡散層23に達す
るコンタクトホール32゜および前記pウェル22内に
形成されたnチャネルMO8型トランジスタのゲート電
極31をはさんで開口され九、ソース自ドレイン領域と
なるベキn+拡散l−24に達するコンタクトホール3
3をそれぞれ開口したあとで、SEMによって、試料電
流像観察し、前記コンタクトホールの形成状態の検査を
する工程を模式的に示したものである。
FIG. 2 is a diagram illustrating the problem of observing this sample current image. This diagram shows the n+
Contact hole 34 reaching diffusion layer 25. n-substrate 21
A contact hole 32° reaching the p+ diffusion layer 23 formed in the upper p-wafer 22 and a gate electrode 31 of an n-channel MO8 type transistor formed in the p-well 22 are opened. Contact hole 3 reaching the power n+diffusion l-24 which becomes the region
3 is a diagram schematically showing a process of observing a current image of the sample using an SEM and inspecting the formation state of the contact hole after opening each of the contact holes.

コレラコンタクトホールのうち、n+拡散層25に遅す
るフンタクトホール34については、ここに電子線26
が照射されると、注入された電子27はn型基板21の
中を拡散して、外部に流れ出ることができる。このn型
基板21から流れ出る電流を増幅器28で増幅し、SE
Mの画像部29で映儂化することによって、コンタクト
ホール34の試料電流像を得ることができ、その形成状
態の検査をすることができる。
Among the cholera contact holes, regarding the contact hole 34 that is delayed to the n+ diffusion layer 25, here is the electron beam 26
When irradiated, the injected electrons 27 can diffuse within the n-type substrate 21 and flow out to the outside. The current flowing out from this n-type substrate 21 is amplified by an amplifier 28, and SE
By imaging in the image section 29 of M, a sample current image of the contact hole 34 can be obtained, and its formation state can be inspected.

ところが、pウェル22上に形成されたコンタクトホー
ル32および33の場合は、電子線26によりて注入さ
れた電子27は、pウェル22内には拡散するものの、
逆バイアス状態となる、pウェル22とn型半導体基板
21との界面のpn接合を乗シ越えてpウェル22から
基板21の方向に流れ出すことができず、結果として外
部に電流が流れない。このため、コンタクトホール32
゜33の試料電流像観察ができず、この方法によってコ
ンタクトホール32.33の検査をすることはできない
。又、通常、コンタクトホール34とコンタクトホール
33,32の形状−サイズは異るので、単純にコンタク
トホール34の試料電流像カラコンタクトホール33,
32の形成状態を頌推するというのも困難であった。
However, in the case of the contact holes 32 and 33 formed on the p-well 22, although the electrons 27 injected by the electron beam 26 diffuse into the p-well 22,
The current cannot flow from the p-well 22 toward the substrate 21 across the p-n junction at the interface between the p-well 22 and the n-type semiconductor substrate 21, which is in a reverse bias state, and as a result, no current flows to the outside. For this reason, the contact hole 32
It is not possible to observe the sample current image at .degree. 33, and the contact holes 32 and 33 cannot be inspected by this method. Also, since the contact hole 34 and the contact holes 33 and 32 are usually different in shape and size, the sample current image of the contact hole 34 is simply the color contact hole 33,
It was also difficult to examine the state of formation of 32.

本発明は、かかろ従来の方法の欠点を解消すべく創作さ
れたもので、絶縁膜に開口し九微細な開口部の形成状態
を、非破壊で検査することを可能にする半導体装置の製
造方法を提供すること金その目的とする。
The present invention was created in order to overcome the shortcomings of conventional methods, and is a method for manufacturing a semiconductor device that makes it possible to non-destructively inspect the formation of nine minute openings in an insulating film. Its purpose is to provide money.

〔間IIt−解決するための手段〕[Interval IIt-Means for solving]

この目的は、 半導体上に形成された、n型半導体領域に囲まれたp型
半導体領域の表面、もしくは、該p型半導体領域と電気
的に接続する纂1の導電層の表面をおおうように絶縁膜
を形成する工程と、咳絶縁膜に前記p型半導体領域もし
くは前記第1の導電層に達する第1の開口部を形成する
工程とを有する半導体装置の製造方法において、 前記第1の開口部の形成と同時に、その形状が前記第1
の開口部と路間−であり、かつ、前把手2の開口部表面
に電子線を走査して照射し、前記第2の開口部の試料電
流像を観察するようにすることによって達成される。
The purpose of this is to cover the surface of a p-type semiconductor region formed on a semiconductor and surrounded by an n-type semiconductor region, or the surface of a conductive layer in series 1 that is electrically connected to the p-type semiconductor region. A method for manufacturing a semiconductor device comprising the steps of forming an insulating film and forming a first opening in the insulating film that reaches the p-type semiconductor region or the first conductive layer, wherein the first opening At the same time as forming the part, its shape changes to the first part.
This is achieved by scanning and irradiating the surface of the opening of the front handle 2 with an electron beam and observing the sample current image of the second opening. .

〔作 用〕[For production]

本発明の半導体装置の製造方法においては、試料電流像
による検査が可能で、かつ、その形状が、検査対象であ
る開口部と、その形状が路間−な形成状態モニター用の
開口部が前記検査対象の開口部と同時に形成されるため
、この形成状態モニター用開口部で試料電流観察するこ
とにより、検査の対象とすべき開口部の形成状態を矧る
ことができる。
In the method for manufacturing a semiconductor device of the present invention, inspection can be performed using a sample current image, and the shape of the opening to be inspected and the opening for monitoring the formation state whose shape is between the two are as described above. Since it is formed at the same time as the opening to be inspected, the formation state of the opening to be inspected can be determined by observing the sample current through this formation state monitoring opening.

〔実施例〕〔Example〕

第1図は本発明の一実施例を説明する図で、n型半導体
基板1上のpウェル2に形成されたnチャネルMO8m
トランジスタのソースのドレイン領域となるべきn+拡
散層3に達するコンタクトホール12の形成状態を検査
する場合を示したものである。
FIG. 1 is a diagram illustrating one embodiment of the present invention, in which an n-channel MO8m formed in a p-well 2 on an n-type semiconductor substrate 1 is shown.
This figure shows a case where the formation state of a contact hole 12 reaching an n+ diffusion layer 3 which is to become a source/drain region of a transistor is inspected.

先に説明した、従来の方法と異る点は、検査対象である
nチャネルMO8型トランジスタのすぐ横のnW半導体
基21上に、同一形状の検査用のダミーMO8)ランジ
スタ構造を、me n f apネルMO8ffi)ラ
ンジスタの作成と全く同一の工程を経て形成したことで
ある。本来のコンタクトホール12とモニター用コンタ
クトホール13Fi、同一形状で同時に形成した。この
あと、従来と同様に、SEMを用いて試料電流像を観察
し九ところ、モニター用コンタクトホール13では良好
な試料電流像が得られ、これによって、このモニター用
コンタクトホール13と同時に形成された実際の半導体
素子の構成要素になるべきコンタクトホール12の形成
状態を知ることができた。なお、本実施例では、モニタ
ー用コンタクトホール13の形成にあたり、直接使用し
ないダミーの電極14をも形成するようにしたが、これ
は、絶縁膜10の形状やその絶縁膜にエツチングされる
コンタクトホール12の形状が、その下地となる部分の
表面形状によって左右されるため、この下地の表面形状
のちがいの影響を低減するためのものである。
The difference from the conventional method described above is that a dummy MO8 transistor structure of the same shape for inspection is placed on the nW semiconductor substrate 21 immediately next to the n-channel MO8 transistor to be inspected. This is because it was formed through the exact same process as that used to create the transistor (apnel MO8ffi). The original contact hole 12 and the monitor contact hole 13Fi have the same shape and are formed at the same time. After this, the sample current image was observed using a SEM in the same way as before, and a good sample current image was obtained in the monitor contact hole 13, which indicated that the monitor contact hole 13 was formed at the same time. It was possible to know the formation state of contact hole 12, which should become a component of an actual semiconductor device. In this embodiment, when forming the monitoring contact hole 13, a dummy electrode 14 that is not directly used is also formed, but this may depend on the shape of the insulating film 10 and the contact hole etched into the insulating film. Since the shape of 12 depends on the surface shape of the underlying portion, this purpose is to reduce the influence of differences in the surface shape of the underlying portion.

なお、このような、モニター用コンタクトホール13は
、検査の対象とすべき開口部の樵幾ごとに、それぞれ半
導体ウェハ上に適宜配置すればよく、これを設置するこ
とによる半導体ウェハの利用効率の低下は、実質的には
問題とならない。
Incidentally, such monitoring contact holes 13 may be appropriately placed on the semiconductor wafer for each number of openings to be inspected, and by installing them, the utilization efficiency of the semiconductor wafer can be improved. The drop is practically not a problem.

又、本実施例中のfi4p 、p−)nとしても、本発
明の効果にかわりはなかった。
Furthermore, even if fi4p and p-)n were used in this example, the effects of the present invention remained the same.

この実施例ではコンタクトホールについて示したが、配
線層間のいわゆるピアホールの場合も、同様にモニター
用ピアホールを構成することができる。即ち、接合を介
してのみ半導体基板に接続されている配線層上に形成さ
れるピアホールの形成状態を知りたい場合は、N型拡散
層に接続し、周辺も含めてほぼ同一の形状を有する配線
層を用意しておき、この上にほぼ同一の形状に窓を開け
て、この窓を試料電流像観察すれば良い。
In this embodiment, a contact hole is shown, but a so-called peer hole between wiring layers can be similarly configured as a monitoring peer hole. In other words, if you want to know the formation state of a peer hole formed on a wiring layer that is connected to a semiconductor substrate only through a bond, check the formation status of a peer hole that is connected to an N-type diffusion layer and has almost the same shape including the periphery. It is sufficient to prepare a layer, open a window in almost the same shape on the layer, and observe the current image of the sample through this window.

また、本発明の応用は、これらの実施例にとどまらず、
製造する素子のS類や用いる半導体の導電型を問わず適
用可能なことは明らかである。
Moreover, the application of the present invention is not limited to these examples,
It is clear that the present invention is applicable regardless of the type S of the device to be manufactured or the conductivity type of the semiconductor used.

〔発明の効果〕〔Effect of the invention〕

以上のように本発明によれば、絶縁膜に形成された縦横
比の大きい微細な開口部の形成状態を非破壊で、その開
口部の形態によらず検査することができ、短時間で製造
工程にフィードバックすることができるため、半導体装
置の製造のスループットおよび製造歩留まりが向上する
という効果がある。
As described above, according to the present invention, it is possible to non-destructively inspect the formation state of minute openings with a large aspect ratio formed in an insulating film, regardless of the shape of the openings, and the manufacturing process can be completed in a short time. Since feedback can be provided to the process, there is an effect that the throughput and manufacturing yield of semiconductor device manufacturing are improved.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は、従来の試料電流像観察の問題点を説明する図
、第2図は本発明の一実施例を説明する因である。 図において、 1.21はn型半導体基板、 2.22はpウェル、 3.24.25はn十拡散層、 4は素子分離領域、 10.30は絶縁膜、 11.31はゲート電極、 12.32,33.34はコンタクトホール、13はモ
ニター用コンタクトホール、 14はダミー電極、 26は電子線、 27は電子、 28は増幅器、 29はS EMtiijm部、 である。 茅l 図 手続補正書(方式) 63.6.07 昭和 年 月 日 昭和63年特許願第061478号 2 発明の名称 半導体装置の製造方法 3 補正をする者 事件との関係  特許出願人 住所 神奈川県用崎市中原区上小田中1015番地名称
 (522)富士通株式会社 代表者山本卓眞 4 代理人 郵便番号 211 5 補正により増加する発明の数   なしく1)本願
明細書の第1頁第20行に、「3、発明の詳細な説明」 を追加する。
FIG. 1 is a diagram illustrating problems in conventional sample current image observation, and FIG. 2 is a diagram illustrating an embodiment of the present invention. In the figure, 1.21 is an n-type semiconductor substrate, 2.22 is a p-well, 3.24.25 is an n-diffusion layer, 4 is an element isolation region, 10.30 is an insulating film, 11.31 is a gate electrode, 12, 32, 33, and 34 are contact holes, 13 is a contact hole for monitoring, 14 is a dummy electrode, 26 is an electron beam, 27 is an electron, 28 is an amplifier, and 29 is a SEM unit.茅l Drawing procedure amendment (method) 63.6.07 Showa year, month, day, 1986 Patent Application No. 061478 2 Title of invention Method for manufacturing semiconductor devices 3 Relationship with the case of the person making the amendment Patent applicant address Kanagawa Prefecture 1015 Kamiodanaka, Nakahara-ku, Yozaki-shi Name (522) Fujitsu Limited Representative Takuma Yamamoto 4 Agent Postal code 211 5 Number of inventions increased by amendment None 1) In line 20 of page 1 of the specification of the present application , "3. Detailed description of the invention" is added.

Claims (1)

【特許請求の範囲】  半導体上に形成名れた、n型半導体領域に囲まれたp
型半導体領域の表面、もしくは、該p型半導体領域と電
気的に接続する第1の導電層の表面をおおうように絶縁
膜を形成する工程と、該絶縁膜に前記p型半導体領域も
しくは前記第1の導電層に達する第1の開口部を形成す
る工程とを有する半導体装置の製造方法において、 前記第1の開口部の形成と同時に、その形状が前記第1
の開口部と略同一であり、かつ、前記半導体基板、もし
くは、該半導体基板と電気的に接続する第2の導電層に
達する第2の開口部を形成する工程と前記第2の開口部
表面に電子線を走査して照射し、前記第2の開口部の試
料電流像を観察することにより、開口部の形成状態を検
査する工程を有することを特徴とする半導体装置の製造
方法。
[Claims] P formed on a semiconductor and surrounded by an n-type semiconductor region
forming an insulating film so as to cover the surface of the p-type semiconductor region or the surface of the first conductive layer electrically connected to the p-type semiconductor region; forming a first opening that reaches a first conductive layer;
forming a second opening that is substantially the same as the opening and that reaches the semiconductor substrate or a second conductive layer electrically connected to the semiconductor substrate; and a surface of the second opening. A method for manufacturing a semiconductor device, comprising the step of inspecting the formation state of the opening by scanning and irradiating the sample with an electron beam and observing a sample current image of the second opening.
JP6147888A 1988-03-15 1988-03-15 Manufacture of semiconductor device Pending JPH01235244A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6147888A JPH01235244A (en) 1988-03-15 1988-03-15 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6147888A JPH01235244A (en) 1988-03-15 1988-03-15 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH01235244A true JPH01235244A (en) 1989-09-20

Family

ID=13172217

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6147888A Pending JPH01235244A (en) 1988-03-15 1988-03-15 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH01235244A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1154456A (en) * 1997-07-25 1999-02-26 Samsung Electron Co Ltd Manufacture of semiconductor device
JP2002216697A (en) * 2001-01-17 2002-08-02 Horon:Kk Inspecting device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1154456A (en) * 1997-07-25 1999-02-26 Samsung Electron Co Ltd Manufacture of semiconductor device
JP2002216697A (en) * 2001-01-17 2002-08-02 Horon:Kk Inspecting device

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