JPH01233897A - Color killer circuit - Google Patents

Abstract

PURPOSE:To obtain a large color killer time constant without using a large capacity of capacitor by storing the state of a burst signal, supplying a signal representing the stored value in excess of a prescribed value to the counter so as to control the count and applying color killer based on the signal generated when the count reaches a prescribed value. CONSTITUTION:The state of the burst signal is stored in a capacitor 20 and a signal representing the stored value in excess of a prescribed value is given to a counter 36 to control the count and when the count reaches a prescribed number or over, a signal to be generated is used for color killer. Thus, a large color killer time constant is obtained without using a large capacity of capacitor and the capacitor 20 is incorporated in the inside of the IC. Moreover, the color killer time constant is decided nearly by the clock signal supplied to the counter 36, then accurate signal is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION A. Field of Industrial Application The present invention relates to a color killer circuit used, for example, in a color television receiver.

B1 Summary of the Invention The present invention accumulates the state of a burst signal in a color killer circuit used in a color television receiver, and supplies a signal indicating that the accumulated value exceeds a predetermined value to a counter. By controlling the counting operation and performing the color killer operation based on the signal generated when the number of counts exceeds a predetermined value, a large color killer time constant can be achieved without using a large capacity capacitor. In addition, it is possible to obtain accurate color killer time constants.

C1 Conventional technology Traditionally, for example, color television receivers have been equipped with a color killer circuit, and unless they are correctly receiving a color broadcast, a color killer operation is performed to eliminate color noise in the image. It has become so. An example of a conventional color killer circuit is shown in FIG. Note that this color killer circuit is used, for example, in a PAL television receiver.

In FIG. 4, a signal source 1O5 connected between the bases of transistors 101 and 102 and between the bases of transistors 103 and 104 supplies a burst signal. In addition, the transistors 106, 10
For example, the signal source 108 connected between each base of 7 is (R
-Y) for supplying a reference subcarrier for color demodulation corresponding to the color difference signal component. The emitters of the transistors 106 and 107 are connected to a current a 1110 via a switch 109 which is controlled on/off by a gate pulse corresponding to the burst signal portion, ie, the burst period. The demodulated burst signal is supplied to the capacitor 120 as a current from the collectors of the transistors i11 and 119. A current a131 is connected to the capacitor 120, which provides a bias current (2) to the capacitor 120. The capacitor 120 is discharged via transistor 119 if the burst signal is large enough.

Further, the capacitor 120 is charged via the transistor 111 when the burst signal becomes small. The voltage of the capacitor 120 increases and the voltage source 12
3, the output of the operational amplifier 124 becomes high level and a detection signal is output from the terminal 125. This detection signal becomes a color killer signal and is supplied to, for example, a color killer circuit, so that a color killer operation is performed.

Problems to be solved by the D0 invention By the way, the color killer time constant is usually several tens of lll5
eC to several hundred m5ec is required, so the capacitor 120 is required to have a large capacity.
When considering integrated circuits, it is extremely difficult to build this capacitance inside an IC, which increases the number of pins for external components.Also, using a large capacitance capacitor causes variations in the elements. It is difficult to obtain accurate color killer time constants.

The present invention was proposed in view of the above circumstances, and provides a method that allows a large color killer time constant to be obtained without using a large-capacity capacitor, and also allows an accurate color killer time constant to be obtained. The purpose is to provide a color killer circuit.

Means for Solving the E0 Problem In order to achieve the above-mentioned object, the color killer circuit according to the present invention includes a demodulating means for demodulating a burst signal, and a storage for accumulating the state of the burst signal using the output of the demodulating means. a detecting means for detecting that the accumulated value of the accumulating means exceeds a predetermined value; and a counter whose counting operation is controlled by being supplied with the output of the detecting means; The feature is that a color killer operation is performed based on a signal generated when the number exceeds a predetermined number.

F1 Effect According to the present invention, a large color killer time constant can be obtained without using a large capacitance capacitor.

G. Example Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a circuit diagram showing a color killer circuit in this embodiment. Note that this color killer circuit is, for example, PAL.
used in television receivers.

In FIG. 1, a signal source 5, connected in one section to each of the transistors 1.2 and between the bases of each of the transistors 3, 4, supplies a burst signal. Further, a signal source 8 connected between the bases of the transistors 6 and 7 supplies a reference subcarrier for color demodulation corresponding to the (RY) color difference signal component, for example. Each emitter of transistor 1.2 is connected to the collector of transistor 6, and each emitter of transistor 3.4 is connected to the collector of transistor 7. Each emitter of the transistor 6.7 is connected via a switch 9 to a current source 10.

The collectors of the transistors 1.3 are connected to the base of the transistor 11 and also to the power supply terminal 13 via the diode 12, and the collectors of the transistors 2.4
Each collector is connected to the base of the transistor 14, and is also connected to the IT power supply terminal 3 via a diode 15. The collector of transistor 14 is connected to current source 17 via switch 16 . This current source 17 supplies a bias current to a capacitor 20, which will be described later.
. Further, the collector of the transistor 14 is grounded via the diode 18, and
Connected to the base of transistor 19. The collector of this transistor 19 and the collector of the transistor 11 are each connected to a capacitor 20.

The capacitor 20 is connected to the emitter of a transistor 22 whose base is connected to a voltage source 21, and an operational amplifier 2 whose inverting input terminal is connected to a voltage a23.
It is connected to the non-inverting input terminal of No. 4. The output terminal of the operational amplifier 24 is connected to a terminal 25. The switches 9 and 16 are controlled on/off synchronously by gate pulses corresponding to the burst period. Above switch 9
, 16 are of course turned on during the burst period.

The demodulated or synchronously detected burst signal is supplied to the capacitor 20 as a current from each collector of the transistors 11 and 19. The capacitor 20 is discharged via the transistor 19 if the burst signal is large enough. Further, the capacitor 20 is charged via the transistor 11 when the burst signal becomes smaller than the bias voltage fiIs. That is, the state of the burst signal is stored in the capacitor 20.

When the voltage (accumulated value) of the capacitor 20 exceeds a predetermined threshold voltage determined by the voltage source 23, this is detected and the output of the operational amplifier 24 becomes high level and the terminal 25
A detection signal DS is output from. Note that transistor 2
2 and the voltage source 21 determines the lower limit value of the voltage of the capacitor 20, and if the burst signal continues to be sufficiently large, the voltage of the capacitor 20 is maintained at that value.

The detection signal DS is supplied to the counter circuit section 26, thereby controlling the counting operation of the up/down counter 36 (for example, switching control between count up and count down). Then, the count number of the up/down counter 36 is a predetermined number ('l0 in this embodiment).
J) Color killer signal C is output from terminal 54 when the
K is output, and a color killer operation is performed based on this color killer signal CK.

A specific configuration example of the color killer circuit section 26 is shown in FIG. 2. In FIG. 2, a terminal 31 to which the detection signal DS- is supplied is connected to an AND circuit 32. As shown in FIG. Also,
The terminal 31 is connected to an AND circuit 33 and also to an AND circuit 35 via an inverter 34. The AND circuit 32 is connected to an UP/DN terminal of a 4-bit up/down counter 36 and an AND circuit 37, respectively. The up/down counter 36 performs a count-up operation during a period when the U P/D N terminal is at a high level, and performs a count-down operation during a period when the U P/D N terminal is at a low level.

A terminal lock signal φ is supplied from a terminal 38 to the C terminal of the amplifier down counter 36. This clock signal φ
For example, the vertical synchronization period (IV = 20 m5ec)
A pulse having a period of about Q0 to Q of the up/down counter 36.

Each terminal is connected to an AND circuit 39, and is also connected to an AND circuit 44 via each inverter 40, 41, 42, 43, respectively. The AND circuit 39 is configured so that the up/down counter 36 has a maximum count number C, A, l (in this embodiment, "15").
", "11ll" in binary notation), and the AND circuit 44 decodes the fact that the count number of the up/down counter 36 is the minimum count number C□N (
In this embodiment, it is decoded to indicate that it has become "0" (roooo in binary notation).

The AND circuit 39 is connected to the AND circuit 33, and is also connected to the AND circuit 32 and the AND circuit 35 via an inverter 45, respectively. Also,
The AND circuit 44 is connected to the AND circuit 35 and also to the AND circuit 33 via an inverter 46.

The AND circuits 33 and 35 are each connected to an OR circuit 47, and the OR circuit 47 is connected to the PE terminal of the up/down counter 36. The PE terminal becomes high level when the up/down counter 36
This is the case when the count number is the maximum count number CMA11 and the terminal 31 is at a high level, or when the above count number is the minimum count number C□ and the terminal 31 is at a low level. When the PE terminal becomes high level, the count number is held at the maximum count number CMAX or the minimum count number CMIN.

The terminals Q2 to Q of the up/down counter 36 are connected to the OR circuit 4, respectively. This OR circuit 48
The count number of the up/down counter 36 is "4"
This is to decode that the value is r0100J or more in binary notation, and by this, the color killer signal CK, which will be described later, is decoded.
A threshold value TL is determined to set the value to low level. The OR circuit 48 is connected to an AND circuit 49.

The Q1 terminal of the up/down counter 36 is connected to an AND circuit 50, and the Q2 terminal is connected to the AND circuit 50 via an inverter 42. The AND circuit 50 and the Q2 terminal are connected to an OR circuit 51, respectively. The OR circuit 151 and the Q terminal of the up/down counter 36 are connected to an AND circuit 52, respectively. This AND circuit 52 calculates that the count number of the up/down counter 36 is "lO", rl in binary notation.
olo, which decodes the above,
As a result, a threshold (t!TH) for setting the color killer signal CK to a high level, which will be described later, is determined. The AND circuit 52 is connected to an AND circuit 37. The above AND circuit 49
The AND circuit 49 is connected to a terminal 54 from which a color killer signal CK is output. Also,
The AND circuit 49 is connected to the OR circuit 53 and also to the AND circuit 37 via an inverter 55.

Next, a third section regarding the operation of the counter circuit section 26 described above will be explained.
This will be explained with reference to the time chart shown in the figure. In FIG. 3, (A) shows the clock signal φ, and (B)
shows the detection signal DS, (C) shows the count number of the up/down counter 36, and (D) shows the color killer signal CK.

A lock signal φ is supplied to the terminal 38, that is, the C terminal of the up/down counter 36, as shown in FIG. 3(A). If the detection signal DS as shown in FIG. 3(B) is now supplied to the terminal 31, the up/down counter 36
As shown in FIG. 3(C), the detection signal DS
A count amplifier operation is performed during the period when the signal is at a high level, and a countdown operation is performed during a period when the signal is at a low level. As shown in FIG. 3(D), the color killer signal CK outputted from the terminal 45 becomes high level when the count number of the up/down counter 36 reaches a predetermined count number rl 04 which is the threshold value TH. Then,
It becomes a low level when the predetermined count number "3" becomes the threshold value TL or less. The color killer signal CK obtained in this manner is supplied to, for example, a color control circuit or the like, and a color killer operation is performed.

The counter circuit unit 26 described above has a large time constant, and even if the detection signal DS changes in a short time, the color killer signal CK does not respond. Therefore, according to the color killer circuit of this embodiment shown in FIG. 1, an isometrically large color killer time constant can be obtained.

Therefore, there is no need to use a large capacity capacitor 20, and it can be built inside the capacitor 20. Also,
The color killer time constant is accurate because it is determined by the frequency of the clock signal φ.

Note that the color killer circuit according to the present invention is, for example, NTS
It can also be applied to a C-scheme television receiver.

H1 Effects of the Invention As is clear from the description of the embodiments described above, the color killer circuit according to the present invention accumulates the state of the burst signal and supplies the counter with a signal indicating that the accumulated value exceeds a predetermined value. The color killer operation is performed based on a signal generated when the counted number exceeds a predetermined number. Therefore, a large color killer time constant can be obtained without using a large capacity capacitor, and the capacitor can be built inside the IC. Furthermore, since the color killer time constant is almost determined by the clock signal supplied to the counter, an accurate one can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of the color killer circuit according to the present invention, FIG. 2 is a logic circuit diagram showing a specific configuration example of a counter circuit section, and FIG. 3 is a circuit diagram showing an example of a specific configuration of a counter circuit section. 5 is a time chart for explaining the operation of the circuit section. FIG. 4 is a circuit diagram showing an example of a conventional color killer circuit. ], 2.3, 4, 6. ,? ... Transistor (demodulation means) 20 ... Capacitor (accumulation means) 24 ... Operational amplifier (detection means) 36 ... Up-down counter

Claims (1)

[Scope of Claims] Demodulation means for demodulating a burst signal; Accumulation means for accumulating the state of the burst signal based on the output of the demodulation means; Detection for detecting that the accumulated value of the accumulation means exceeds a predetermined value. and a counter whose counting operation is controlled by being supplied with the output of the detection means, and performs a color killer operation based on a signal generated when the count number of the counter exceeds a predetermined number. A color killer circuit that is characterized by the following: