JPH01228213A - Clock signal adjusting circuit - Google Patents

Abstract

PURPOSE:To obtain a clock signal whose duty and phase are adjusted by inputting the output of a differentiation circuit with one time constant to an AND circuit with the output fed back by passing the differentiation circuit with a different time constant, and inputting the output to the AND circuit after inverting. CONSTITUTION:A clock signal (a) is inverted at a first inverting circuit 1, and is inputted to the differentiation circuit 2. The signal of the circuit 2 is inputted to a first AND circuit 3. The output of a second differentiation circuit 4 goes to an L. level at the time of falling the signal similarly, and after that, it goes to the signal whose level is recovered to an H level by the time constant tau2. The signal (d) of the circuit 3 is inverted at a second inverting circuit 5, and the AND of the output (b) of the circuit 2 is taken at a second AND circuit 6. The time constant tau1 of the circuit 2 and the time constant tau2 of the circuit 4 are selected arbitrarily. The signal inputted to the circuits 3 and 6 is set at the L level once, and a time to recover to a threshold voltage is adjusted. In such a way, the duty and the phase can be adjusted.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a circuit that adjusts the duty and phase of a clock signal using a gate circuit and a differential circuit.

[Prior Art] Conventionally, a circuit shown in FIG. 3 has been proposed as a circuit for adjusting the duty and phase of a clock signal. This circuit adjusts the duty using a differentiating circuit 11 and an AND circuit 12, and an inverting circuit 13. Differentiation circuit 14, AND circuit 15. The differential circuit I6 and the inversion circuit 17 are configured to adjust the phase.

[Problem to be solved by the invention]

The conventional clock signal adjustment circuit described above has a circuit configuration in which the duty and phase are adjusted independently, so each circuit must be configured with an individual differentiating circuit and a gate circuit, and in the end, the overall There are three differentiating circuits 1
2, 14, 16 and four gate circuits 11, 13, 15
．． 17 is required, which increases the number of parts constituting the circuit and makes the circuit complicated.

SUMMARY OF THE INVENTION An object of the present invention is to provide a clock signal adjustment circuit that allows duty cycle adjustment with a reduced number of component parts.

[Means to solve the problem]

The clock signal adjustment circuit of the present invention includes first and second inverting circuits, first and second differentiating circuits, and first and second AND circuits, and unifies the outputs of the inverting circuits. The output is input to a differentiating circuit with a time constant of It is configured to obtain a clock signal with its phase adjusted.

[Effect]

In the above configuration, the output of the inverting circuit is input to a differentiating circuit with a time constant of one, and the output is used as the input of the AND circuit together with the output fed back through the differentiating circuit with a different time constant, and after inverting this output, the former A clock signal with duty and phase adjusted is obtained through an AND circuit along with the output of the differentiating circuit.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention.

In the figure, the input clock signal is the first inverted (NO
T) It is inverted in the circuit 1 and input to the first differentiating circuit 2. This first differentiating circuit 2 has a time constant τ.

The output thereof is input to one input terminal of the first AND circuit 3. The output of the first AND circuit 3 is branched, and a portion is inputted to the other input terminal of the first AND circuit 3 through a second differentiator 4 having a time constant τ2.

Other signals from the first AND circuit 3 are sent to the second inverting circuit 5.
The signal is inverted at , and inputted to one input terminal of the second AND circuit 6 . The output of the first differentiating circuit 2 is input to the other input terminal of the second AND circuit 6, and a clock signal whose duty and phase have been adjusted is output from the second AND circuit 6.

Now, when a clock signal having the duty and phase shown in FIG. 2(a) is input to the first inverting circuit 1, this clock signal is inverted and input to the differentiating circuit 2. low) level, and then the time constant τ of the differentiator circuit 2
The signal shown in FIG. 2(b) is returned to the H (high) level by .

When this signal is input to the first AND circuit 3, when the signal falls, it becomes L level no matter what other input signals are, so the output of the second differentiator circuit 4 which takes this as input is the first differentiator. Similar to circuit 2, the signal becomes L level at the falling edge of the signal, and then returns to H level with time constant τ2, resulting in the signal shown in FIG. 2(C).

From this, the output of the first AND circuit 3 becomes the signal shown in FIG. 2(d) by performing the logical product (AND) of FIG. 2(b) and (C).

Next, this signal in FIG. 2(d) is inverted by a second inverting circuit 5, and in a second AND circuit 6, it is ANDed with the signal in the state of the first differentiating circuit 2, that is, the signal in FIG. 2(b). By taking , the signal shown in FIG. 2(e) can be obtained.

Therefore, in this circuit, the time constant τ of the first differentiating circuit 2,
By arbitrarily selecting the time constant τ2 of the second differentiating circuit 4, the signal input to the first and second AND circuits 3.6 becomes L level once, and returns to the threshold voltage of each AND circuit. You can adjust the time until
This makes it possible to change the ON time of each AND circuit 3.6, making it possible to adjust the duty and phase.

In the end, this circuit can be configured with two differentiating circuits and four gate circuits, and compared to the conventional structure shown in FIG. 3, the number of differentiating circuits can be reduced by one, and the number of circuit components can be reduced and the circuit can be simplified.

[Effects of the Invention] As explained above, the present invention inputs the output of an inverting circuit to a differentiating circuit with a time constant of one, and uses the output as an input of an AND circuit together with the output fed back through a differentiating circuit with a different time constant. This output is inverted and then passed through an AND circuit together with the output of the former differentiating circuit to obtain a clock signal with the duty and phase adjusted, so one differentiating circuit can be reduced compared to the conventional structure. This has the effect of reducing the number of parts and downsizing the entire circuit.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of one embodiment of the present invention, and FIG. 2 is a block diagram of an embodiment of the present invention.
A time chart showing the signals at each point a''-e in the circuit shown in the figure, and FIG. 3 is a block diagram of a conventional clock signal adjustment circuit. 1... first inverting circuit, 2... first differentiating circuit , 3...
・First AND circuit, 4... Second differentiating circuit, 5... Second inverting circuit, 6... Second AND circuit, 11... AND circuit, 12... Differentiating circuit, 13...・Inversion circuit, 1
4... Differential circuit, 15... AND circuit, 16...
Differential circuit, 17...inversion circuit. Figure 3

Claims (1)

[Claims] 1. A first inverting circuit that inverts the input clock signal, a first differentiating circuit that differentiates this inverted signal with one time constant, and a second differentiating circuit that differentiates the output of this first differentiating circuit with a different time constant. a first AND circuit that takes an AND of the outputs of the first and second differentiating circuits; a second inverting circuit that inverts the output of the first AND circuit; 1. A clock signal adjustment circuit comprising: a second AND circuit that performs a logical product of the outputs of the first differentiation circuit and outputs an output clock signal.