JPH01227112A - Automatic focusing device - Google Patents

Abstract

PURPOSE:To speedily and accurately focus and control an image pickup optical system with respect to an object by calculating defocus quantity from deviation from the position of a picture element when it is focused and controlling a driving means according to the defocus quantity so that the image pickup optical system is driven to a focal point on its optical axis. CONSTITUTION:A sensor means 32 nondestructively outputs a pair of analog electrical signals corresponding to the luminosity distribution of a pair of optical images at prescribed intervals by shifting the output timing on a picture element basis. A comparing means 78 compares the magnification of correlation values outputted from an analog arithmetic means 74, and based on the result, a control means 86 calculates the deviation from the position of a picture element of the sensor means 32 when the correlation values are minimized. The defocus quantity is calculated from the deviation, and the driving means is controlled such that the image pickup optical system is driven by the defocus quantity in the direction in which said system can be focused. Thus, the image pickup optical system can be speedily and precisely focused and controlled with respect to an object by the simple expedient.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an automatic focus adjustment device for optical equipment such as a camera, and in particular, the arithmetic processing of phase difference detection performed during focus detection of an imaging optical system is performed by analog signal processing. The present invention relates to an automatic focus adjustment device suitable for use in an automatic focus adjustment device for a camera used in a camera.

[Conventional technology]

An automatic focus detection device used in a conventional automatic focus adjustment device for optical equipment such as a camera has a configuration shown in FIG. A lens 3, a separator lens 4, and a phase difference detection device are arranged in this order.

The phase difference detection device is a CC that receives a pair of subject images formed by the separator lens 4 and photoelectrically converts the received images.
It is comprised of a line sensor 5.6 such as D, and a processing circuit 7 that determines the in-focus state based on an electrical signal generated according to the luminous intensity distribution in each pixel of the line sensor 5.6.

The image formed on the line sensor 5.6 approaches the optical axis 8 side when the subject image is in the front focus state located in front of the imaging eccentricity 2, and conversely when the subject image is in the rear focus state. The lens moves further away, and in the focused state is at a predetermined position between the front focus and the rear focus. Therefore, processing time vJ! 7 is each line sensor 5
, 6, and by detecting the position of the image from the optical axis 8, the in-focus state is determined. A phase difference detection method is used to detect the position of the image formed on the line sensors 5 and 6. This method uses the following formula (1
), the correlation calculation value of a pair of images formed on the line sensor 5.6 is calculated, and the in-focus state is determined based on the relative movement amount (phase difference) of these images until the correlation calculation value becomes the minimum. Determine.

However, l is an integer from 1 to 9 and indicates the above-mentioned relative movement amount.

however! When =1, the shift operation is not performed,
! A shift operation is performed when ≧2 or more.

For example, B(k) is an electrical signal output in time series from each pixel of the line sensor 5, R(k+f-1) is an electrical signal output in time series from each pixel in the line sensor 6, and β If the above formula [1] is calculated every time the value is changed from 1 to 9, the correlation calculation values H(1), H(2),...H(
9) is obtained. For example, it is set in advance that the in-focus state is achieved when the correlation calculation value H(5) is the minimum value, and if the correlation calculation value at a position deviated from this becomes the minimum value, the deviation amount, that is, β A phase difference of up to =5 can be detected as a focus shift (defocus amount).

The configuration of a conventional processing circuit 7 is shown in FIG. Analog electrical signal B generated by each pixel of line sensor 5.6
(k) and R(k) are converted into, for example, 8-bit digital data by an A/D converter 9, and once stored in RAM (Random Ac
The digital data is stored in the digital data, and then the above equation (1) is calculated based on these digital data.

[Problem that the invention seeks to solve]

However, in such conventional automatic focus adjustment devices, calculation processing for phase detection during focus detection of the imaging optical system is performed by digital signal processing using a microcomputer, etc., so it is fast and In order to perform high-precision calculations, expensive A/D converters are required, and rounding errors occur due to quantization of the microcomputer that performs the calculations, resulting in a decrease in calculation accuracy.
Furthermore, the burden of designing a computer program for arithmetic processing increases, and the number of parts increases due to the need for a storage device that stores a large amount of digital data (which leads to problems such as an increase in the size of the device). there were.

The present invention was made in view of these circumstances, and
It is an object of the present invention to provide an automatic focus adjustment device that has a simple configuration and can control the focus of an imaging optical system on a subject at high speed and with high precision.

[Means for solving problems]

In order to achieve the above object, the present invention detects the relative position of a pair of optical images of a subject to determine whether or not the imaging optical system is in a focused state, and if the imaging optical system is not in a focused state, the relative position of a pair of optical images of a subject is detected. In an automatic focusing device that performs focusing by driving the imaging optical system in the direction of its optical axis based on the target position until it reaches the in-focus state, multiple photoelectric conversion elements forming one pixel are arranged in a line. The sensor includes a pair of sensors arranged, and the pair of sensors photoelectrically converts the pair of optical images, and the photoelectric conversion generates an analog electrical signal corresponding to one optical image on one side and an optical image on the other side. A sensor means that non-destructively outputs an analog electrical signal while shifting it pixel by pixel at a predetermined period, and an analog sensor that performs a +/- opening calculation on a pair of analog electrical signals output from the sensor means and outputs a correlation calculation value. a calculation means, a comparison means for sequentially comparing the magnitudes of the correlation calculation values outputted in time series from the analog calculation means, a drive means for driving the imaging optical system in the direction of its optical axis, and an output signal of the comparison means. , calculate the pixel position of the sensor means at which the correlation calculation value outputted from the analog calculation means is minimum based on the comparison output, and calculate the amount of deviation of the pixel position from the pixel position at the time of focusing. , a control means for calculating a defocus amount from the deviation amount and controlling the driving means to drive the imaging optical system to a focus position on its optical axis in accordance with the defocus amount. That is.

[Effect]

In the automatic focus adjustment device according to the present invention, an optical image of an object is transmitted to a pair of sensors constituting a sensor means in which a plurality of photoelectric conversion elements forming one pixel are arranged in a line through an imaging optical system. is imaged.

The sensor means non-destructively outputs a pair of analog electrical signals corresponding to the luminous intensity distribution of the pair of optical images for each pixel at a predetermined period.

A pair of analog electrical signals outputted from the sensor means are subjected to correlation calculation by the analog calculation means, and correlation calculation values are outputted in time series.

The correlation calculation value outputted from the analog calculation means is compared in magnitude by the comparison means, and based on the comparison result, the control means selects the pixel position of the sensor means at which the correlation calculation value is the minimum from the pixel position at the time of focusing. A defocus amount is calculated from the deviation amount, and the driving means is controlled so as to drive the imaging optical system by the defocus amount in a direction in which the imaging optical system is brought into focus.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 shows the configuration of an embodiment of a camera equipped with an automatic focus adjustment device to which the present invention is applied. In the figure, the zoom lens 20 includes a focus lens group 2OA that forms an image of the object [1 on the focal plane, a variator lens group 20B that changes the focal length, and a variator lens group 20B that changes the focal length. Compensator lens group 20 to be corrected
C, and master lens groups 20D and 20E. A diaphragm 22 is disposed between the compensator lens group 20C and the master lens group 20D. Furthermore, a beam splitter 24 is arranged between the master lens groups 20D and 20E.

The focus lens group 2OA is held in a tenth inner cylinder (not shown) and passed through the first outer cylinder. By rotating the first outer cylinder, the focus lens group 2OA can be moved in the optical axis direction, and the rotation of the outer cylinder is performed by a DC motor 66. The DC motor 66 is rotationally driven by a drive signal output from a motor drive circuit 68. The absolute position of the focus lens group 2OA, which moves to a predetermined position as the first outer cylinder rotates, is determined by the focus lens position detection unit 7 provided in the tenth outer cylinder.
This can be determined from the position data based on the gray code output from 0. Position data based on the gray code is created by pattern electrodes formed in the focus lens position detection section 70, and position data indicating the movement position of the focus lens group 2OA is output to the control circuit 86.

The control circuit 86 is composed of a micro combi coater, etc.
Although each part of the camera including focus control is controlled, in this embodiment, controls other than focus control will not be explained because they are outside the scope of the present invention.

A rotating shaft of the DC motor 66 is connected to a first outer cylinder via a gear mechanism, and the first outer cylinder is rotated by the DC motor 66.

The amount of rotation is determined by a disk 6 with many radially formed slits.
4A and a photo ink club Taro 4B.

To detect the movement tlJl of the focus lens group 2OA, the amount of rotation of the DC motor 66 is detected by a detector that counts the number of slits in a disk with slits, and the detected value is associated with the amount of movement of the focus lens group 2OA. It may also be configured to do this by

The variator lens group 20B and the compensator lens group 20C are held together in a second inner cylinder (not shown).
It is passed through the outer cylinder. A cam groove is formed inside the second outer cylinder, and a pin protruding from the outside of the second inner cylinder is located in the cam groove. Although the magnification of the zoom lens changes by rotating the second outer cylinder, the subject image is always focused on the light receiving surface of the CCD 42 for imaging. The magnification of the zoom lens is determined by the zoom information based on the gray code (in this example, the focal length f of the zoom lens) output from the zoom lens detection unit 72 provided in the 20th outer cylinder.
You can check from z).

Zoom information output from the zoom lens detection B72 is manually input to the control circuit 86.

The light passing through the aperture is split by a beam splitter 24 into an imaging optical system and an AF optical system.

The light split by the beam splitter 24 is AF (A
The light is received by a sensor means 32 for AF via an autofocus lens 26, a reflecting mirror 28, and a sensor optical system 30. The sensor optical system is composed of a condenser lens 3, a separator lens 4, etc. shown in FIG.

The aperture of the diaphragm 22 is adjusted by a servo motor (not shown) that is driven and controlled by a control circuit 86.

The light passing through the zoom lens is reflected upward by the reflecting mirror 34.
0° is reflected and enters the beam distributor 36. The reflecting mirror 34 is kicked upward during photographing, whereby the incident light passes through the low-pass filter 38 and the stripper 40 and forms an image on the light receiving surface of the CCD 42 for imaging. Charges corresponding to the subject image are accumulated on the light-receiving surface of the CCD 42, and an electric signal corresponding to the charge pattern is output to the recording section 44.

A low-pass filter 38 is provided to remove unnecessary components from the incident light so that interference fringes are not generated, and a shutter 40 is provided to adjust the light reception time of the CCD 42. The recording unit 44 is configured to create a video signal representing a subject image based on the input signal and record it on a recording medium such as a magnetic sheet.

The light incident on the beam splitter 36 is directly guided to the finder optical system via the imaging lens 44, and a portion of the light from the beam splitter 36 is received by the light receiving element 46.

The electric signal photoelectrically converted by the light receiving element 46 is input to a control circuit 86, and the control circuit 86 controls the aperture value of the aperture 22 and the shutter speed of the shutter 40 based on this input signal.

The finder optical system is composed of a reflecting mirror 48, a relay lens 50, and an eyepiece lens 52.

A strobe 53 is installed on the top of the camera body! A light emitting element 12 is provided within the main body of the strobe 53 to be used as auxiliary light when the brightness of field light is insufficient during automatic focus adjustment.

The control circuit 86 is a circuit that integrates and controls the camera body, and the control circuit 86 includes an operation section 88 such as a power switch and a shirt release button, and a display section (not shown) that displays various data. It is connected.

Now, the photoelectrically converted analog electric signal outputted from the sensor means is input to the analog calculation means 74, and the analog calculation means 74 performs a correlation calculation. The configuration of the sensor means 32 and analog calculation means 74 is shown in FIG. In the figure, the sensor means 32 is the reference image sensor 3.
20, a reference image sensor 321, a reference readout B522, and a reference readout unit 323. The reference image sensor 320 and the reference image sensor 321 are
CC corresponds to line sensor 5.6 in the figure and transfers signal charges generated for each pixel using multiple charge transfer elements.
p <charge storage device).

Further, the reference readout unit 322 and the base readout unit 323 are configured to output analog electrical signals (hereinafter referred to as pixel signals) related to the subject image photoelectrically converted by each image sensor 320 and 321 in time series at a predetermined timing. It has become.

The analog calculation means 74 includes an analog calculation section 740, a control signal generation section 742, and an AGC circuit 744.

The analog calculation 740 performs a phase difference detection calculation based on the pixel signals R(k) and B(k) outputted from the reference succession unit 322 and the base table succession unit 323 while shifting each pixel unit, The calculation result is output to the output terminal 745.

The control signal generator B742 generates various control signals for controlling the operation timing of the entire device, such as a charge transfer lock signal for operating the CCD in the image sensors 320 and 321, and a readout unit 322, 323. A control signal and other signals are generated for outputting the pixel signals R(k) and B(k) at a predetermined timing synchronized with the charge transfer lock signal.

The AGC circuit 744 detects the signal charge generated in each pixel of the image sensor 320 and 321, and when it detects that a predetermined amount of charge has been reached, it sends a command to the control signal generation unit 742 to start calculation of phase difference detection. command.

FIG. 3 shows a specific circuit constructed in step 5) based on the block diagram shown in FIG. Explaining the circuit in correspondence with each block in FIG. 2, the reference image sensor 320 and the reference image sensor 321 have almost the same configuration, and the photoelectric conversion elements Drl to DrnSDbl, which become the respective pixels.
A storage section 102.10 consisting of a light receiving section 100.101 having ~Dbn and a CCD provided for storing signal charges generated in each of the light receiving sections 100.101 for each pixel.
3, and shift registers R104 and 105 formed by CCDs that take in signal charges transferred from storage sections 102 and 103 and transfer the charges in the horizontal direction.

That is, the storage sections 102 and 103 and the shift register section 10
4.105 are photoelectric conversion elements Drl to Drn.

Charge transfer elements Tr1~ corresponding to Dbl~Dbn
Trn, Tbl ~ TbnXCr1 ~ Crn5Cbl
~Cbn, the storage units 102 and 103 transfer the signal charges in parallel to the shift register units 104 and 105, and the shift register unit 104 transfers them in the horizontal direction. As will be described later, the shift register B1 on the reference image sensor side
Unlike the shift register 'B104, the register 05 does not transfer signal charges in the horizontal direction.

106.107 is from the light receiving section 100.101 to the storage section 1.
This is a conductive layer formed on the surface of the channel section that transfers signal charges to 02.103, and is formed of a polycondensate layer and serves as a potential barrier section.

108 and 109 are transfer gates that control the movement of signal charges.

Furthermore, each charge transfer element) Crl to Crn.

Floating gate Frl adjacent to Cbl to Cbn
~Frn, Fbl~Fbn are formed, and each floating gate Frl -FrnXFbl ~Fbn is an MO3 type FET whose gate is supplied with a control signal CE.
MO3 type FETs Qrl to Qr that are connected to the reset terminal RES via Mrl to Mrn and Mbl to Mbn and perform multiplex operation by applying a channel switching signal GHI-CHn to their gates.
n, common contact Pr through Qbl to Qbn,
Pb, and the common contacts Pr and Pb are connected to the contact Pr through impedance conversion circuits 110 and 111, respectively.
Connected to 01PbO.

The impedance conversion circuits 110 and 111 both have the same circuit configuration, and include an MO3 type FET Irl whose drain-source path is connected in series between the power supply ■DD and the ground terminal.
Ir2, Ibl, Ib2 and MO3 type FET Tri
, Ibl are connected in parallel between the gates and sources of MOS type FETs 1r3 and Ib, which clamp the common contacts Pr and Pb to the power supply VDD when the refresh signal φR is applied.
3, and the gates of the MOS type FETs Ir2 and Ib2 are biased to a predetermined potential.

Next, the positional relationship between the shift register sections 104 and 105 and the floating gates Frl to Frn and Fbl to Fbn will be explained with reference to FIG.

Light receiving unit 100 and storage unit 1 on the reference image sensor 320 side
02, 48 photoelectric conversion elements and charge transfer elements of the shift register section 104 are formed with the same pitch width W, and there are 40 photoelectric conversion elements and 48 charge transfer elements, excluding the first and second blocks IR and IIR, each consisting of four parts on both sides. The third block II [R charge transfer elements Crl to Cr40
Floating gates Frl to Fr40 are added to the 32 floating gates Frl to Fr40.
The fourth block rVR consists of 32 blocks, and the remaining fifth block VR. One end of the floating gates Frl to Fr40 is connected to the MO3 type F in FIG.
ET Mrl, Mr2, . . . are connected to the reset terminal RES, and the floating gate Fr among them is
l~F r32 is the MOS type FET Qr in Fig. 3
It is connected to contact Pr via l to Qrn. That is, in FIG. 3, the third and fourth blocks II [R
, rVR is shown as a representative, and other IR, UR, VR
Although the description of the part is omitted, these are reserve areas that operate when transferring signal charges in the horizontal direction.

On the other hand, 40 photoelectric conversion elements and charge transfer elements of the light receiving section 101, the storage section 103, and the register section 105 of the reference image sensor 321 are formed with the same pitch width W (the same on the reference image sensor 320 side), Floating gates Fbl to Fb32 are provided adjacent to the charge transfer elements Cbl to Cb32 of the third block I[[B, excluding the first and second blocks IB and IIB, which are composed of four parts on each side. One end of each of the floating games Fbl to Fb32 is connected to the MOS type FET Mbl in FIG.
~Mbn, Qbl is connected to ~Qbn.

That is, FIG. 3 shows the third block I[IB in FIG. 4.

Also, the distance between the light receiving unit 100 and the optical axis 90 is ! The light receiving portions 101 are formed with a distance of 11 and a pitch width of 4W.
are separated by a distance β2 (=11+4·W).

Next, the phase difference detection device according to this embodiment is integrated into a single chip as a semiconductor integrated circuit device, and includes an image sensor 100 (101) to a floating gate F.
The structure will be explained based on the schematic cross-sectional view of FIG. 5 shown from rl to Frn (Fbl to Fbn).

In FIG.
A group of photoelectric conversion elements of the light receiving section 100 (101) is configured by forming the eyebrows. In addition, there are 8
The transfer gate electrode layer and the transfer gate 108 (109) which constitute each charge transfer element of the barrier section 106 (107) and the storage section 102 (103) that generate the signal STS are formed through 102 layers (not shown). A gate electrode layer and a transfer gate electrode layer constituting each charge transfer element of the shift register section 104 (105) are provided together. Further, floating gates Frl to Frn are adjacent to the shift register sections 104 and 105.

The polysilicon layer constituting Fbl to Fbn and the power supply V
An electrode layer Al is laminated to be clamped to the DD. This electrode layer Al is formed so as to cover the entire upper surface of the plurality of floating gates Fr1-Frn, Fbl to Fbn. Then, MO3 type FETs Mrl to MrnSMbl are connected to one end of each floating gate.
~Mbn is connected.

In addition, the light receiving part 100° formed on the surface part of the semiconductor substrate
A lateral overflow gate (LOG) 90 is provided adjacent to (101) via an 8102 layer (not shown), and a lateral overflow drain (LOG) 90 is provided adjacent to the lateral overflow gate 90 on the surface of the semiconductor substrate. LOD) 92 is formed.

The overflow gate 90 is supplied with a power supply voltage Vcc or a voltage VBA (VBA < Vcc) via a switch 94 that can be switched manually or automatically.

Now, the reset signal φ applied to the reset terminal RES
By setting FG to the same potential as the power supply VDD and controlling the “H” level control signal CE, MO3 type FETs Mr1 to Mrn
Floating game via Mbl~Mbn) Fr
After clamping l ~FrnXFbl ~Fbn to the power supply VDD, MO3 type FET Mrl ~Mr again
When nSMb1 to Mbn are turned off, a deep potential well is formed in the semiconductor substrate as shown by the dotted line in FIG. 5, and the signal charge of the shift register section 104 (105) flows into the region under the floating gate. The voltage drop corresponding to the amount of each of the signal charges flowing in is the voltage drop of each floating gate)Frl~Frn(Fbl
~Fbn), and the imaged pattern on the light receiving section 100 (101) can be detected as a voltage signal.

On the other hand, after setting the reset terminal RES to ground potential, MO
By turning on the type 3 FETs Mrl~Mrn and Mbl~Mbn, the floating gates Frl~F
When rn, Fbl to Fbn are set to "L" level, the potential well in the region under the floating gate becomes shallower, and the signal charge can be returned to the shift register section 104 (105) again. Since such signal charge movement is performed non-destructively, signal charge reading can be repeated many times.

On the other hand, unnecessary charges among the signal charges generated by photoelectric conversion by the light receiving section 100 (101) are removed by clamping the lateral overflow gate 90 to the power supply voltage Vcc (>VB8) (by doing so, the lateral overflow drain (L
(OD) area 92.

Therefore, only the signal charges of the photoelectric conversion elements within a specific range among the plurality of photoelectric conversion element groups constituting the light receiving section 100 are transferred to the floating gate) Frl~Frn (Fbl~Fb).
n) In order to cause the signal charge to flow into the lower region and detect it as a voltage signal, the signal charge generated in the photoelectric conversion element outside the above-mentioned specific range can be discharged to the lateral overflow drain region 92 as described above.

In this way, the floating gates Frl to Frn.

The signal generated via Fbl to Fbn is transferred to an MO3 type FET.
Time series signals R(k), B(k
) and convert the terminals PrQ and Pb of the analog calculation red 740 into
Output to Q.

The control signal generation section 742 generates channel switching signals CHI to C)In of a predetermined period, a transfer lock signal Tf, and a transfer gate 108.10 to the storage section 102.103.
9 gate signal TG, shift register section 104.105
Transfer lock signals φr1 to φr4, φbl to φb4,
Enable signal EN, clear signal CLR and control signal C
E, φSR, and φSit are generated at predetermined timings.

Next, the operation of phase difference detection by the phase difference detection device shown in FIGS. 2 and 3 will be explained with reference to the timing chart of FIG. 6.

Before time to, photoelectric conversion elements Drl to Drn
When the AGC circuit 744 detects that Dbl to Dbn have generated a predetermined signal charge, the AC signal becomes “H”.
'' level, the start signal S applied at time to
Arithmetic processing starts in synchronization with TR (which occurs in conjunction with a camera release button, etc.). First, reset terminal 28
A reset signal φR with a constant period Ta is generated. Also, during the period from time to to t3, each charge transfer element of the shift register section 104 and 105 (see FIG. 4)
4-phase lock signals φr1 to φr4, φb1 to φb4 that cause charge transfer based on the 4-phase driving force formula to be performed for one pitch only.
occurs.

Time t1 during charge transfer by this charge transfer element
At this time, the control signal CE becomes "H" level and the MO
Type 3 FET ~1rl ~Mrn, Mbl ~Mb
When n is turned on, the reset signal φFG is “L”.
By inverting from o to "H" level, the 7 o-ting gates Frl ~ Fr40, Fbl ~ Fb32
is clamped to the potential of the power supply voltage VDD, and at time t2, the control signal CE becomes "L" level and the MO3 type FET
Since Mrl, Mr2, . . . , Mbl, Mb2, . . . have high impedance, the floating gate is maintained at the potential. As a result, a potential well as shown in FIG. 5 is formed in the semiconductor substrate under the floating gate. Then, since the transfer gates 108 and 109 are made conductive by the gate signal φTG a little before time t2, the storage section 1
The signal charge of 02.103 is transferred to the shift register section 104.1.
05 to the corresponding charge transfer element. The signal charges are further transferred to each of the potential wells before the transfer operation of the charge transfer element is completed at time t4.

Next, during the period from time t4 to t5, channel switching signals CHI to CH32 are output, and the MOS type FETs Qrl to Qrn, which constitute the multiplexer circuit,
Qbl to Qbn are turned on, and time-series signals for each pixel are output to contacts Pro and Pb(l. Contacts PrQ,
The signal waveform of PbO appears, for example, as shown by CQi in FIG. That is, each floating game) Frl~l
"rnSFbl to Fbn have a voltage drop corresponding to the signal charge for each pixel, and the contact Pr01PbO has a power supply voltage V
A voltage waveform appears that is lowered by the voltage drop with DD as a reference.

Next, the configuration of the analog calculation section 740 shown in FIG.
This will be explained based on the diagram. This analog calculation section 740 consists of a switched capacitor bond divider, and has a terminal Pro (
3) is connected to the inverting input terminal of the differential integrator 142 via the switching terminal 140, the capacitive element Csl, and the switching element 141, which are connected in series with each other. Both ends are connected to a ground terminal via switching elements 143 and 144.

On the other hand, a signal line ° extending from the terminal PbQ (see FIG. 3) is connected to the inverting input terminal of the differential integrator 1420 via the switching element 145, the capacitive element Cs2, and the switching element 146, which are connected in series with each other. Capacitive element Cs
Both ends of 2 are connected to the ground terminal via switching elements 147 and 148. Between the inverting input terminal and the output terminal 149 of the differential integrator 142, a switching element 150 and a capacitive element CI are connected in parallel with each other.

Furthermore, the inverting/inverting input terminals of the analog comparator 151 are connected to the signal lines extending from the terminals PrQ and PbQ, and the input terminals are connected to the channel select circuit 152.
0 input terminal, and the channel select circuit 152
are switching elements 140.141.143.144.
145.146.147.148 "on", "off"
Select signals φ1, φ2, φKA, and φKB are generated to control the φ1, φ2, φKA, and φKB.

The analog comparator 151 detects that the level of the operated signal is R.
When (k)≧B(k), “H” level, R(k) <B
(k), a polarity signal Sgn(k) of "L" level is output, and select signals φ1, φ2, φKA are generated in accordance with this polarity signal Sgn(k) level.

The voltage level of φKB is determined.

Next, the operation of the analog calculation section 740 having such a configuration will be explained based on the timing chart of FIG. 8.

First, the switching element 150 is turned on by a reset signal φIsT from a reset means (not shown) to discharge unnecessary charges in the capacitive element CI, and then the switching element 150 is turned off again as shown in FIG. The operation begins.

Reference reading section 322 in sensor means 32, base 71! The readout unit 323 outputs the operated signals R(k) and B(k) at a predetermined period as shown in FIG.
1 to t2, the operated signal is R(k)≧
If there is a relationship of B(k), the polarity signal Sgn(k) is “H”
Then, the rectangular wave select signals φl, φ2, φKA, φKB as shown in (B), (C), (D), and (E) in the same figure
occurs. Here, select signals φ1 and φ2, φKA,
φKB occurs at timings that do not become "H" at the same time.

On the other hand, as in the period from time t3 to t4, the operated signal is R.
(k) <B (k), the polarity signal Sgn(
k) becomes "L", and φKB is generated in the select signal φ whose phase is opposite to that from time t1 to t2. Note that the select signals φ1 and φ2 are generated at the same timing regardless of the level of the polarity signal Sgn(k).

These select signals φ1, φ2, φKA, and φKB switch the switching elements 144.148 and 140.1 in the first half period TFI of the period t1 to t2.
47 is turned on, the operated signal R(k) is charged in the capacitive element Csl, and unnecessary charges in the capacitive element C82 are discharged. Next, in the second half period TRI of the period t1 to t2, the switching elements 143 and 141 are turned on, so the charges of the capacitive element Csl and the capacitive element CI are combined, and at the same time, the switching elements 145 and 146 are turned on. Since the switching elements 147 and 148 are turned "off", the operated signal B(k) is supplied to the differential integrator 142 via the capacitive element C32. As a result, the following formula (2)
A charge q(k) shown in is accumulated in the capacitive element CI.

q(k)= On the other hand, as from time t3 to t4, the operated signal is R(k)
In the case of <B (k), the switching elements 144, 148 and 143, 145 are turned on in the first half period TF2 of the period t3 to t4,
The operated signal B(k) is charged in the capacitive element CS2, and unnecessary charges in the capacitive element Csl are discharged. Next, period t3-t
In the second half period TR2 of 4, the switching element 14
7.146 is "on", so capacitive element C32 and capacitive element C.

charges are combined, and at the same time, switching elements 140.141 are turned on, and switching elements 143.141 are turned on.
144 is turned off, the operand word R(k) is supplied to the differential integrator 142 via the capacitive element Csl. As a result, charge q(k) shown in the following equation (3) is accumulated in the capacitive element CI.

q(k) = As is clear from the above equations (°2) and (3), this analog calculation section 740 always generates a charge corresponding to the value obtained by subtracting the operated signal with a small level from the operated signal with a large level. Capacitive element C+I: Since it accumulates, the time-series operand signal R
(1),...R(n), B(1)...B(n)', ), the difference between these signals is calculated as shown in the following equation (4). An absolute value of 1 mH is obtained as a voltage at the output terminal 745.

When the calculation of the above equation (4) is completed, the reference sequencer 322 shifts the shift register of the reference image sensor 320! The signal charge held in 104 is transferred to the female blade shift register section 105.
The analog calculation unit 740 performs the calculation process according to the above equation (4) by transferring charges for one pitch with respect to the signal charges, and reading out the mutually phase-shifted signal charges again in time series. Then, the phase of the signal charges in the shift register sections 104 and 105 is further shifted and this process is repeated. This phase shift corresponds to the above-mentioned relative movement amount 2, and when this movement amount l is sequentially changed, the correlation calculation value can be obtained as the following equation (5), and is detected as a voltage from the output terminal 745. .

sl That is, the above equation (5) corresponds to the above equation (1), and the correlation calculation values H(1), H(2), . . . H(ri) are obtained by analog signal processing.

Next, in the period from time tlo to tll, the previous time t
The same process from 6 to tlO is repeated a predetermined number of times,
A correlation calculation value between the pattern that is sequentially shifted in the shift register section 104 and the pattern of the shift register section 105 that is not softened is calculated.

The above process is! If is the number of shift operations, then it is expressed as, and corresponds to the correlation calculation value [see equation (1)] by the digital signal processing described in the conventional example.

Figures 10(a) to (C) show examples of the signal Vout which is distorted by the output terminal 45 and 45 by eight shift operations. When a pattern of t-eye calculated values that sometimes reaches the minimum value occurs, it can be identified as being in focus, and as shown in (b) in the same figure, the correlation calculated value when f < 4 is When it is the minimum, it is the front focus state, and when it is the minimum when 1>4 as shown in FIG.

As explained above, according to this embodiment, since the correlation calculation value is calculated by analog signal processing, the calculation speed is extremely high, and since the circuit can be unitized, it can be manufactured as a semiconductor integrated circuit device. suitable for.

In particular, the relative accuracy of capacitors in semiconductor integrated circuits is extremely poor, and together with the unitization of circuits, highly accurate calculations become possible.

Furthermore, since the shift register is equipped with a floating gate, the signal charge can be read out repeatedly in a non-destructive manner, eliminating the need for a storage device to store signals of patterns related to the subject image, and allowing a compact phase difference detection device to be installed. can be provided.

Return to Figure 1 again. As described above, the analog calculation section 740 in the analog calculation means 74 performs the correlation calculation 1aH1.
') is calculated, and the correlation calculation value H1) is manually input to the comparator 78 via the sample and hold circuit 76 or directly.

The analog calculation means 74 periodically outputs the correlation calculation value Hi)
l' is an integer greater than or equal to 1) are output sequentially as H(1), H(2), etc., but the sample controlled by the timing pulse generator 80 is input to the non-inverting input terminal of the comparator 78. The hold circuit 76 holds the correlation calculation value outputted from the analog calculation means 74 last time. Here, the first eye calculation value outputted last time from the analog calculation means 74 is H(
β=1), and the correlation calculation value output this time is Hi), then Hl! -1) and Hi) are compared by a comparator 78.

The control circuit 86 sends a control signal to the motor drive circuit 6 based on the comparison result of the comparator 78 to drive and control the DC motor 66 which is a drive means for driving the subfocus tube of the zoom lens 20.
Output to 8.

Next, the contents of the automatic focus control processing program executed by the control circuit 86 are shown in FIG. In the figure, when the program is started, the timing pulse generator 80 receives a control signal from the control circuit 86 and outputs a timing pulse to the sample and hold circuit 76, and the sample and hold circuit 76 outputs a timing pulse from the analog calculation means 74. Sample and hold the correlation calculation value H(β) at a predetermined period (
Step 500). Next, a comparator 78 compares the correlation calculation value H(f-1) previously output from the analog calculation means 74 held by the sample hold circuit 76 with the correlation calculation value Hi) output this time. (step 501).

If it is determined in step 501 that H(β-1)<H(β), the count value J of the soft counter in the control circuit 86 is incremented, and the process returns to step 501 (step 502).

Here, the soft counter calculates the deviation amount (relative movement amount) in pixel units between the reference image sensor 320 and the standard image sensor 321 when performing analog correlation calculation by the analog calculation means 74 (in this embodiment, j = 1 to 9). ).

If it is determined in step 501 that H1'-1) > H (the contents of the soft counter at that time)
is captured (step 503), and defocus calculation is performed (step 504). The defocus calculation is performed as follows. That is, it is assumed that at the time of focusing, the amount of relative movement is small and the correlation calculation 1aH(β) is minimized. If the relative movement amount when the correlation calculation value H (R) is the minimum when out of focus is J, then after the relative movement where the eye opening calculation 1mH (β) at 71 when out of focus is the maximum,
Xl The difference n between the amount of movement and the amount of relative movement at which the correlation calculation 1aH (1) at the time of focusing is the maximum is n = - (j 1) ... (7) (n takes a positive or negative sign .) becomes. Next, the focus lens group 2 of the zoom lens 20
If the defocus amount of 0A (Fig. 1) is Δd1 and the defocus amount per pixel on the image sensor 320 and 321 where the correlation calculation value H (β) is maximum is ΔX, then the defocus amount Δd is Δd=△ x-n...(8)

Incidentally, in the above equation (7), in the present embodiment, ?=5. Further, the sign n indicates the direction in which the focus lens group 2OA is driven in the optical axis direction of the imaging optical system, and corresponds to the rotational driving direction of the DC motor 66.

The control circuit 86 calculates the defocus amount Δd using the above equations (7) and (8), and further controls the motor 66 to move the focus lens group 2OA on its optical axis to the in-focus position according to the defocus amount. A control signal for driving the motor is output to the motor drive circuit 68 (step 505).

As a result, the focus lens group 20A1 and the zoom lens 20 are adjusted to be in focus.

In the above embodiments, the automatic focus adjustment device according to the present invention is applied to a camera, but the present invention is not limited to this and can be applied to other optical devices, such as a distance measuring device. Of course.

〔Effect of the invention〕

As explained above, in the present invention, it is determined whether or not the imaging optical system is in a focused state by detecting the relative positions of a pair of optical images of a subject. In an automatic focusing device that performs focusing by driving the imaging optical system in the direction of its optical axis based on the target position until it reaches the in-focus state, multiple photoelectric conversion elements forming one pixel are arranged in a line. The pair of sensors photoelectrically convert the pair of optical images, and the photoelectric conversion generates an analog electrical signal corresponding to one optical image and an analog corresponding to the other optical image. A sensor means for non-destructively outputting an electric wet field while shifting it pixel by pixel at a predetermined period, and an analog calculation means for performing a correlation calculation on a pair of analog electric signals outputted by the sensor means and outputting a correlation calculation value. a comparison means for sequentially comparing the magnitudes of the correlation calculation values outputted in time series from the analog calculation means; a drive means for driving the imaging optical system in the driving direction; and an output signal of the comparison means is taken in; Based on the comparison output, the pixel position of the sensor means at which the correlation calculation value outputted from the analog calculation means is the minimum is determined, and the deviation of the pixel position from the pixel position when the pixel position is in focus is calculated. and a control means for controlling the driving means to calculate the defocus amount from the defocus amount and drive the imaging optical system to the in-focus position on the optical axis according to the defocus amount, According to the present invention, it is possible to perform focusing control of an imaging optical system on a subject with a simple configuration at high speed and with high precision.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of a camera equipped with an automatic focus adjustment device to which the present invention is applied, and FIG. 2 is a block diagram showing the configuration of an embodiment of the phase difference detection device in FIG. 1. 3 is a circuit diagram showing the specific circuit configuration of the embodiment shown in FIG. 2, and FIG. 4 is an explanation showing the arrangement of the light receiving section, storage section, shift register section, and floating gate of the reference section and reference section. 5 is a vertical cross-sectional view schematically showing the main parts of the light receiving section, the storage section, the shift register section, and the floating gate. FIG. 6 is a timing chart for explaining the circuit operation of FIG. 3. 7 is a circuit diagram showing the specific circuit configuration of the analog calculation section in FIG. 3, FIG. 8 is a timing chart showing the operation of the analog calculation section, and FIG.
The figure is an explanatory diagram for explaining the calculation process of the correlation calculation value, Fig. 10 is an explanatory diagram showing the principle for determining the in-focus state from the correlation calculation value, and Fig. 11 is an explanatory diagram showing the principle of determining the focus state from the correlation calculation value. FIG. 12 is a flowchart showing the contents of a control processing program, FIG. 12 is a schematic configuration diagram showing the configuration of a conventional automatic focus adjustment device, and FIG. 13 is a block diagram showing the configuration of the phase difference detection device in FIG. 20...Zoom lens, 32...Sensor means,
68... Motor drive circuit, 74... Analog calculation means, 76... Sampling hold circuit,
78... Comparator, 86... Control circuit.

Claims (1)

[Claims] It is determined whether the imaging optical system is in a focused state by detecting the relative position of a pair of optical images of a subject, and if the imaging optical system is not in a focused state, based on the relative position. In an automatic focusing device that performs focusing by driving an imaging optical system in the direction of its optical axis until it reaches a focused state, a plurality of photoelectric conversion elements forming one pixel are arranged in a line. the pair of sensors photoelectrically converts the pair of optical images and generates an analog electrical signal corresponding to one optical image and an analog electrical signal corresponding to the other optical image generated by the photoelectric conversion. A sensor means that non-destructively outputs an output while shifting each pixel at a predetermined period; an analog calculation means that performs a correlation calculation on a pair of analog electrical signals outputted from the sensor means and outputs a correlation calculation value; a comparing means for sequentially comparing the magnitudes of the correlation calculation values outputted from the means in time series; a driving means for driving the imaging optical system in the direction of its optical axis; Based on this, the pixel position of the sensor means at which the correlation calculation value outputted from the analog calculation means is minimum is determined, and the amount of deviation from the pixel position when the pixel position is in focus is calculated, and defocusing is performed from the amount of deviation. control means for calculating the defocus amount and controlling the driving means to drive the imaging optical system to a focusing position on its optical axis according to the defocus amount;
An automatic focus adjustment device comprising: