JPH01220842A - Semiconductor internal matching device - Google Patents

Semiconductor internal matching device

Info

Publication number
JPH01220842A
JPH01220842A JP63047309A JP4730988A JPH01220842A JP H01220842 A JPH01220842 A JP H01220842A JP 63047309 A JP63047309 A JP 63047309A JP 4730988 A JP4730988 A JP 4730988A JP H01220842 A JPH01220842 A JP H01220842A
Authority
JP
Japan
Prior art keywords
marker
surface conductor
thin metal
bonding
chip capacitor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63047309A
Other languages
Japanese (ja)
Inventor
Akira Kumagai
亮 熊谷
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP63047309A priority Critical patent/JPH01220842A/en
Publication of JPH01220842A publication Critical patent/JPH01220842A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
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    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
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    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
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    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49112—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting a common bonding area on the semiconductor or solid-state body to different bonding areas outside the body, e.g. diverging wires
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    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
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    • H01L2924/30111—Impedance matching

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To restrain the irregularity of length, and obtain stable matching characteristics, by providing each surface conductor of two chip capacitors for input and output, with positioning markers to be used at the time of fixing terminals on one side of a plurality of metal thin wires. CONSTITUTION:When a bonding position is to be set, for example, at a center line position in the longitudinal direction of a bonding region 13c, a third marker 14c and a eighth marker 15c corresponding with the maker 14c are set as indexes, and Au wires having specified dimensions with a specified interval on a prolonged line of the marks are respectively subjected to heat compression bonding. A first and a second marker groups 14, 15 are formed on the respective surface conductors of chip capacitors 11 having capacitances rated in various kinds.

Description

【発明の詳細な説明】 ［産業上の利用分野］ 本発明はマイクロ周波数帯域において、常に安定した整
合特性を実現するために金属細線の取付は位置を正確に
規定し得るように構成した半導体内部整合装置に関する
ものである。[Detailed Description of the Invention] [Industrial Application Field] The present invention is directed to a semiconductor device constructed in such a way that the attachment position of a thin metal wire can be precisely defined in order to always achieve stable matching characteristics in the micro frequency band. The present invention relates to a matching device.

［従来の技術］ 従来のＧａＡｓ　−ＭＥＳＦＥＴ用の５０Ω内部整合回
路は、−最的に、ＧａＡｓ　−ＦＥＴチップのゲート及
びドレインの画電極と内部整合用チップコンデンサの表
面導体との間をＡｕ等からなる金属細線でボンディング
することにより形成されている。この金属細線のボンデ
ィングは、目視によってボンディング位置を位置決めす
ることにより行われる。なお、金属細線は５０Ω内部整
合回路においてコイルとして機能する。[Prior Art] A conventional 50Ω internal matching circuit for a GaAs-MESFET is constructed using a conductor made of Au or the like between the gate and drain picture electrodes of the GaAs-FET chip and the surface conductor of the chip capacitor for internal matching. It is formed by bonding with thin metal wires. This bonding of the thin metal wires is performed by visually determining the bonding position. Note that the metal thin wire functions as a coil in the 50Ω internal matching circuit.

そして、内部整合用チップコンデンサ及び金属細線が夫
々有する回路定数、即ち、静電容量Ｃ及びインダクタン
スしどの組合せによって、指定周波数において内部整合
がとられている。Then, internal matching is achieved at a designated frequency by a combination of circuit constants of the internal matching chip capacitor and the thin metal wire, that is, the capacitance C and the inductance.

［発明が解決しようとする課題］ しかしながら、上述した従来のＧａＡｓ　−ＭＥＳＦＥ
Ｔ用の５０Ω内部整合回路においては、以下に述べるよ
うな問題点がある。[Problem to be solved by the invention] However, the above-mentioned conventional GaAs-MESFE
The 50Ω internal matching circuit for T has the following problems.

即ち、整合回路を構成するチップコンデンサ及び金属細
線は回路定数として、夫々に固有の静電容量Ｃ及びイン
ダクタンスＬを有しており、このためにこれらの回路定
数において許容範囲を超えた誤差があると、指定周波数
での整合にズレが生じる。In other words, the chip capacitors and thin metal wires that make up the matching circuit each have their own specific capacitance C and inductance L as circuit constants, and for this reason, there are errors in these circuit constants that exceed the allowable range. This will cause a mismatch in matching at the specified frequency.

ここでチップコンデンサの容量値は離散的な値に規格化
されており、多様の値をとり得ない。また、このように
規格化された容量値を有するチップコンデンサにおいて
、その容量値の誤差は極めて小さく、通常は許容範囲を
十分に満たしている。Here, the capacitance value of a chip capacitor is standardized to a discrete value and cannot take on a variety of values. Furthermore, in a chip capacitor having such a standardized capacitance value, the error in the capacitance value is extremely small and usually satisfies the allowable range.

従って、装置を駆動する際に所定の内部整合を実現する
には、いきおい金属細線のボンディング位置の位置決め
精度に大きく依存せざるを得ない。Therefore, in order to achieve a predetermined internal alignment when driving the device, it is necessary to rely largely on the positioning accuracy of the bonding position of the thin metal wire.

金属細線のボンディング位置にバラツキが生じると、必
然的にその長さにもバラツキが生じる。このような金属
細線のバラツキはインダクタンスＬの大きさのバラツキ
となって現れ、超高周波数帯における整合状態のズレに
大きく影響してくる。If there are variations in the bonding positions of the thin metal wires, there will inevitably be variations in their lengths. Such variations in the thin metal wire appear as variations in the size of the inductance L, and greatly influence the deviation in the matching state in the ultra-high frequency band.

そこで、整合状態のズレを回避するには、チップコンデ
ンサの表面導体上において金属細線のボンデインク位置
を正確に規定して、その長さのバラツキを十分に抑える
必要がある。Therefore, in order to avoid deviations in the matching state, it is necessary to accurately define the bonding ink position of the thin metal wire on the surface conductor of the chip capacitor, and to sufficiently suppress variations in the length.

しかし、現状において、金属細線のボンディング位置の
位置決めは上述したように自分量に基いて行れるので、
正確な位置決めを行うことが困難であり、ボンディング
位置がバラツキ易い。従って、ボンディングされた金属
細線の長さに必然的にバラツキが生じインダクタンスＬ
の再現性が悪く、このために安定した整合状態を実現す
ることが困難である。However, at present, the bonding position of the thin metal wire can be determined based on its own amount as described above.
It is difficult to perform accurate positioning, and bonding positions tend to vary. Therefore, the length of the bonded thin metal wire inevitably varies, and the inductance L
reproducibility is poor, making it difficult to achieve a stable matching state.

本発明はかかる問題点に鑑みてなされたものであって、
常に安定した整合状態を得るために、金属細線の取付は
位置を正確に規定し得るように構成した半導体内部整合
装置を提供することを目的とする。The present invention has been made in view of such problems, and includes:
It is an object of the present invention to provide a semiconductor internal alignment device configured such that the attachment position of the thin metal wire can be accurately defined in order to always obtain a stable alignment state.

［課題を解決するための手段］ 本発明に係る半導体内部整合装置は、表面導体を有する
入出力用の２個のチップコンデンサと前記表面導体と半
導体装置の所定端子とを夫々接続する複数の金属細線と
を備え、前記入出力用の２個のチップコンデンサの静電
容量と前記複数の金属細線のインダクタンスの組合せに
よってマイクロ波周波数帯域における電気的整合を行う
半導体内部整合装置において、前記入出力用の２個のチ
ップコンデンサの各表面導体に、前記複数の金属細線の
一方の端子を夫々取り付ける際の位置決め用のマーカを
設けたことを特徴とする。[Means for Solving the Problems] A semiconductor internal matching device according to the present invention includes two chip capacitors for input/output having a surface conductor, and a plurality of metals each connecting the surface conductor and a predetermined terminal of a semiconductor device. A semiconductor internal matching device comprising a thin wire and performing electrical matching in a microwave frequency band by a combination of the capacitance of the two chip capacitors for input and output and the inductance of the plurality of thin metal wires, Each surface conductor of the two chip capacitors is provided with a marker for positioning when attaching one terminal of the plurality of thin metal wires, respectively.

［作用］ 以上のように構成された本発明の半導体内部整合装置に
よれば、複数の金属細線の一方の端部を入出力用の２個
のチップコンデンサの夫々の表面導体に取付ける際、こ
れらの表面導体に夫々設けられたマーカを指標としてそ
の取付は位置を正確に位置決めすることができる。この
ために、前記複数の金属細線の一方の端部を取付は予定
位置に正確に取付けることができるので、前記複数の金
属細線の取付は位置のバラツキ、即ち長さのバラツキが
抑制され、前記複数の金属細線において所望のインダク
タンスを高精度で得ることができる。[Function] According to the semiconductor internal matching device of the present invention configured as described above, when one end of a plurality of thin metal wires is attached to the surface conductor of each of two chip capacitors for input/output, these The attachment position can be accurately determined using the markers provided on the surface conductors of each as an index. For this reason, one end of the plurality of thin metal wires can be accurately attached to a predetermined position, so that the dispersion in the attachment position of the plurality of thin metal wires, that is, the variation in length, is suppressed. A desired inductance can be obtained with high precision in a plurality of thin metal wires.

故に、本発明の半導体内部整合装置は、伝送系に対して
常に安定した整合特性を提供することができる。Therefore, the semiconductor internal matching device of the present invention can always provide stable matching characteristics to the transmission system.

［実施例］ 以下、添付の図面を参照して、本発明を５０Ω内部整合
回路に適用した実施例について具体的に説明する。[Example] Hereinafter, an example in which the present invention is applied to a 50Ω internal matching circuit will be specifically described with reference to the accompanying drawings.

先ず、第１図を参照して、本発明の整合回路を構成する
チップコンデンサについて説明する。なお、第１図（ａ
）はチップコンデンサの斜視図、また第１図（ｂ）はそ
の要部を部分的に拡大した平面図である。First, with reference to FIG. 1, a chip capacitor constituting the matching circuit of the present invention will be explained. In addition, Fig. 1 (a
) is a perspective view of a chip capacitor, and FIG. 1(b) is a partially enlarged plan view of the main part thereof.

第１図（ａ）において、チップコンデンサ１１は直方形
状の誘電体基板１２、並びにこの誘電体基板１２の対向
する両表面に形成された上面側の表面導体（Ａｕ）１３
及び下面側の表面導体Ａｕ（図示せず）とで構成されて
いる。そして、長方形状の表面導体１３は抵抗ペースト
〈紫色）を線状に塗布印刷することにより、長手方向に
て相互に対向する比較的小面積の第１−及び第２のマー
カ形成領域１３ａ、１３ｂ及びこれらの領域１３ａ。In FIG. 1(a), a chip capacitor 11 includes a rectangular dielectric substrate 12, and upper surface conductors (Au) 13 formed on both opposing surfaces of the dielectric substrate 12.
and a surface conductor Au (not shown) on the lower surface side. The rectangular surface conductor 13 is formed by applying and printing a resistance paste (purple) in a line to form first and second marker forming regions 13a and 13b of relatively small area facing each other in the longitudinal direction. and these areas 13a.

１３ｂとで挾まれた大面積のホンディング領域１３ｃと
に区分されている。13b and a large-area honding area 13c sandwiched between the areas 13b and 13c.

第１のマーカ形成領域１３ａにおいては、表面導体１３
の長手方向に沿って所定長を有する細いストライプ状の
第１乃至第５のマーカ１４ａ乃至１４ｅが、第１図（ｂ
）に示すように、相互間に間隔を置いて平行に形成され
ている。また、これらの第１乃至第５のマーカ１４ａ乃
至１４ｅにより第１のマーカ群１４が構成される。一方
、第２のマーカ形成領域１３ｂにおいては、上述した第
１のマーカ形成領域１３ａの場合と同様にして第６乃至
第１０のマーカ１５ａ乃至１５ｅが夫々形成されている
。これらの第６乃至第１０のマーカ１５ａ乃至１５ｅは
、第１乃至第５のマーカ１４ａ乃至１４ｅと夫々対応し
ており、第２のマーカ群１５を構成している。なお、第
１及び第２のマーカ群１４．１５は、既述した抵抗ペー
ストの塗布印刷工程において形成される。In the first marker forming region 13a, the surface conductor 13
First to fifth markers 14a to 14e in the form of thin stripes each having a predetermined length along the longitudinal direction of FIG.
), they are formed parallel to each other with a space between them. Further, the first to fifth markers 14a to 14e constitute a first marker group 14. On the other hand, in the second marker forming area 13b, sixth to tenth markers 15a to 15e are formed, respectively, in the same manner as in the first marker forming area 13a described above. These sixth to tenth markers 15a to 15e correspond to the first to fifth markers 14a to 14e, respectively, and constitute a second marker group 15. Note that the first and second marker groups 14 and 15 are formed in the resistor paste coating and printing process described above.

次に、第１図（ｂ）を参照して第１のマーカ群１４を例
にとって第１乃至第５のマーカ１４ａ乃至１４ｅの形成
位置について説明する。なお、第１図（ｂ）は第１図（
ａ）においてａで指示した部分を平面図として拡大して
示したものである。Next, the formation positions of the first to fifth markers 14a to 14e will be explained using the first marker group 14 as an example with reference to FIG. 1(b). Note that Fig. 1(b) is similar to Fig. 1(b).
The part indicated by a in a) is shown in an enlarged plan view.

即ち、表面導体１３の幅を１としたとき、第１乃至第５
のマーカ１４ａ乃至１４ｅは、第１図（ｂ）に示す表面
導体１３の左端から１／４．１／３．１／２．２／３及
び３／４の距離の位置に夫々形成されている。第１乃至
第５のマーカ１４ａ乃至１４ｅに夫々対応する第６乃至
第１０のマーカ１５ａ乃至１５ｅについても、これらと
同様の各位置に形成されている。That is, when the width of the surface conductor 13 is 1, the first to fifth
The markers 14a to 14e are formed at distances of 1/4.1/3.1/2.2/3 and 3/4 from the left end of the surface conductor 13 shown in FIG. 1(b), respectively. . Sixth to tenth markers 15a to 15e corresponding to first to fifth markers 14a to 14e, respectively, are also formed at similar positions.

従って、例えば、ボンディング領域１３ｃの長手方向に
おける中心線位置にボンディング位置が設定された場合
には、第３のマーカ１４ｃとこれに対応する第８のマー
カ１５ｃとを指標にして、これらの延長線上に所定間隔
をおいて所定寸法を有するＡｕワイヤ（第２図参照）を
熱圧着により夫々ボンディングする。なお、第１図に示
した第１及び第２のマーカ群１４．１５は、多数種類に
規格化された容量を有するチップコンデンサ１１の夫々
の表面導体１３に形成されている。Therefore, for example, when the bonding position is set at the center line position in the longitudinal direction of the bonding area 13c, the third marker 14c and the corresponding eighth marker 15c are used as indicators, and the bonding position is set on the extension line of the third marker 14c and the corresponding eighth marker 15c. Au wires having predetermined dimensions (see FIG. 2) are bonded to each other by thermocompression bonding at predetermined intervals. The first and second marker groups 14 and 15 shown in FIG. 1 are formed on the surface conductor 13 of each chip capacitor 11 having a large number of standardized capacitances.

また、ＧａＡｓ−ＭＥＳＦＥＴが異なる幾っがの特定の
マイクロ波周波数帯（例えば、数ＧＨｚ帯）で駆動され
る場合、整合回路において使用される周波数帯域に応じ
て入出力側との間の電気的整合をとる必要がある。In addition, when a GaAs-MESFET is driven in several different specific microwave frequency bands (for example, several GHz band), the electrical connection between the input and output sides depends on the frequency band used in the matching circuit. It is necessary to achieve consistency.

一般に、より高い周波数帯域を使用する場合、この周波
数帯域での電気的整合をとるために、整合回路において
は、チップコンデンサ１１の容量Ｃ及びＡｕワイヤのイ
ンダクタンスＬを共により小さく設定する必要がある。Generally, when using a higher frequency band, it is necessary to set both the capacitance C of the chip capacitor 11 and the inductance L of the Au wire smaller in the matching circuit in order to achieve electrical matching in this frequency band. .

このような場合には、容量が一層小さいチップコンデン
サ１１を使用する。また、これと同時にインダクタンス
Ｌを一層小さく抑えるために、チップコンデンサ１１の
表面導体１３においてＡｕワイヤの長さを一層短くとる
ことができる、例えば第２のマーカ１４ｂと第７のマー
カ１５ｂ組合せ（出力用チップコンデンサの場合）又は
第５図のマーカ１４ｅと第１０のマーカ１５ｅの組合せ
（入力用チップコンデンサの場合）を選択し、これらの
選択されたマーカを指標にしてＡｕワイヤをボンディン
グする。In such a case, a chip capacitor 11 with a smaller capacitance is used. At the same time, in order to further reduce the inductance L, the length of the Au wire in the surface conductor 13 of the chip capacitor 11 can be made even shorter. For example, the combination of the second marker 14b and the seventh marker 15b (output (in the case of an input chip capacitor) or a combination of the marker 14e and the tenth marker 15e in FIG. 5 (in the case of an input chip capacitor), and bond the Au wire using these selected markers as indicators.

このように、実際上の要求を満たすためには、−般に、
第１のマーカ群１４と第２のマーカ群１５との間で、使
用される周波数帯域に応じて第１乃至第５のマーカ１４
ａ乃至１４ｅと第６乃至第１０のマーカ１５ａ乃至１５
ｅとの組合せを適宜選択し、組合せの選択されたマーカ
を指標にしてボンディングを行うようにすればよい。Thus, in order to meet practical requirements - generally,
Between the first marker group 14 and the second marker group 15, the first to fifth markers 14 are arranged according to the frequency band used.
a to 14e and sixth to tenth markers 15a to 15
What is necessary is to appropriately select a combination with e and perform bonding using the selected marker of the combination as an index.

第２図は上述した手法を使用して入出力用チップコンデ
ンサとＧａＡｓ　−ＭＥＳＦＥＴとをＡｕワイヤで夫々
ボンディング接続した５０Ω整合回路の構成例を示した
ものである。FIG. 2 shows a configuration example of a 50Ω matching circuit in which an input/output chip capacitor and a GaAs-MESFET are connected by bonding with Au wires using the above-described method.

第２図において、ストリップ導体２３ａと接続端子部２
３ｂとが表面に形成された入力用アルミナ基板２３と、
ストリップ導体２４ａと接続端子部２４ｂとが同様にし
て表面に形成された出力用アルミナ基板２４との間に、
入力用チップコンデンサ１１ａ、出力用チップコンデン
サｌｌｂ及びＧａＡｓ　−ＭＥＳＦＥＴ２１とが配設さ
れている。In FIG. 2, the strip conductor 23a and the connecting terminal portion 2
3b is formed on the surface of the input alumina substrate 23;
Between the strip conductor 24a and the output alumina substrate 24 having the connecting terminal portion 24b formed on the surface in the same manner,
An input chip capacitor 11a, an output chip capacitor llb, and a GaAs-MESFET 21 are arranged.

ここで、ＧａＡｓ　−ＭＥＳＦＥＴ２１の５０Ω内部整
合回路は入力用チップコンデンサｌｌａと出力用チップ
コンデンサ１１ｂ、並びにこれらのチップコンデンサｌ
ｌａ、ｌｌｂとＦＥＴ２１とを接続しているＡｕワイヤ
群２２ａ、２２ｂとで構成されている。Here, the 50Ω internal matching circuit of the GaAs-MESFET 21 includes an input chip capacitor lla, an output chip capacitor 11b, and these chip capacitors l.
It is composed of a group of Au wires 22a and 22b connecting the FET 21 with the FET 21 and the FET 21.

Ａｕワイヤ群２２ａ、２２ｂの接続構成について具体的
に説明する。即ち、Ａｕワイヤ群２２ａは、入力用チッ
プコンデンサｌｌａの表面導体の一方の側とＧａＡｓ　
−ＭＥＳＦＥＴ２１のゲート端子群２１ａとを夫々接続
している。また、Ａｕワイヤ群２２ｂは、ＧａＡｓ　−
ＭＥＳＦＥＴ２１のトレイン端子群２１ｂと出力用チッ
プコンデンサｌｌｂの表面導体の一方の側とを夫々接続
している。The connection configuration of the Au wire groups 22a and 22b will be specifically described. That is, the Au wire group 22a is connected to one side of the surface conductor of the input chip capacitor lla and the GaAs
- They are connected to the gate terminal group 21a of the MESFET 21, respectively. Moreover, the Au wire group 22b is made of GaAs −
The train terminal group 21b of the MESFET 21 is connected to one side of the surface conductor of the output chip capacitor llb, respectively.

なお、入力用アルミナ基板２３の伝送路と入力用チップ
コンデンサｌｌａは、接続端子部２３ｂと表面導体の他
方の側とを夫々接続しているＡｕワイヤ群２２ｃで電気
的に接続されている。一方、出力用アルミナ基板２４の
伝送路と出力用チップコンデンサ１−１ｂも、接続端子
部２４ｂと表面導体の他方の側とを夫々接続しているＡ
ｕワイヤ群２２ｄで同様にして電気的に接続されている
。Note that the transmission path of the input alumina substrate 23 and the input chip capacitor lla are electrically connected by Au wire groups 22c that respectively connect the connection terminal portion 23b and the other side of the surface conductor. On the other hand, the transmission path of the output alumina substrate 24 and the output chip capacitor 1-1b also connect the connecting terminal portion 24b and the other side of the surface conductor, respectively.
They are electrically connected in the same way by the u wire group 22d.

Ａｕワイヤ群２２ａ、２２ｂ等は、いずれも所定のイン
ダクタンスＬを実現するために、使用されるマイクロ波
周波数帯域に応じて選択されたマーカを指標にして、入
出力用チップコンデンサ１１ａ、ｌｌｂの夫々の表面導
体の所定位置に正確にボンディングされている。このた
めに、上記構成の整合回路は第２図に示した伝送系にお
いて常に安定した整合特性を提供することができる。In order to achieve a predetermined inductance L, the Au wire groups 22a, 22b, etc. are connected to the input/output chip capacitors 11a, llb, respectively, using markers selected according to the microwave frequency band used as indicators. are precisely bonded to the predetermined positions of the surface conductors. Therefore, the matching circuit having the above configuration can always provide stable matching characteristics in the transmission system shown in FIG. 2.

ここにおいて、上述した実施例では、チップコンデンサ
１１の表面導体１３を区分して得られた第１及び第２の
マーカ形成領域１３ａ、１３ｂにのみ第１及び第２のマ
ーカ群１４．１５を夫々形成するようにしているが、本
発明はこのような構成に限定されるものではないことは
勿論である。Here, in the embodiment described above, the first and second marker groups 14 and 15 are respectively placed only in the first and second marker forming regions 13a and 13b obtained by dividing the surface conductor 13 of the chip capacitor 11. However, it goes without saying that the present invention is not limited to this configuration.

即ち、表面導体１３を区分せず、一方の端部の複数の所
定箇所から対応する他方の端部の複数の所定箇所へと夫
々伸びる複数の直線又は点線等でマーカを構成すること
ができる。また、表面導体１３に格子状のパターンを形
成し、これをマーカとして使用することもできる。この
ような場合、Ａｕワイヤを直線又は点線で構成されるマ
ーカの近傍位置に、又は格子状パターンにおける交叉点
の近傍位置にボンディングすることでＡｕワイヤホンデ
ィングの位置決めを正確に行うことができる。That is, without dividing the surface conductor 13, the markers can be configured with a plurality of straight lines or dotted lines extending from a plurality of predetermined locations on one end to a plurality of corresponding predetermined locations on the other end. It is also possible to form a grid pattern on the surface conductor 13 and use it as a marker. In such a case, the Au wire bonding can be accurately positioned by bonding the Au wire near a marker made of straight or dotted lines or near a crossing point in a grid pattern.

この外に、マーカは、上述したストライプ状等の他に形
状が簡単なスポット状に形成することもできる。In addition to this, the marker can also be formed in a simple spot shape other than the above-mentioned stripe shape.

更に、本発明の半導体内部整合装置に使用される半導体
装置は、上述した実施例におけるＧａＡｓ−ＭＥＳＦＥ
Ｔに限定されるものではないことは勿論である。Furthermore, the semiconductor device used in the semiconductor internal matching device of the present invention is the GaAs-MESFE in the above-mentioned embodiment.
Of course, it is not limited to T.

［発明の効果］ 以上、説明したように本発明によれば、入出力の２個の
チップコンデンサの夫々の表面導体にマーカを設けるよ
うに構成したので、このマーカを指標にして、コイルを
構成する複数の金属細線の一方の端部を夫々の表面導体
の所定位置に正確に位置決めして取付けることができ、
このために取付は位置のバラツキを抑制することができ
、前記複数の金属細線において所望のインダクタンスを
高精度で得ることができる。故に、伝送系において、使
用する周波数帯域に応じて常に安定した整合特性を実現
することができる。[Effects of the Invention] As explained above, according to the present invention, since a marker is provided on the surface conductor of each of the two input/output chip capacitors, the coil can be configured using this marker as an index. One end of a plurality of thin metal wires can be accurately positioned and attached to a predetermined position on each surface conductor,
Therefore, variations in the mounting position can be suppressed, and a desired inductance can be obtained with high precision in the plurality of thin metal wires. Therefore, in the transmission system, stable matching characteristics can always be achieved depending on the frequency band used.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明の実施例に係る５０Ωの整合回路に使用
されるチップコンデンサにおいてその表面導体にマーカ
が設けられた状態を示す図であり、第１図（ａ）はチッ
プコンデンサの斜視概略図、第１図（ｂ）は第１図（ａ
）においてａで指示した部分を拡大して示す平面図、第
２図は第１図に示したチップコンデンサを５０Ωに整合
回路に適用した場合の構成を示す要部の斜視図である。 １１、ｌｌａ、ｌｌｂ；チップコンデンサ、１２；誘電
体基板、１３；表面導体、１３ａ；第１のマーカ形成領
域、１３ｂ；第２のマーカ形成領域、１３ｃ；ボンディ
ング領域、１４；第１のマーカ群、１５；第２のマーカ
群、２１：ＧａＡｓ−ＭＥＳＦＥＴ、２１ａ；ゲート端
子群、２１ｂ；ドレイン端子群、２２ａ乃至２２ｄ；Ａ
ｕワイヤ群FIG. 1 is a diagram showing a state in which a marker is provided on the surface conductor of a chip capacitor used in a 50Ω matching circuit according to an embodiment of the present invention, and FIG. 1(a) is a schematic perspective view of the chip capacitor. Figure 1(b) and Figure 1(a)
) is an enlarged plan view showing the part indicated by a, and FIG. 2 is a perspective view of the main part showing the configuration when the chip capacitor shown in FIG. 11, lla, llb; chip capacitor; 12; dielectric substrate; 13; surface conductor; 13a; first marker formation region; 13b; second marker formation region; 13c; bonding region; 14; first marker group , 15; second marker group, 21: GaAs-MESFET, 21a; gate terminal group, 21b; drain terminal group, 22a to 22d; A
u wire group

Claims (1)

【特許請求の範囲】[Claims] （１）表面導体を有する入出力用の２個のチップコンデ
ンサと前記表面導体と半導体装置の所定端子とを夫々接
続する複数の金属細線とを備え、前記入出力用の２個の
チップコンデンサの静電容量と前記複数の金属細線のイ
ンダクタンスの組合せによってマイクロ波周波数帯域に
おける電気的整合を行う半導体内部整合装置において、
前記入出力用の２個のチップコンデンサの各表面導体に
、前記複数の金属細線の一方の端子を夫々取り付ける際
の位置決め用のマーカを設けたことを特徴とする半導体
内部整合装置。(1) Two chip capacitors for input/output each having a surface conductor and a plurality of thin metal wires respectively connecting the surface conductor and a predetermined terminal of a semiconductor device; In a semiconductor internal matching device that performs electrical matching in a microwave frequency band by a combination of capacitance and inductance of the plurality of thin metal wires,
A semiconductor internal matching device characterized in that each surface conductor of the two chip capacitors for input/output is provided with a marker for positioning when attaching one terminal of the plurality of thin metal wires, respectively.
JP63047309A 1988-02-29 1988-02-29 Semiconductor internal matching device Pending JPH01220842A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63047309A JPH01220842A (en) 1988-02-29 1988-02-29 Semiconductor internal matching device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63047309A JPH01220842A (en) 1988-02-29 1988-02-29 Semiconductor internal matching device

Publications (1)

Publication Number Publication Date
JPH01220842A true JPH01220842A (en) 1989-09-04

Family

ID=12771694

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63047309A Pending JPH01220842A (en) 1988-02-29 1988-02-29 Semiconductor internal matching device

Country Status (1)

Country Link
JP (1) JPH01220842A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2011148819A1 (en) 2010-05-28 2011-12-01 日本碍子株式会社 Impedance matching element

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2011148819A1 (en) 2010-05-28 2011-12-01 日本碍子株式会社 Impedance matching element
US8878625B2 (en) 2010-05-28 2014-11-04 Ngk Insulators, Ltd. Impedance matching device

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