JPH01220581A - Noise reducer - Google Patents

Abstract

PURPOSE:To efficiently improve an S/N and to prevent resolution from being deteriorated by providing a limiter circuit to set the feedback coefficient of a coefficient multiplication circuit variably and to lower an output level when the absolute value of the level of an error signal exceeds a prescribed level. CONSTITUTION:In an image signal with a low S/N, a control circuit 8 sets a large feedback coefficient for the coefficient multiplication circuit 4, and sets an input/output characteristic with a high limiter level on the limiter circuit 7 corresponding to the above. Thereby, the circuit 7 passes a noise component sufficiently, and a large feedback quantity is supplied to the circuit 4, and the S/N is improved, and picture quality can be improved remarkably. When the S/N is large, the circuit 8 sets a small feedback coefficient on the circuit 4, and sets the input/output characteristic with a low limiter level on the circuit 7. In such a way, the circuit 7 passes the noise component with a low level, and the differential signal of an image signal can be suppressed sufficiently, and the feedback quantity of the circuit 4 is reduced, then, the resolution can be prevented from being deteriorated. In such a way, it is possible to set the feedback coefficient of the circuit 4 and the input/output characteristic of the circuit 7 from the level of the S/N of an input image signal, and to obtain the image with superior picture quality.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a noise reducer suitable for reducing noise in image signals.

[Conventional technology]

As a noise reduction circuit for an image signal, a so-called noise reducer that utilizes the correlation between lines, fields, frames, etc. in an image signal is often used. In addition, due to recent advances in semiconductor technology and the development of high-speed A/D (analog/digital) converters, D/A (digital/analog) converters, and large-capacity memories that can be applied to image signal processing, etc. It has also become possible to realize a noise reducer using digital technology. In particular, by using such a large-capacity memory as a delay circuit, it becomes possible to perform field and frame delays for image signals, and practical use of noise reducers that utilize field correlation and frame correlation, which were previously impossible with analog circuits. Now you can.

Regarding such noise reducers, for example, Fukinuki, “
“Digital signal processing of images” published by Nikkan Kogyo Shimbun, pp. 1
15-118, an example of which will now be described with reference to FIGS. 9 and 10. In the figure, 2 is an arithmetic circuit, 3 is a delay circuit, 4 is a coefficient multiplication circuit, 5 is an input terminal, and 6 is an output terminal.

Now, the input signal at time t is X8, and the output signal of delay circuit 3 is y,, arithmetic circuit! Assuming that the output signal of is Z, the input signal Xi is supplied to the arithmetic circuit 1.2 at this time t. The output signal Y of the delay circuit 3 is also supplied to the arithmetic circuit 2, and the difference signal (Yi
-xt) is formed and supplied to the coefficient multiplication circuit 4.

In the coefficient multiplication circuit 4, the feedback coefficient K (however, 0≦K<1)
is set, and the supplied difference signal (Yi - Xi) is multiplied and supplied to the arithmetic circuit I. Therefore, the arithmetic circuit l
Now, input signal X! supplied from input terminal 5! and the signal K·(YiXi) supplied from the coefficient multiplication circuit 4 are added to form the signal Z5.

This signal Zi is output from the output terminal 6, and
The signal is supplied to the delay circuit 3. In the delay circuit 3, the supplied signal Zm is delayed for a certain period of time and is supplied to the arithmetic circuit 2. These arithmetic circuits 1 and 2, coefficient multiplication circuit 4, and delay circuit 3 constitute a so-called feedback noise reducer.

The transfer function T (Z) of this feedback type noise reducer is:
It is expressed by the following equation (1).

Here, Z″1 is a unit delay operator, and T is a delay circuit 3.
If the delay time is Z-kuz,, e-aljlt......(
2).

The frequency characteristics of this feedback type noise reducer can be obtained by substituting equation (1) into equation (2), and as shown in Figure 1θ, the frequency is n/T (n=1.2°3,・・・
...) and a trough at frequency (2n+1)/2T, exhibiting a comb-shaped characteristic. The input signal from the input terminal 5 in FIG. 9 is an image signal, and the delay time T of the delay circuit 3 is
If is one line period, l field period, or one frame period of this image signal, then due to their correlation, the frequency spectrum of the image signal matches the peaks in Fig. 10, and uncorrelated noise components match the valleys. One loss to the club. For this reason, the image signal input from input terminal 1 is not reduced and is output to output terminal 6.
The noise located in the valleys is reduced. For this reason, the S/N ratio is improved.

Furthermore, as shown in Figure 1O, the frequency characteristics of this noise reducer are such that when the feedback coefficient K is small, the gain at the valley is thick (and when the feedback coefficient K is large, the gain is small. The noise reduction effect is determined by the feedback coefficient K
The larger the , the thicker it becomes.

[Problems to be Solved by the Invention] The feedback noise reducer described above is extremely effective in reducing noise in image signals. However, on the other hand, if the feedback coefficient is set to a large value in order to improve the noise reduction effect, there is a problem that resolution deterioration occurs, as is well known.

In other words, with a line noise reducer that uses vertical correlation, the vertical resolution deteriorates (vertical blur) at the edge of the image.
In addition, frame noise reducers that use frame correlation cause deterioration of dynamic resolution (afterimages) due to differences in image content between frames in a video, and field noise reducers that use field correlation cause
Since these line noise reducers and frame noise reducers have intermediate characteristics, vertical resolution and dynamic resolution are degraded.

SUMMARY OF THE INVENTION An object of the present invention is to provide a noise reducer that can solve the above-mentioned problems, reduce the above-mentioned resolution deterioration, and efficiently reduce noise.

[Means to solve the problem]

In order to achieve the above object, the present invention provides a feedback noise reducer in which the feedback coefficient of a coefficient multiplier circuit is made variable, and an arithmetic circuit that generates a difference signal between an input signal and an output signal of a delay circuit; A limiter circuit having an input/output characteristic that reduces the output level when the absolute value of the level of the error signal is above a certain level is provided between the multiplier circuit, and a feedback circuit whose input/output characteristics of the limiter circuit is set to the coefficient multiplier circuit. Vary depending on the coefficient.

[Effect]

Generally, in a noise reducer, the S/
When N is low, a large amount of S/N improvement is required, so the feedback coefficient is increased to set a large amount of feedback, and when the S/N of the image signal is relatively good, the S/N is improved. Since the amount of improvement is not so necessary, the amount of feedback is set low by reducing the feedback coefficient. Therefore, S/ of the image signal
It can be said that there is a certain degree of correlation between N and the feedback amount of the noise reducer.

On the other hand, in the noise reducer, when the absolute value level of the difference signal from the arithmetic circuit is large, this difference signal is regarded as a difference component of the image signal, and when the absolute value level is small, this difference signal is regarded as a noise component. Therefore, the limiter circuit limits the difference signal when the absolute value level is above a certain level to reduce feedback.
An uncorrelated portion where the image signal changes significantly is not processed, and no resolution deterioration occurs in this portion. However, for signals with a level below this limiter level, resolution deterioration still occurs. Therefore, from the perspective of preventing resolution deterioration, it is preferable to set this limiter level as low as possible.
On the other hand, if the limiter level is lower than the noise level, the S/N improvement effect will be reduced. Therefore, it is necessary to set this limiter level higher than the noise level depending on the noise level.

The present invention is based on the above viewpoint, and the feedback coefficient of the coefficient multiplication circuit and the input/output characteristics of the limiter circuit are made variable, and from the correlation between the S/N level of the image and the amount of feedback,
For image signals with low S/N, the feedback coefficient of the coefficient multiplier circuit is made thicker (to increase the amount of feedback), and the input/output characteristics of the limiter circuit are set so that the limiter level becomes high. Efficiency <Improve S/N,
For image signals with high S/N, the feedback coefficient of the coefficient multiplier circuit is reduced to reduce the amount of feedback, and the input/output characteristics of the limiter circuit are adjusted so that the limiter level is low to minimize resolution degradation. Try to hold it down.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the noise reducer according to the present invention, in which 1.2 is an arithmetic circuit, 3 is a delay circuit, 4 is a coefficient multiplication circuit, 5 is an input terminal, 6 is an output terminal,
7 is a limiter circuit, and 8 is a control circuit.

In the figure, an image signal (for example, a luminance signal) is input from an input terminal 5 and supplied to an arithmetic circuit 1.2. Here, let this input image signal at time #ti be X5, the output signal of the delay circuit 3 at this time be Yi, and the output signal of the arithmetic circuit 1 be Zi. The output signal Y of the delay circuit 3,
is supplied to the arithmetic circuit 2, and a difference signal (Yi - X□) between this output signal Y8 and the input image signal Xi is generated. This difference signal (Y, -X,) is supplied to the limiter circuit 7.

The limiter circuit 7 is controlled by a control circuit 6 together with the coefficient multiplication circuit 4, and by this control, the coefficient multiplication circuit 4
When the feedback coefficient K is set, input/output characteristics suitable for this feedback coefficient K are set in the limiter circuit 7. Difference signal (Y
, -X,) are processed by this limiter circuit 7 and 1. Letting α be the function representing the input/output characteristics of this limiter circuit 7,
The output signal of the limiter circuit 7 is α・(Yi −Xi)
This output signal α·(Yi −Xi) is supplied to the coefficient multiplication circuit 4. Here, the function α is the difference signal (Y
i-X3). The coefficient multiplier circuit 4 receives the signal α・supplied with the feedback coefficient K set by the control circuit 8.
(Yi - Xi) is multiplied, and the resulting signal K.alpha.(Yi - Xi') is supplied to the arithmetic circuit 1. In the arithmetic circuit 1, the input image signal X and the signal K・α
- (Yi - Xi) are added and a signal Zi is output. This signal Z, is output from the output terminal 6 and is passed through the delay circuit 3 for a certain period T (one line period for the line noise reducer, one line period for the field noise reducer).
The signal is delayed by a field period (or, in the case of a frame noise reducer, an e-frame period), and then supplied to the arithmetic circuit 2.

According to this embodiment, the signal Y is expressed by the following equation using Zl.

Y6 =Z, e−'LL'' −−・・−−−
(3) Furthermore, as a result of the above processing, Zi = Xi +K.alpha. (Yi -

However, K'=K・α This equation (4) represents the transfer function of the conventional example shown in FIG. This embodiment differs from the conventional example described above in the following two points.

1) α is 1 in the conventional example, but is a function of the difference signal (Yi - Xi) in this embodiment.

2) The function α differs depending on the feedback coefficient K.

Now, the feedback coefficient set by the coefficient multiplication circuit 4 is +,
Kz, and these feedback coefficients =.

Assuming that the input/output characteristics of the limiter circuit 7 for K 2 (K 2 > K + ) are given by the characteristics a and b in FIG. 2, the function α for K=, Kz, respectively, is as follows.
It will look like this:

1) When K=, 1i) When Kz is 2, where A +, A z are K = K +, K
This is the limiter level of the limiter circuit 7 for each of z, and the relationship is A2>A. From the above equations (5) and (6), it can be seen that the substantial feedback coefficient in the above equation (4) is the part that changes a lot (i.e., l Yi −Xi l
is large), it becomes small, and as a result, resolution deterioration (vertical bleeding, afterimage) is reduced. Furthermore, since K' is smaller when K=2 than when K=2, resolution deterioration can be further suppressed.

Therefore, an image signal with a low S/N is input, and its S/N
When the main purpose is to improve the feedback coefficient of the coefficient multiplier circuit 4, the control circuit 8 sets the feedback coefficient of the coefficient multiplier circuit 4 to a large value of 2 when the user instructs the user to that effect. The limiter circuit 7 is set with input/output characteristics of a high limiter level A2.

As a result, the limiter circuit 7 sufficiently passes the noise component, and the coefficient multiplier circuit 4 sufficiently increases the amount of feedback. Therefore, the S/N ratio is sufficiently improved. In this case, the vertical resolution and dynamic resolution of this image signal will deteriorate, but the S/N improvement effect will be greater than this, so
Image quality is greatly improved.

Furthermore, in the case of an image signal with a high S/N ratio, the problem is not so much an improvement in the S/N ratio but rather a deterioration in vertical resolution and dynamic resolution. In such a case, according to the user's instruction, the control circuit 8 sets the feedback coefficient of the coefficient multiplication circuit 4 to a small value of +, and accordingly sets the limiter circuit 7 to a low limiter level A.
Set the input/output characteristics of 1. As a result, the limiter circuit 7 passes low-level noise components and sufficiently suppresses the difference signal between the image signals. Further, 1. The coefficient multiplication circuit 4 reduces the amount of feedback. Therefore, although the S/N improvement effect is not large, deterioration of vertical resolution and dynamic resolution can be prevented.

In this way, the feedback coefficient of the coefficient multiplication circuit 4 and the input/output characteristics of the limiter circuit 7 can be set based on the S/N ratio of the input image signal, and a high-quality image can be obtained.

FIG. 3 shows the S of the input image signal according to the embodiment shown in FIG.
/N is a characteristic diagram showing the relationship between (input S/N) and the amount of S/N improvement, and (A) is a characteristic diagram based on analog processing;
CB) in the same figure is due to digital processing, and
a is the feedback coefficient =! In this case, b is the feedback coefficient.

In Fig. 3 (A), the amount of S/N improvement is greater for K = than for 1, and in both cases, the amount of S/N improvement increases as the input S/N increases up to the limiter level. However, above the limiter level, the amount of S/N improvement becomes constant. The usage range of characteristic a is set to the region S2 where the input S/N is low, and the usage range of the characteristic A is set to the range S1 where the input S/N is high.

In FIG. 3(B), characteristics a and b are the same as in FIG. 3(A), but since the number of quantization bits of the image signal is finite, in the region where the input S/N is high, The amount of S/N improvement is decreasing. The maximum S/
This is because N is limited. The number of quantization bits is determined from the required S/N value. When the image signal is a luminance signal, the number of quantization bits is generally about 8 bits.

(In addition, even in the case of analog processing, the maximum S/
Although N may be limited, in FIG. 3(A), it is assumed that no noise component occurs at this maximum S/N). Third
In the diagram (B), a region S1 is an area in which characteristic a is used, and an area St is an area in which characteristic S is used.

As a result, the limiter characteristics can always be optimized for the required amount of S/N improvement, so resolution deterioration can be kept to a minimum.

As described above, according to this embodiment, noise in the image signal can be reduced while suppressing resolution deterioration as much as possible.

FIG. 4 is a block diagram showing another embodiment of the noise reducer according to the present invention, in which 9 is a RAM (Random Access Memory), 10 is a ROM (Read Only Memory), and the parts corresponding to those in FIG. are given the same reference numerals and redundant explanations will be omitted.

In the figure, ROM10 stores feedback coefficients + and Kz to be set in the coefficient multiplier circuit 4, and functions α3, . α, and are stored. The control circuit 8 receives instructions from the outside.
Read the feedback coefficient 2 from ROM10 and set it in the coefficient multiplier circuit 4, and read the feedback coefficient KI.
Function α1 or α2 of input/output characteristics corresponding to or 2
is also read from ROM10 and stored in RAM9 of limiter circuit 7.
write to. Data corresponding to the difference signal (Yi - Xi) output from the arithmetic circuit 2 is read from the RAM 9,
This is supplied to the coefficient multiplication circuit 4 as the output of the limiter circuit 7.

According to this embodiment, more finely optimized input/output characteristics can be given to the limiter circuit 7 than in the embodiment shown in FIG. 1, and resolution deterioration can be further reduced in accordance with each feedback coefficient. be able to. Note that FIG. 5 shows two different feedback coefficients K.

An example of input/output characteristics of the limiter circuit 7 with respect to K2 is shown.

FIG. 6 is a block diagram showing still another embodiment of the noise reducer according to the present invention, and parts corresponding to those in FIG. 4 are given the same reference numerals.

The embodiment shown in FIG. 4 also has a recursive coefficient K of the coefficient multiplication circuit 4.
, for the function α representing the input/output characteristics of the limiter circuit 7,
It has the transfer function of the above equation (4) where K'=K·α is the feedback coefficient. In the embodiment shown in FIG. 6, the input/output characteristics of the limiter circuit are expressed by the feedback coefficient ', thereby making it possible to omit the coefficient multiplication circuit.

In Fig. 4, let the feedback coefficient be +, Kz,
The function α of the input/output characteristics of the limiter circuit 7 for each is α
1. Assuming that α2, in FIG. 6, +'=+.alpha. and 2'=2.alpha.2 are stored in the ROM10. . The control circuit 8 reads the coefficient 1' or 2' according to an external instruction, and sets the R of the limiter circuit 7.
Write to AM9.

The difference signal (Yi-X
, ) is read out and supplied to the arithmetic circuit 1 as the output of the limiter circuit 7.

FIG. 7 shows an example of the input/output characteristics of the limiter circuit 7.

FIG. 8 is a block diagram showing a specific example of the limiter circuit in FIGS. 4 and 6, in which 11 is an input terminal, 12 is a level detection circuit, 13 is a multiplexer, 14 is a mask circuit, and 15 is an output terminal. The parts corresponding to FIGS. 4 and 6 are given the same reference numerals.

In the same figure, in the case of the embodiment of FIG. 4, the ROM10 contains feedback coefficients K1. 2 and the corresponding function α7.
α2 is stored, and in the case of the embodiment shown in FIG. 6, coefficients K l ′ (=K I·αl) and Km′ (=2·α2) are stored.

First, writing of data in ROM10 to RAM9 will be explained.

When there is an instruction from the outside, the control circuit 8 puts the RAM 9 into a write mode using the read/write signal R/W, and puts the multiplexer 13 into a state where the address signal An' from the control circuit 8 is selected using the control signal S. Set.

Then, the control circuit 8 sends the address signal All to the ROM10.
and an address signal An' are sent to the RAM 9 through the multiplexer 13, respectively. In the case of the embodiment shown in FIG. 4, the function α1 or α2 corresponding to the instruction from the outside is output from the ROM10 by this address signal A, and in the case of the embodiment shown in FIG. The coefficient Kl' or K21 according to an external instruction is read out as data DT, respectively, and supplied to the RAM 9 via the control circuit 8.

In the RAM 9, this data Dr is sequentially written to addresses specified by the address signal AD'.

As a result, the input/output characteristics of the limiter circuit 7 become as shown in FIG. 5 or FIG. 7.

In this way RAM 9. data is written to
When processing the difference signal (Yi-Xi), the control circuit 8 uses the control signal S to cause the multiplexer 13 to select the input terminal 11 side, and sets the RAM 9 to the read mode. .

Difference signal (Yi - Xi) input from input terminal 11
is supplied to the level detection circuit 12 and also to the RAM 9 through the multiplexer 13. RAM9
Then, this difference signal (Yi - Xi) acts as an address signal, and data D corresponding to this difference signal (Yl - Xi) is read out. This data DT is transferred to the mask circuit 14.
The signal is output from the output terminal 15 via.

The level detection circuit 12 receives a difference signal (Yi
-Xi) is higher than a certain level (hereinafter referred to as the dark value level), and when the level is higher than the dark value level, the mask circuit 14 is controlled to transfer the data DT from the RAM 9.
cut off. As a result, if the output level can be set to zero if the input level exceeds a certain level with the characteristics shown in FIGS. 5 and 7, this certain level can be used as the dark value level in the level detection circuit 12 Therefore, R
It is sufficient to store corresponding data up to this dark value level in the AM9, and the capacity of the RAM9 can be reduced.

Further, when the output level is always constant when the input level is above a certain level, this certain level is set as the dark value level, and the mask circuit 14 outputs the above-mentioned certain output level above this dark value level. This can also reduce the capacity of the RAM 9.

In addition, in FIGS. 4 and 6, RO is used instead of RAM9.
M is used to store functions of input/output characteristics corresponding to each feedback coefficient K in this ROM, and the control circuit 8 selects a function corresponding to the feedback coefficient set in the coefficient multiplier circuit 4. Good too.

〔Effect of the invention〕

As explained above, according to the present invention, it is possible to optimize the feedback coefficient and the input/output characteristics of the limiter circuit according to the S/N of the input image signal, thereby efficiently improving the S/N and preventing resolution deterioration. can be realized.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the noise reducer according to the present invention, FIG. 2 is a diagram showing an example of the input/output characteristics of the limiter circuit in FIG. 1, and FIG. 3 is an example of the embodiment shown in FIG. 1. FIG. 4 is a block diagram showing another embodiment of the noise reducer according to the present invention.
FIG. 5 is a diagram showing an example of the input/output characteristics of the limiter circuit in FIG. 4, FIG. 6 is a block diagram showing still another embodiment of the noise reducer according to the present invention, and FIG. 7 is the limiter circuit in FIG. 6. Figure 8 shows an example of the input/output characteristics of
This figure is a block diagram showing a specific example of the limiter circuit in FIGS. 4 and 6, FIG. 9 is a block diagram showing an example of a conventional noise reducer, and FIG. 10 is a frequency characteristic diagram thereof. 1.2... Arithmetic circuit, 3... Delay circuit, 4... Coefficient multiplication circuit, 5... Input terminal, 6...... Output terminal, 7...Limiter circuit, 8...Control circuit, 9...RAM
, 10...ROM. Figure 1 Figure 2 Figure 3 (A) (B) Input S/N Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10

Claims (1)

[Claims] 1. A first arithmetic circuit to which an input image signal is supplied; a delay circuit that delays the output image signal of the first arithmetic circuit by a unit period; A second arithmetic circuit that generates a difference signal from the input image signal, and a feedback coefficient K that is
(However, 0≦K<1) is set, and the first arithmetic circuit includes a coefficient multiplier circuit that multiplies the difference signal by the feedback coefficient K, and the first arithmetic circuit converts the input image signal and the output signal of the coefficient multiplier circuit. In the noise reducer that performs arithmetic processing, the second
a limiter circuit that processes the difference signal output from the arithmetic circuit; and a control circuit that controls the input/output characteristics of the limiter circuit and the feedback coefficient of the coefficient multiplication circuit, and In addition to serving as an input signal to the coefficient multiplier circuit, the control circuit switches and sets the feedback coefficient K of the coefficient multiplier circuit, and sets input/output characteristics to the limiter circuit according to the coefficient set in the coefficient multiplier circuit. A noise reducer characterized by: 2. In claim 1, the limiter circuit has a rewritable memory that stores a function α giving an input characteristic;
A noise reducer, characterized in that data corresponding to the difference signal from the second arithmetic circuit is read out from the memory and outputted. 3. In claim 2, instead of the coefficient multiplier circuit in which the feedback coefficient K is set and the limiter circuit in which the input/output characteristic function α is set, the coefficient K·α is controlled by the control circuit. 1. A noise reducer comprising a limiter circuit having a memory that can be rewritten. 4. In claim 1, the limiter circuit has a read-only memory that stores functions of input/output characteristics corresponding to each feedback coefficient K to be set in the coefficient multiplication circuit, and the control circuit controls the A noise reducer characterized in that a function of input/output characteristics is selected according to a feedback coefficient K set in a coefficient multiplication circuit.