JPH01220293A - Associative memory circuit - Google Patents

Abstract

PURPOSE:To use a circuit mode flexibly than ever before by providing a first switch means controlled by the coincident output of a coincidence detection circuit, and a second switch means connected between the first switch means and a coincident output line and controlled by the storage output of a second storage element. CONSTITUTION:The coincidence detection circuit connected to a first storage cell 100 is constituted so as to detect coincidence between first storage output 104 that is the storage content of the first storage cell 100 and retrieval data supplied via a first bit line 102 and the coincident output 108 powers a first switch 130 at a time when no coincidence is obtained. Meanwhile, the second storage cell 110 stores a don't-care flag which represents whether the storage information of the first storage cell 100 is valid (logic value 1) or invalid (logic value 0). A second switch 140 is controlled by the storage content of the second storage element 110, and the second switch 140 is opened via second storage output 107 when the flag shows an invalid state. By constituting the circuit in such way, it is possible to provide a storing state of don't-care which represents the coincidence compulsorily, and to perform the registration or retrieval of data with variable length.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a novel associative memory device that can perform addressing based on stored contents. This associative memory device is
It is characterized by the structure of its storage unit, which allows it to handle variable length data.

Regarding conventional technology associative memory circuits, several proposals have already been made in papers and patents, such as “IB[!BJO[IR
NAL OF 5OLID -5TATE CIRC[
IITS, VOL, 5C-20, N005.19
85 rAn 3-kbit Content-Add
Ressable and Reentrant Mem
As described in U.S. Pat. No. 4,538,243 and U.S. Pat.

Problems to be Solved by the Invention However, conventional associative memory circuits with such a configuration are configured to generate a search result that either matches or mismatches the search data with the stored content when searching for stored data. Therefore, it has the disadvantage that information indicating a match cannot be stored regardless of the memory state of "Batonto Care", that is, the search data.

For this reason, conventional associative memory devices in which content addressable memory circuits are arranged in a matrix form have the problem that they can only handle data of a fixed length defined by the matrix size, that is, a predetermined bit size. Ta.

Furthermore, conventional associative memory circuits are limited in their operation to address conversion using fixed-length logical addresses as input, and cannot be applied to the fields of slam matching processing and character string matching processing that handle variable-length data. Ta. This is due to the above-mentioned configuration in which the conventional associative memory circuit cannot assume a "don't care" memory state.

Therefore, the present invention solves the problems of the prior art described above, and
The object of the present invention is to provide a new associative memory circuit that can be used more flexibly.

Means for solving the problem, namely, according to the invention, a first storage element connected to a first bit line and a word line; a second storage element connected to a second bit line and the word line; , a coincidence detection circuit to which the storage output of the first storage element and the search data of the first bit line are input; a first switch means controlled by the coincidence output of the coincidence detection circuit; A content addressable memory circuit is provided, comprising a switch means and a second switch means connected between the coincidence output line and controlled by the memory output of the second memory element.

Here, according to one aspect of the present invention, the first switch means and the second switch means can be connected in series between the ground and the -dispersion output line.

Also, according to another aspect of the invention, the first switch means may be connected between ground and the -dispersion output line, and the second switch means may be inserted into the coincidence output line. .

Operation The content addressable memory circuit provided by the present invention includes a first memory element connected to a first bit line and a word line, a second memory element connected to a second bit line and a word line, and a second memory element connected to a first bit line and a word line. a coincidence detection circuit that receives the storage output of the first storage element and the search data of the first bit line as input, and further includes a first switch means whose opening and closing are controlled by the coincidence output of the coincidence detection circuit;
Its main feature is that it includes a second switch means connected between the first switch means and the coincidence output line and whose opening and closing are controlled by the memory output of the second memory element.

That is, in contrast to conventional associative memory circuits, the present invention can forcibly provide a don't care memory state that indicates a match.
It also makes it possible to register and search variable length data.

EXAMPLES The present invention will be described in more detail below with reference to the drawings, but what is disclosed below is only one example of the present invention and does not limit the technical scope of the present invention in any way. .

Embodiment 1 FIG. 1 is a circuit diagram partially showing a configuration example of an associative memory circuit according to the present invention.

This circuit includes a plurality of memory cells, each memory cell having - similar to a semiconductor memory element in a conventional memory circuit.
As in the memory cell 100 (200) shown in FIG. 1, by setting the word line 101 to a high potential, the first bit line 1
02 (112) to take in write data and read stored contents.

Here, the coincidence detection circuit 12 connected to the memory cell 100
0 detects a match between the first memory output 104, which is the storage content of the first memory cell 100, and the search data supplied via the first bit line 102, and the match output 106 is output to the first switch 130 when there is a mismatch. is configured to conduct.

On the other hand, the second memory cell 110 is the same as the first memory cell 100.
Stores a don't care flag indicating whether the storage information in the memory is valid (logical value ``1'') or invalid (logical value ``0'').Second
Switch 140 is controlled by the storage contents of this second storage cell 110. In other words, the flag is in an invalid state (“0
”), the second memory output 1 is
The second switch 140 is opened via the switch 07.

The circuit according to the present invention configured as described above operates as follows in a search operation.

First, prior to a search operation, the word line 101 is set to a low potential, and the -spread output line 108 is precharged to a high potential.

As mentioned above, the don't care data in the second storage cell 110
When the flag indicates the valid status B (“1”), the second switch 140- is conductive. In addition, the first bit line 102
When the above search data and the stored content of the first storage cell 100 do not match, the first switch 130 becomes conductive. Therefore, the charge on the -spread output line 108 is discharged to a low potential through the first switch 130 and the second switch 140, and the -spread output line 108 exhibits a mismatch condition.

On the other hand, if the search data and the stored content match, the first switch 130 is opened, and the -spread output line 108 maintains the high potential of the matched state. Here, if the don't care flag in the second memory cell 110 indicates an invalid state (P0''), the second switch 140 is opened.

Therefore, regardless of the search data and the storage contents of the first storage cell 100, the -spread output line 108 maintains a high potential, resulting in a don't care storage state.

Embodiment 2 FIG. 2 is a circuit diagram showing an example of the configuration of an associative memory circuit according to the present invention, and differs from FIG. 1 in that each component is specifically realized with a MOS transistor. The difference is that the first and second bit lines are in positive and negative pairs.

In FIG. 2, first and second memory cells 200 and 210 each surrounded by a broken line are connected to a pair of inverters 230 whose inputs and outputs are connected to each other, and whose outputs are connected to positive and negative channels. 1 bit line 102.103
A pair of M connected to (second bit line 112, 113)
OS) This is a general static RAM element composed of a transistor 240.

Further, the -scattering product output circuit 220 is connected to the positive and negative first bit lines 10.
2. MOS transistor 2 inserted in series between 103
40, and the connection point corresponds to the coincidence output 106. That is, the positive and negative first bit lines 102 and 103 during the search
are supplied with positive and negative search data, respectively, and when the search data and the storage contents of the first memory cell 200 do not match, the potential becomes high and the first MOS transistor 250 becomes conductive.

In the circuit configured in this way, the second memory cell 210
The state in which "0" is stored in the memory, that is, the second memory output 107 is at a low potential and the second M03) transistor 250 is in an open state is the "don't care" state. In this memory state, when the potential is high, The precharged match output line 108 holds a high potential corresponding to the match state regardless of the search data.

Note that when both the positive and negative first bit lines 102 and 103 are driven to a low potential, the -dissipated output 106 is reduced to the first memory cell 200.
Regardless of the contents of , the potential becomes low and the first M03) transistor 250 is opened. That is, masking of the search data is performed.

As described above, this associative memory circuit has a search function in addition to reading/writing, and can also store stored data in a ``don't care'' state. It is also possible to search variable length data.

Embodiment 3 FIG. 3 is a circuit diagram showing the configuration of a third embodiment of the present invention. Here, unlike the embodiment shown in FIG. 2, a second M03) transistor 320 is inserted into the coincidence output line 108. Note that the memory cell 200 and the second memory cell 2
10. - The scattering product output circuit 220 is the same component as the circuit shown in FIG. 1, and the reference numbers are also the same.

Furthermore, in terms of operation, read and write operations are performed in the same manner.

In this embodiment, if "0" indicating that the storage information in the first storage cell 200 is invalid, that is, don't care, is stored in the second storage cell 210, the second M03)
Transistor 320 is opened.

Therefore, when a plurality of content addressable memory circuits are realized by connecting the coincidence output lines 108 and lead wires 101 of a plurality of content addressable memory circuits in series on the left and right, don't care for the second memory cell 210 of a specific bit among them. When "0" is stored, the coincidence output line 108 is cut off at this bit. That is, the second storage cell 2 of the appropriate bit
By storing #O# in 10, an associative memory circuit capable of handling data of various lengths is realized.

In this case, in place of the second M03) transistor 320, a switch in which a pair of P-channel and N-channel MOS) transistors are connected in parallel is used to realize a multi-bit content addressable memory circuit. This is advantageous because it is possible to prevent the voltage of the coincidence output line 108 from dropping.

Embodiment 4 FIG. 4 shows a configuration example of an associative memory device combining the associative memory circuit of the present invention. The associative memory device of this embodiment includes an associative memory circuit 410 configured by arranging the previously described associative memory circuits in a matrix of m rows and n rows, and has an associative memory with a capacity of m words x n bits.゛ has been realized.

In this device, the word lines 101 in the same row are commonly connected to the output of the word line driver 430, and the match output line 108 in the same row is commonly connected to the drain of each MO3) transistor 420 and the encoder 440. Further, the positive and negative first bit lines 102 and 103 and the positive and negative second bit lines 112 and 113 of each column are commonly connected to a read/write amplifier 450.

In this content addressable memory device, a read or write address is given by an input address 431, and a word line 101 designated by the input address is driven by a word driver 430. The variable length registration data during registration operation is right-justified and the first
The data terminal 451 provides the flag, and the don't care flag is provided from the second data terminal 452. When registering data with a size of n bits or less, when inputting the registration data, use the second data terminal 4 corresponding to the first data terminal 451.
52 is given information of "1" indicating validity, and information of "0" indicating don't care is given to the second data terminal 452 corresponding to the remaining left bit.

Note that when the associative memory circuit shown in FIG. 2 is used as the associative memory circuit 410, not only variable length data but also data that includes don't care bits can be registered. Furthermore, when using the associative memory circuit shown in Fig. 3, there is no need to give "0" to all unused bits on the left to the second data terminal, and only the last bit is given "0"'. Since the coincidence output line 108 can be cut off by this, it is also possible to register variable length data.

When search data is applied to the first data terminal 451 to perform a search on variable length data, the search result is output to the match input/output line 108. Therefore, by applying the precharge signal 421 immediately before the search operation, the -several output line 108 is precharged to a high potential by the MOS transistor 420. The matching person output line 108 of the row in which information matching the search data is stored is held at a high potential,
The match input/output line 108 of the row storing the mismatch information is discharged to a low potential. - Makito output line 10
The match signal on 8 is supplied to an encoder 440 and output as a match'address 441 via the encoder 440.

As described in detail, the associative memory circuit according to the present invention achieves a don't care memory state due to its unique configuration. Therefore, it is possible to register and search variable length data, which was impossible with conventional associative memory circuits.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a configuration example of an associative memory circuit according to the present invention, and FIGS. 2, 3, and 4 are circuit diagrams showing configurations of different embodiments of the present invention. [Main reference number] 100.200...first storage cell, 110.2
10...Second storage cell, 120.220
...-scattering output circuit, 130 ... first switch, 140 ... second switch, 230 ... inverter, 240.420 ... MOS) transistor, 250
．． 310...Ith MOS transistor, 260.
320...2nd M03) transistor, 410
... Content addressable memory circuit, 430 ... Read driver, 440 ... Encoder, 450 ... Read/write/write amplifier.

Claims (1)

[Claims] a first storage element connected to a first bit line and a word line; a second storage element connected to a second bit line and the word line;
a memory element, and a coincidence detection circuit that receives as input the memory output of the first memory element and the search data of the first bit line;
a first switch means controlled by the coincidence output of the coincidence detection circuit; and a second switch means connected between the first switch means and the coincidence output line and controlled by the memory output of the second memory element.
An associative memory circuit comprising switch means.