JPH01217796A - Non-volatile semiconductor memory device - Google Patents

Abstract

PURPOSE:To operate a comparison detector according to a designed value by setting the output voltage of a reference voltage generating circuit to the intermediate of the output voltage of a sense amplifying circuit when a pseudo memory element is written, the threshold thereof is changed and the memory element storing 0 and 1 is selected. CONSTITUTION:In the reference voltage generating circuit, the pseudo memory element (reference cell) M3 which is the same in a structure and a characteristic as a storing cell is disposed and the reference cell M3 is written by a similar means to the storing cell to control a current changing a the threshold and flowing and set to the intermediate of the output voltage of the sense amplifying circuit when the storing cell where the output is written and an erased storing cell are selected. Accordingly, the current voltage characteristics of the storing cell and the reference cell M3 have the characteristics having no saturation area and even when the output voltage of the sense amplifying circuit is changed due to the change of the threshold and the fluctuation in a process condition, the output voltage of the reference voltage generating circuit is similarly changed. Thereby, the difference between both output voltages is substantially equal to the designed value to prevent difficulty in a detection by the comparison detector of a next step.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The invention relates to a non-volatile semiconductor memory device whose main component is an insulated gate field effect transistor (hereinafter referred to as IGFET), and in particular relates to a non-volatile semiconductor memory device that is electrically writable and erasable. The present invention relates to a semiconductor memory device (hereinafter referred to as EEFROM).

[Conventional technology]

An example of a conventional EEFROM is shown in the block diagram of FIG. Here, the X decoder circuit and Y decoder circuit for selecting the byte specified by the address are completely omitted. In the figure, ON channel type enhancement type IGFE for selecting Y address of Qa memory cells M11, . . . M, 1
T (hereinafter referred to as NE-IGFET), memory cell M
1□〜M! 11 is composed of a selection cell MS,1, which is an NE-IGFET, and a storage cell MM1m, which has a floating gate and stores all information of "0" or "1".
ls NE-IGFE for selection of Y address of B byte
T, M, 1-MBnl is byte xl, . The address selection NE-IGFET %Q1t is a write NE-IGFET that is selected by the address and becomes conductive when writing the memory cell.

Hereinafter, to simplify the explanation, the threshold values of all NE-IGFETs are assumed to be the same VTN, and the storage cells are assumed to have a conductive state defined as ``0'' and ``1'' as the stored information. Suppose there is a non-conducting state.

As shown in FIG. 7, an EEPROM that requires a high read speed has a voltage of the output Mk of the sense amplifier circuit 12, which changes depending on the information stored in the memory cell MM1□, and an output RA of the reference voltage generation circuit 15. is compared with the voltage VuF by a comparison detector 16 to detect and amplify whether the selected memory cell is in a conductive state or a non-conductive state, and output the result from an output buffer 17.

This EEP OM/1 has a high voltage generation circuit (charge pump circuit) 11 that generates a high voltage Vppk necessary for writing and erasing from the power supply voltage VOO, and the voltage of this output CP is mode, VPP in erase mode
In addition, in the read mode, it is set to a value close to ■co1 or ■00. The control gate voltage control circuit 13 sets the voltage of the output CGS to "0" in the write mode, to VPP in the erase mode, and to the read voltage VR in the read mode.
is set to In the write mode, this write control circuit 10 sets the output WC to the voltage VPP when writing to a memory cell.
When not writing, the output WCt-voltage is set to "0" in erase mode and read mode. The source voltage control circuit 14 sets the voltage of the output VS to V in the write mode.
Set to "0" in OO, in erase mode, and in read mode.

Next, memory cell MM,, 'i write, memory cell M
The case of erasing Mn1 will be explained.

First, when writing to memory cell MM, 1'ji, address 1llYx m Xt is set to high voltage Vpp K: L
, output WC to Vpp, output CGS to rOJ, Vs
l is set to VOO. Therefore, transistor Qll
*Qtz tM, 1. ,Ql,,MB,1 is conductive, and if the memory cell stripe is connected, the drain of 1 has (VPP VT
Since "0" is applied to the gate, the electrons injected into the floating gate are emitted to the drain. At this time, the threshold values of memory cells MM, , shift negative from the initial state, so in read mode, when a read voltage is applied to the gate electrode, memory cells MM, 1 become conductive, and the current ION increases. flows.

When erasing memory cell MMn 1, the address line Y!
.

Xn is set to all Vpp, the output WC of the write control circuit 10 is O, and the output CG of the control gate voltage control circuit 13 is
S is set to VPP and vsl is set to O. Therefore, the transistor Qss? MB n 1 , memory cell Kusunoki becomes conductive, and ho is connected to the drain of memory cell MMn 1 .
vPP is applied to the gate, and electrons are injected from the drain to the floating gate. At this time, since the threshold value of the memory cell MMnl shifts positively from the initial state, the memory cell MMn1 becomes non-conductive even if the read voltage vR is applied to the gate electrode in the read mode.

Figure 2 shows the charge pump circuit 11 at Vpp = 19v.
If designed to be 120V or 21V, writing/
Threshold value VTM(N) of written memory cell vs. erase pulse time, threshold value VT of erased memory cell
This shows how M(El changes for each VPP. The higher the voltage VPP, the longer the write pulse time and the erase pulse time, the greater the change from the initial value of the threshold value. Become.

FIG. 8 is a block diagram of an example of the sense amplifier circuit 12 of FIG. 7. A P-channel enhancement type IGFET with an output of 8A with the Qsff source connected to the power supply VOO and the gate and drain connected in common (hereinafter referred to as PE-IGFET).
), Q9 connects the drain to the full output, SA, the source to the other output SB, the input of the inverting amplifier I2, and the gate to the input of the inverting amplifier I2.
It is.

First, the operation of the sense amplifier circuit 12 when the written memory cell MM11 is selected will be described.

Current I is applied to memory cell MMII. n flows, the voltage at the output 8B decreases, the output voltage of the inverting amplifier I2 increases, and the transistor Q9 becomes conductive. The voltage of the output SA is at 9, and the voltage of the output SA is balanced when it matches the current flow flowing through the transistor Q8. Memory cell MMII
The more current that flows through the output SA, the smaller the voltage of the output SA becomes.

The output SA of the sense amplifier circuit 12 when the written memory cell is selected is set to the voltage VOn.

Next, the operation of the sense amplifier circuit when the erased memory cell MMn1 is selected will be described. At this time, cell M
Since Mn1 becomes non-conductive, the voltage of the output SB is charged and increases, and the gate voltage of the transistor Q decreases and becomes non-conductive. Therefore, the output 8AOt pressure [, PE-IQFB
To [, la value 't VTP (Vo
o -VTP). The erased memory cell is selected and the output SA of the sense amplifier circuit 12 at 9 o'clock is set to the voltage Voff.

FIG. 9 is a ratio block diagram showing an example of the reference voltage generation circuit 15 of FIG. 7. Transistor Q4 is a PE-IGFET whose source is connected to the power supply VOO and whose gate and drain are commonly connected to output A, and has the same (gate width)/(gate length) as transistor Q9.

The drain of the transistor Q5 is the output A, the source is the output RB and the input of the inverting amplifier Il, and the gate is the inverting amplifier Il. connected to the output of and identical to Qe (gate m)
The NE-IGFET%M4 has the same (gate width)/(gate length) as the transistor Q12, with the drain connected to the output terminal B and the gate connected to the power source VooK. The drain is connected to the source of the transistor Q7, the gate is connected to the voltage source 11Voo, and the transistor Ms11. , , the same (gate width)/(gate length) t-more NE(GF
ET, M, has its drain connected to the source of FET M4,
It is a NE-IGFET (hereinafter referred to as a reference IGFET) whose source is connected to ground and whose gate is connected to a reference readout control line CGR.

This conventional reference voltage generation circuit 15 controls the entire voltage of (gate width)/(gate length)/CGR of IGPETM, output voltage VRII, and the next time a written memory cell is selected. The output voltage V of the sense amplifier circuit 12 of
On, the output voltage of the sense amplifier circuit 12 when an erased memory cell is selected. It functions by setting between ff.

Next, the output voltage (RA) of this reference voltage generation circuit 15
The Vamp voltage setting method will be described.

FIG. 10 shows the current-voltage characteristics of the write voltage VPP determined by the charge pump circuit 11 and the current-voltage characteristic of the memory cell t which is input from the write pulse @t and PwK, and the current IREP flowing through the reference IGFET M11 of the Ice reference voltage generation circuit 15. In the current-voltage characteristic IR3 and the sense amplifier circuit 12, Qs s Qs * ”x t
Qs*mMsll, the reference voltage generation circuit 1
5, Q4 ・Q5 ・11 , Qt , M4
Load characteristics of the load circuit consisting of Ll eLz s
IJ! C or lower (referred to as a load curve). FETQ, and q.

Q9 and Qs * Qt z and Q7. Msll and M4
Both have the same (gate@)/(gate length), and ■2
has the same input/output characteristics as 11, so the load curves of sense amplifier circuit 12 and reference voltage generating circuit 15 exhibit the same characteristics.

Ll is '31%' When the logical threshold value of R1 is as designed, the logical threshold values of ISI and IRI for L2 and L3 may be negative or negative from the designed value due to variations in threshold values, fluctuations in process conditions, etc. This figure shows the load curve in the case of a positive shift.

~M-finger memory cell MMIIs The drain has a thin oxide layer of about 100A called a tunnel gate through which electrons pass, and the gate and drain are strongly capacitively coupled, so the structure shown by ICe in Figure 10 is , the drain current increases as the drain voltage increases, and there is no saturation region as seen in the current-voltage characteristic L3 of the IGFET.

Figure 41 shows the current “ONs” flowing through the written t storage cell.
The output voltage V of the sense amplifier circuit 12 with respect to the current IRIIF flowing through the reference IGFET. ff.

vON s Output voltage of reference voltage generation circuit 15 V RIP
It is a t-characteristic diagram showing how the O value changes. L.

The load surface ah shown in is mainly FET Qa, Q4
The sense amplifier circuit 12 and the reference voltage generation circuit 15 have the same characteristics.

In FIG. 10, the current-voltage characteristics ICe of the written memory cell, the sense amplifier circuit, and the reference voltage generation circuit 1 are shown.
Disadvantage P with load curve Ll of 5! The current value l0N(1) indicates the entire current value that actually flows through the memory cell in the design, and from FIG. 11, it can be seen that the output of the sense amplifier circuit 12 corresponding to IoNtll is Von (IJ. Reference IGF'ETM of voltage generation circuit 15
, the current value flowing into F0, VREF= i Vof
f Yon (1))/2. The point Q1 between the current-voltage characteristic IR3 and the load surface HL1 of this reference IGFETM is the reference voltage generation circuit 15.
is the equilibrium point at the design value of the drain of the reference IGFE'll'MS.

Next, the reference voltage generation circuit 15 and the sense amplifier circuit 1
The case where the load curve L1 of No. 2 changes to L2 will be explained. In this case, the intersection P1 of the load curve and ICe changes to P2, and the current Ion (IJ is
However, since the reference I GFETMS is operating in the saturation region, this reference I GF
The current flowing through ET remains I rtgp (Di. Therefore, the output voltage van (I
J will change to Von (21. At this time, the output voltage of the sense amplifier circuit 12 and the reference voltage generation circuit 15
Difference in output voltage (Vaap (DJ Von (2), difference in case of design value (VREP (I)l V.o
(Since it is smaller than 1υ, detection by the comparison detector 16 at the next stage becomes difficult.

Next, a case will be described in which the load curves of the sense amplifier circuit and the reference voltage generation circuit change to L3. In this case, the load curve and the fault P1 of ICe are changed to P3, and the current flowing through the cell (Ion(II) changes to 31, but the current flowing through the reference IGFETM is
(2) The RBF port remains as it is, and the output voltage Von (IJ) of the sense amplifier circuit 12 changes to Von (3J).

At this time, the difference between the output voltage of the sense amplifier circuit and the output voltage of the reference voltage generation circuit (VFLmp CD) Von (3
However, the difference in the case of the design value (VRBF (D) - V.n(
Since it is larger than 1)), there is a drawback that the read speed becomes slower when the next erased memory cell is selected.

There is also a method of using a memory cell that is neither written nor erased as M, but the memory cell has a tunnel gate of about 100A, and during EEFROM manufacturing, the floating gate is charged through the tunnel gate. Since the threshold value of the memory cell varies within the chip, it cannot be used as a memory cell kMs that is neither written nor erased.

[Problem to be solved by the invention]

As described above, the conventional reference voltage generation circuit 15 uses an IGF'ET as a current source that determines the output voltage 7 part rt'', and the (gate width)/(gate length) of the IGFET, IG
By controlling the voltage of the reference readout control line connected to the gate electrode of the FET, the output voltage 7 parts v'
k, the output voltage VOn of the sense amplifier circuit 12 at a regular time when a memory cell is selected for writing and t, and the output voltage Voff from the sense amplifier circuit 12 at a regular time when a memory cell is selected and erased.
However, since the current-voltage characteristics of the IGFET and the current-voltage characteristics of the written ratio storage cell are different, the load curves of the sense amplifier circuit and the reference voltage generation circuit are designed to be in the middle of the threshold voltage. If there is a negative shift due to variations in variations or process conditions, the difference between Von and EP becomes much smaller than the designed value, and if a cell is selected for data storage, it becomes difficult to detect with a comparison detector. There is.

Also, if the load curve shifts positively due to variations in threshold values or process conditions, V. n and V. If the difference from ff is larger than the designed value, then if a memory cell to be erased is selected next, there is a drawback that the read speed becomes slow.

In addition, in the conventional reference voltage generation circuit, the output voltage cannot be arbitrarily changed at the stage of checking the functionality of the chip, so it is difficult to estimate how much the current that is written and flows to the companion memory cell varies within the chip. Large capacity EEPR
There were drawbacks that made it unsuitable for OM.

An object of the present invention is to enable the comparison detector to operate according to the designed value even if there are variations in threshold values or process conditions, and to ensure that a written storage cell is selected in a chip function check and that the Another object of the present invention is to provide a non-volatile conductor memory device in which variations in current flowing through memory cells can be evaluated and, based on the evaluation results, the output voltage of a reference voltage generation circuit can be set to an appropriate value.

[Elaborate means to solve problems]

In the uninvented configuration, the rOJ cross of the digital signal is "1".
, a plurality of memory elements that store , digit and t lines that output the full voltage according to the memory contents of these memory elements, a sense amplifier circuit that detects voltage changes on these digit lines, and a sense amplifier circuit that corresponds to the output voltage of these sense amplifier circuits. A nonvolatile conductor memory device comprising a reference voltage generation circuit that generates a reference voltage, and a comparison detector that compares the output voltage of the reference voltage generation circuit with the output voltage of the sense amplifier and extracts it as an output voltage. The reference voltage generation circuit includes at least a pseudo memory element having the same structure and the same characteristics as the memory element, and a write circuit for writing the digital signal into the pseudo memory element, and the output of the reference voltage generation circuit includes: The voltage is written to all the pseudo memory elements and its threshold f
By changing fl, the output voltage of the sense amplifier circuit at 9 o'clock when rOJ is memorized and a constant memory element is selected, and the output voltage of the sense amplifier circuit at 9 o'clock when rLJ is selected and a constant memory element is selected. It is characterized by being able to be set between

〔Example〕

Next, all drawings will be referred to regarding non-invention.

FIG. 1 is a circuit block diagram of a reference voltage generating circuit (15) used in one embodiment of the present invention. In the figure, Q4,
Qs and L are the same as in FIG. 9, M3 is a reference cell (hereinafter referred to as reference cell) that has the same structure and characteristics as the memory cells Mvn to Mn1, and the Y select line YR and the X select line XR are , reference cell X decoder 4 and reference cell X decoder 3
When the reference cell M3 is selected by a control signal, the voltage VPP is supplied in the write/erase mode and the voltage VPP is supplied in the read mode. In addition, the drain of Q is connected to the drain of FET Qs, and the gate is connected to Y select line YR, which is the same as Q7 in FIG.
1fI)/(gate length) t- NE-IGF for selection
E.T.

Ml is an NE-IGFE whose drain is connected to the source of IGFETQ and whose gate is connected to the X selection line XR.
T% Qs u,)' The rain is connected to the output CGS of the control gate voltage control circuit 13, and the gate is connected to the Y select line Y.
The NE-IGFET %M connected to R has a drain connected to I
The source of GFETQ3 is a 72NE-IGFET whose gate is connected to the X select line XR, and the reference cell Mst! , drain force IQFB'l'M.

The source is connected to the source of the (Vs) output ■s1, and the gate is connected to the source of the IGFETM. In addition, the charge pump circuit 2 determines the conditions for writing to the reference cell Mst (VPP I write pulse time), and the write control circuit 1 outputs the output W when writing to the reference cell Mst.
VPP is output to CR. In addition, Ql has a drain connected to the output CPR of the charge pump circuit 2, and a source connected to the IGF
NE-IGF for writing is connected to the drain of E T Q 2 and the gate is connected to the output WCR of the write control circuit 1.
It is ET.

A method of setting the output voltage vRgy of the reference voltage generation circuit of this embodiment will be described.

As shown in FIG. 2, the threshold value vTn(5) of the written memory cell depends on the write voltage VPP and the write pulse width tpy. For example, the charge pump circuit 2 is
If it is designed so that VPP = 20 V, @pw = 1 mS, and the memory cell is written, ■Tn (b) as shown in Figure 2.
It can be seen that = -4v. The current-voltage characteristics of the current flowing through the memory cell when v'rn = -4V are expressed as I in Figure 3.
Ce is shown in Fig. 10. Same as 8.

Since the reference voltage generating circuit of this embodiment has a reference cell Msk having the same structure and characteristics as the memory cell, writing is performed using the same means as the reference cell Mst and the threshold value VTMR (low voltage). ) to a more negative value than the initial state and by controlling the current flowing through the reference cell M3, the output voltage VRBF can be set to a desired value.

For example, when setting the threshold value VTMRw of reference cell M3 to total V'['MIL=-2V, the charge pump circuit 2 shown in FIGS.
0 V s jpy ”' Q, l rns also uV
It can be seen that the design should be such that pp = 19 V and tpW = 1 mS.

When the reference cell Ms'ttr is designed in this manner and the reference cell Ms'ttr is inserted, the current-voltage characteristics of ti flowing through the reference cell are as shown in Figure 3.

Comparing IR in FIG. 3 and IR3 in FIG. 10 (7), it is found that the reference voltage generation circuit of this embodiment has a
”As a result, IR has current-voltage characteristics with no saturation region, similar to ICe. When this reference voltage generation circuit is used, the load curves of the sense amplifier circuit and reference voltage generation circuit are close to the threshold value. The output voltage Yon of the sense amplifier circuit when the friend memory cell to which data is written is selected at 9 o'clock, changes from the design value due to variations in process conditions, variations in process conditions, etc.
The relationship between the output voltage of the reference voltage generation circuit and the output voltage is shown in Figure 3.
This will be explained using FIG.

Similar to FIG. 11, FIG. 4 shows changes in the output voltage Yon of the sense amplifier circuit and the output voltage VREF of the reference voltage generation circuit with respect to the current flowing through the storage cell and the reference cell. The output voltage of the sense amplifier circuit when the current value is O is the output voltage of the sense amplifier circuit when the erased memory cell is selected and normal. Corresponds to ff.

(1) When the load curve Ll shifts negatively to L2 and t, the intersection P1 between the load curve and ICe changes to R2, and the intersection RIl between the load curve and I changes to R2. Therefore, the current IoN (IJ flowing through the memory cell changes by 2J), and the current IRFiF (1) flowing through the reference cell changes to I
RBF (changes to 2J.At this time, from Fig. 4, the output voltage VOn(1) of the sense amplifier circuit becomes VOn(2)
Then, the output voltage of the reference voltage generation circuit P(1) is VIJ
It can be seen that it changes to F(2).

(2) When the load curve L1 shifts positively to L3 and t, the intersection P1 between the load curve and ICe changes to R3, and the intersection R1 between the load curve and IR changes to R3. Therefore, the current Ion(11) flowing in the memory cell changes to Ion(3J, and the current IRIF(1) flowing in the reference cell changes to F(
3). At this time, it can be seen from FIG. 4 that the output (IJ) of the sense amplifier circuit changes to VOn (3), and the output voltage 7F (1) of the reference voltage generation circuit changes to VShoF (31).

As explained above, fC, in the non-embodiment, even if the load curve L1 shifts negatively like L2, the output voltage VOn of the sense amplifier circuit and the output voltage VR1i of the reference voltage generation circuit
Since the difference in IF (Vxp (21-Von (21)) is smaller than the difference in the design value (VREF (11-Von (11)) in the conventional example, If the comparison detector at the next stage selects the friend storage cell for writing, it will not be difficult to detect.

Furthermore, even if the load curve shifts positively to L3, the difference between the output voltage VOn of the sense amplifier circuit and the output voltage VRFiFO of the reference voltage generation circuit (VREF (3) - Von (3J
) is the design value (vFLgr (11Von
(Since the amount of increase is smaller than that in the conventional example, even if the next erased storage cell is selected, the read speed will not be slowed down as in the conventional example.

FIG. 5 is a block diagram of a second embodiment of the invention. In the non-embodiment, instead of the charge pump 2 in the first embodiment, there is an external terminal 20, and the I/C gate and drain of this external terminal 20 are connected in common, the source is connected to the output line, and a current flows through the terminal 20. NE-IGF'ET Q for backflow prevention.

In this embodiment, a method of inserting 8 reference cells M3 will be explained.

The first embodiment uses a write voltage PP and a write pulse Sl from a charge pump circuit 2 built in the chip.
, TI (Fig. 6), reference cell Msk
In this embodiment, the write voltage and write pulse can be directly controlled by the external terminal 20.

Even in the non-embodiment, as described in the embodiment of 81!1, the threshold value VTMR(5) of the reference cell M3
An example of setting TMR (~=-2) will be described.

In the figure, the source of FET Q corresponds to the output of charge pump circuit 2, so its source voltage is 20V.
Either apply a pulse voltage (for example, maximum value 22.5 V, pulse time 0.1 m5) to the terminal 20 as shown in pulse S1 in FIG. In order to set the source voltage of FETQ4 to 19V, apply a voltage to the terminal 20 (for example, the maximum value is 2L5V,
It is sufficient if the pulse time is 1 m5) t-. Input voltage S
Source voltages S2, T2 are shown for l, Tl.

In this embodiment, the voltage ① occurs when the load curve shifts positive or negative from the design value due to variations in threshold values, variations in process conditions, etc. The change in n e voff from the design value is exactly the same as in the first embodiment.

In addition, in the non-embodiment, the output voltage of the reference voltage generation circuit can be changed by writing to the reference cell Mst'' using an arbitrary write voltage and write pulse time from the external terminal 20, and changing the entire threshold value. Example t-EEPRO
When installing the MK, at the stage of checking the functionality of the chip, apply a high voltage from the external terminal to the reference cell t.
By changing the output voltage of the reference voltage generation circuit and checking whether the written memory cell can be read correctly, the current flowing to the written memory cell can be changed to the memory cell in the chip. It is possible to evaluate how much variation there is in daily life, and from this evaluation result, it is possible to set an appropriate value by taking into account the variation in the current flowing through the cells for storing all the output voltages of the reference voltage generation circuit.

〔Effect of the invention〕

As described above, the uninvented semiconductor memory device f! t has a pseudo memory element (reference cell) whose structure and characteristics are the same as a memory cell in a reference voltage generation circuit, and a write circuit, and writes to this reference cell and sets the threshold value of this reference cell. The output voltage of the reference voltage generation circuit, the output voltage of the sense amplifier circuit when a written memory cell is selected, and the erased memory cell are controlled by changing the current flowing through this reference cell. It can be set to an intermediate value between the output voltages of the sense amplifier circuit when the cell is selected.

Therefore, the current-voltage characteristics of the storage cell and the reference cell both have characteristics that do not have a saturation region, and the load curves of the sense amplifier circuit and reference voltage generation circuit are designed depending on changes in the threshold value and variations in process conditions. Even if the output voltage of the sense amplifier circuit changes, the current flowing to the reference cell changes in the same way, and the output voltage of the reference voltage generation circuit also changes. I can do it.

Therefore, even if the load curves of the sense amplifier circuit and the reference voltage generation circuit change from their design values, the output voltage VRFiF of the reference voltage generation circuit and the output of the sense amplifier circuit when a written storage cell is selected. Difference in voltage Yon (VRIF
-V. n) becomes almost the designed value, and as in the case of the conventional example, this difference becomes small and becomes difficult to detect with the comparison detector in the next stage, or this difference becomes too large and is erased next time. If a deep storage cell is selected, there is no need to slow down the read speed.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram of a reference voltage generation circuit in one embodiment of the present invention, and Fig. 2 is a waveform diagram showing fluctuations in the threshold voltage ■T during writing and erasing of a memory cell used in this embodiment. , 3rd
The figure shows the load curve of this example. Current-voltage characteristic diagram of memory cell and reference cell,
FIG. 4 is an output voltage characteristic diagram of the memory cell of this example, and FIG.
The figure is a circuit diagram of the reference voltage generation circuit of the second embodiment of the invention, Figure 6 is a waveform diagram of the pulse applied to the external terminal of the WiJ2 embodiment, and Figure 7 is the conventional EEPROIm and the block of the example. 8 is a circuit diagram of an example of the sense amplifier in FIG. 7, FIG. 9 is a circuit diagram of an example of the reference voltage generation circuit in FIG. 7, and FIG. 10 is a load characteristic diagram of a conventional example, and a memory cell. 11 is a current-voltage characteristic diagram of a reference cell, and FIG. 11 is an output voltage characteristic diagram of a conventional memory cell. 1.10...Write control circuit, 2.11...Charge pump circuit, 3...X decode circuit, 4...Y decode circuit, 12...Sense amplifier circuit, 13...
Control gate voltage control circuit, 14... Source voltage control circuit, 15... Reference circuit, 16...
Comparison detector, 17... Output buffer, 20... External terminal, 21... Output terminal s'1*'2... Inverter, Ml. M2. M,,M5. ,,NE-IGFET%M3...
Reference cell, M1□~Mn1... memory cell,
MMll...Memory cell, M511...Selection cell, Ql...NE-IGFET for writing, Q2, Q
s, Qs~Qy, Qe, Q, I~Q13...NE
-IGFET1Q4 ,Q,...PE-IGET Agent Patent Attorney Susumu Uchihara ¥3 Figure Kaya 4 - Tahaya Z What - Kamo χ

Claims (1)

[Claims] A plurality of memory elements that store digital signals "0" or "1", digit lines that output voltages according to the memory contents of these memory elements, a sense amplifier circuit that detects voltage changes on these digit lines, and these sense A nonvolatile device comprising a reference voltage generation circuit that generates a reference voltage corresponding to the output voltage of an amplifier circuit, and a comparison detector that compares the output voltage of the reference voltage generation circuit with the output voltage of the sense amplifier and extracts it as an output voltage. In the semiconductor memory device, the reference voltage generation circuit includes at least a pseudo memory element having the same structure and the same characteristics as the memory element, and a write circuit for writing the digital signal into the pseudo memory element, By writing the output voltage of the reference voltage generation circuit into the pseudo memory element and changing its threshold value, the output voltage of the sense amplifier circuit when a memory element storing "0" is selected is determined. , and the output voltage of the sense amplifier circuit when a memory element storing "1" is selected.