JPH01215188A - Communication method for recording and reproducing device - Google Patents

Abstract

PURPOSE:To attain quick communication processing by generating a text at 1st half in one period of a signal relating to a rotation reference phase of a recording medium, arranging texts in the order of transmission, storing it into a buffer and applying communication including the transmission of the text generated in the latter half. CONSTITUTION:The communication processing between plural controllers is applied at the latter half in one period of the reference signal relating to the rotation reference phase of the recording medium, a 1st half part generates a text to be sent in the latter half and stored while being arranged in the order of transmission in the buffer. Since the communication is applied in the latter half of one period of the reference signal, a high control requested with high accuracy without being affected by interruption by the communication control is applied. Thus, the communication processing and the processing requiring high accuracy are harmonized in this way. Then in the first half of one period of the reference signal, the text to be sent in the communication processing in the latter half is generated and arranged in the order of transmission, then it is not required to edit the text during communication in the latter half and quick communication is applied.

Description

DETAILED DESCRIPTION OF THE INVENTION Summary of the Invention A plurality of control devices (including a CPU) are provided which share and control each part or the entire recording/reproducing device by communicating with each other. Since the editing is performed in the second half of one cycle of the signal related to the reference phase, the editing of the message is performed in the first half of the same cycle. This enables quick communication processing without wasting time during the short period of time in the latter half.

BACKGROUND OF THE INVENTION This invention involves recording a predetermined signal on a magnetic, optical or other recording medium that rotates once in synchronization with its rotational reference phase, and recording a predetermined signal from a rotating recording medium in synchronization with its rotational reference phase. The present invention relates to a recording/reproducing device that performs at least one of reproducing a signal, and particularly to a method of communication between control devices in a device configured to share control of the recording/reproducing device by a plurality of control devices (including a CPU).

A typical example of this type of recording/playback device is a still video device that captures a still image of a subject with a solid-state electronic imaging device, then FM modulates the output still video signal and magnetically records it on a rotating video floppy. ·camera,
There are still playback devices that play back still video signals from a video floppy, and devices that have both recording and playback functions.

In such a still/video signal recording/playback device,
One rotation of the video floppy records/plays out one field's worth of still video signals. A reference angular position for recording/reproducing still video signals on a floppy during video is determined in advance, and this reference angular position is detected by a phase detector. Then, a reference signal (vertical synchronization signal, etc.) for recording/reproduction synchronized with the phase pulse output from the 1-phase detector is created. record/
The main operations in the reproducing device are performed using this reference signal as a reference.

The disk motor that drives the video floppy disk is controlled by a servo control circuit to rotate at a precisely constant rotation rate. If there are fluctuations in the rotational speed, recording/playback of still video signals will not be performed correctly. Therefore, it is necessary to constantly check whether the rotational speed of the disk motor is maintained at a predetermined constant value. This is called servo lock determination processing.

The phase pulse representing the rotational phase of the video floppy and the reference signal of the device are synchronized so that they have a predetermined phase relationship. Also, since the process of checking whether there is a predetermined phase relationship (synchronous phase relationship determination process) and the servo lock determination process described above include an extremely short 1111 constant process, high accuracy is required.

On the other hand, when considering a configuration in which the recording/reproducing device is controlled in a shared manner by a plurality of control devices (including a CPU), it is necessary for these control devices to communicate with each other. Communication requests are generated individually in each control device. Furthermore, when a communication request is received, it is necessary to respond immediately. Therefore, communication between multiple control devices! +Controls are generally given high priority.

However, if an interrupt for communication occurs while the above-mentioned synchronous phase relationship determination process or servo lock determination process is being performed, and the control device proceeds to this interrupt routine, high accuracy cannot be maintained in the above-mentioned determination process. There is a risk that it will disappear. Therefore, it is preferable to prohibit communication processing during the time period when the control device is performing the above-mentioned determination processing.

Summary of the Invention This invention comprises a plurality of control devices that communicate with each other and share control, each control device performs an operation synchronized with the rotational phase of a recording medium, and at least one control device has extremely high precision. It is an object of the present invention to provide a method that harmonizes high-precision processing and communication processing and enables rapid communication in a recording/reproducing device that requires processing.

In the recording/reproducing apparatus as described above, the present invention performs communication processing between a plurality of control devices in the latter half of one cycle of a reference signal related to the rotational reference phase of a recording medium, and The latter part is characterized by creating the messages to be sent, arranging them in the sending order, and storing them in a buffer.

According to this invention, communication is performed in the latter half of one cycle of the reference signal, so that control that requires high precision is carried out in the first half without being adversely affected by interruptions, etc. associated with communication control. be able to do it. In this way, communication processing and processing requiring high precision are harmonized.

Furthermore, according to the present invention, in the first half of one period of the reference signal, the messages to be sent in the second half of the communication process are created and arranged in the sending order, so that the messages cannot be edited during the second half of the communication. There is no need to carry out communication, and communication can be carried out quickly.

The above reference signal "is generated in a relatively short period.

Although the period of the period is short, efficient communication is possible by the above method. In particular, it is effective to have a control device other than the control device performing the control that requires high precision in the first half of the cycle perform the message editing process in the first half.

An embodiment in which the present invention is applied to a still Φ video Φ camera will be described in detail below. Needless to say, the present invention is also applicable to magnetic recording/reproducing devices, recording/reproducing devices related to optical or magneto-optical recording media, and the like.

Description of Embodiments (1) System Configuration FIG. 1 shows the system configuration of a still video camera.

This still video camera is controlled by three control devices, namely a system control device IO2 photographing control device 30 and a recording control device 70. These control devices 10
．． Each of the 30.70 is composed of a CPU (for example, a microprocessor), a memory (RAM, ROM, etc.) for storing its programs and necessary data, and necessary interface circuits. The CPU of the system control device 10 is the main CPU, and controls the overall operation of the still Φ video camera. Shooting control device 30
and the CPU of the recording control device 70 is a sub-CPU,
It operates according to commands from the main CPU. The photographing control device 30 performs control related to photographing, such as focusing, aperture, shutter speed, and zoom. Recording control device 70
controls the recording of video signals on the video conference floppy disk 1, such as driving the disk motor 3, loading/unloading the magnetic head 2, and transporting the magnetic head 2. These control devices 10, 30, 70 are interconnected by serial transmission lines (including five lines as described later), and communicate at predetermined timings as described later.

A regenerator (regeneration adapter) 90 can also be connected.

This regenerator 90 demodulates the video signal read from the video floppy disk 1, converts it into a color video signal in, for example, NTSC format, and outputs the converted signal. Regenerator 90
It also includes a CPU and memory, and this CPU is positioned as a sub-CPU to the main CPU.

A still video camera is provided with a packet that can be opened and closed. Video floppy 1 is inserted into the opened packet, and when this packet is closed, video floppy 1 is transferred to disk motor 3. Chucked onto the spindle.

The video floppy 1 has a plurality of (for example, 50) tracks (for example, a track pitch of 100 μm) arranged concentrically, and depending on the shooting process, one or two tracks are provided.
1 field or 1 frame (1 frame) per track
An FM-modulated color video signal (including a luminance signal, a color difference signal, etc.) is magnetically recorded. The 50 tracks arranged concentrically on the magnetic recording surface of the video floppy 1 are numbered in order from the outermost ones: No., 1-No., 50.
The track numbers up to this point are attached. The home position HP (origin position or standby position) is outside the track No. 1, and the end position EP is No.
, inside the 50 tracks.

The system control device IO includes a power switch IB, various mode switches 11 to 14. Manual switch signals for the shutter release button 15, etc., detection signals from the packet switch 7 that detects the open/closed state of the packet containing the video conference floppy (and presence or absence of the video floppy, if necessary), and the installation location of the video floppy 1. A detection signal from a dew condensation sensor 8 that measures the humidity in the vicinity is input. The modes that can be set include frame/field session mode, which indicates frame recording or field recording, skip mode, which provides empty tracks that are not recorded on the video conference floppy, and edit mode, which records on empty tracks. . These set modes, the track number to be recorded, and other information are displayed on the liquid crystal display 21. This display 21 is connected to the system control device IO by bus.

Further, when dew condensation is detected or other abnormal conditions occur, the buzzer 22 sounds an alarm. The detection of dew condensation may be displayed on the display 21.

The shutter release button 15 is of a two-step stroke type, in which the first step of pressing releases the switch S1, and the second step of pressing the button 15 further releases the switch S2.
are respectively turned on. When switch S1 is turned on, disk motor 3 is driven. After this, switch S2
When turned on, photographing and recording are performed. , the imaging optical system is a zoom lens system 31. An imaging lens system 32 for forming a subject image. Aperture 33. a beam splitter 34 that deflects a portion of the incident light to enter the Jl optical element 51; It is composed of an infrared cutoff filter 35 and a shutter 36. The illuminance detection signal of the photometric cable 51 is input to the photographing control device 30 through a logarithmic amplifier 52 in red. By the shooting control device 30.

a? A process of calculating an aperture value and a shutter speed based on the incident light illuminance detected by the J optical element 51.

The aperture 33 is controlled based on the determined aperture value, and the shutter 3B is opened and closed based on the similarly determined shutter speed. Opening and closing of the diaphragm 33 is performed by a diaphragm motor 48 driven by a driver 47. Aperture 33
A switch 49 is also provided for detecting the opening and closing limit positions of the opening and closing limits. Unlatching and winding of the leading and trailing curtains of the shutter 3B are performed by a shutter drive device including a shutter φ motor 54 driven by a driver 53. The rotation angle of the motor 54 is detected by a rotary encoder 55 and fed back to the device 30.

The color detection signal from the color sensor 61 is subjected to predetermined processing in the white fist balance processing circuit 62 and then input to the device 30 . This white balance data is applied to the R in the variable gain amplification circuit described later in the signal processing circuit 71.
, G, and B signals for amplification gain control.

In order to measure the distance to the subject, an infrared light emitting diode 63 and a light receiving element 64 that receives the reflected light are provided, and a focusing processing circuit 65 indicates the distance to the subject based on the output signal of the light receiving element 64. Data is obtained. Using this data, an autofocus motor 46 is driven via a driver 45 under the control of the device 30 to perform focusing control.

Additionally, a tele to enter the degree of zoom.

In response to signals from wide switches 38 and 39, control device 30 drives zoom motor 42 via driver 41 to set a predetermined magnification.

The rotation angle of the motor 42 is detected by a rotary φ encoder 43 and fed back to the device 30.

At the focal plane of the imaging optical system, a solid-state electronic imaging device 37 for three primary colors, which is composed of a two-dimensional imaging cell array such as a CCD, is arranged.

The image data accumulated in the imaging device 37 when the shutter 3B is opened is read out as a serial still video signal (R, G, B) in synchronization with the vertical and horizontal synchronizing signals given from the signal processing circuit 71. and input to the signal processing circuit 71.

The signal processing circuit 71 includes an oscillation circuit, and generates and outputs a vertical reference signal VD and a reference clock signal from the output signal of the oscillation circuit. The vertical reference signal VD is supplied to the system controller 10. It is given to the photographing control device 30 and the recording control device 70, and serves as a reference for the operation timing in these devices. The reference clock signal is provided to the servo control circuit 80. As will be described later, the phase pulse PC representing the reference phase of rotation of the video floppy 1 is transmitted to the signal processing circuit 71.
The system control device IO1 is provided to the recording control device 170 and the playback device 90. A reset signal given from the recording control device 70 adjusts the vertical reference signal VD in the signal processing circuit 71 so as to maintain a constant phase relationship with the phase pulse PC. The signal processing circuit 71 also generates vertical and horizontal synchronization signals having a constant phase relationship with the phase pulse PG.

The signal processing circuit 71 further includes a preamplification circuit and a variable gain amplification circuit (
white balance adjustment circuit) and process matrix circuit. A luminance signal Y and two color difference signals RY and BY are created in the process matrix circuit. These color difference signals R-Y and B-Y are then line-sequentialized for each IH in a line-sequentialization circuit 72. The luminance signal Y and the line-sequential color difference signal pass through a pre-emphasis circuit (not shown), are FM modulated in different frequency bands in FM modulation circuits 73 and 74, and are then sent to two synthesis circuits 75.
is synthesized with

It is also possible to record additional information signals on the tracks of the floppy φ disk 1. The additional information signal is an acoustic signal (
narration, etc.) and display signals (representing voices such as narration, music, etc.)
For example, it means character information). This additional information signal is input from a microphone or other human-powered device (not shown) to the signal processing circuit 71, converted into a predetermined format, and output to the luminance signal Y line. The additional information signal S may be superimposed on the luminance signal Y, or when only this signal S is recorded on a predetermined track of the video floppy 1, it is output alone.

Furthermore, data multiplex recording is also possible on video floppies. This multiple recorded data includes initial bits, field/frame data, and track addresses (No.
, ) data, date data, and user usage data. These data are given from the system control device 10, and the signal processing circuit 71 processes them as D P S K (D
If'l'erent1al PhaseSl+il'
t Keying) is modulated and synthesized with the above-mentioned FM modulated video signal in a synthesis circuit 76, and then sent to a recording amplifier circuit 77.
Enter.

A magnetic head 2 (
The floppy disks (two of which are provided at intervals so as to be located on adjacent tracks to enable frame recording) are supported so as to be movable in the radial direction of the video floppy disk 1 by their transport drive control device, and are supported in the same direction. Transport controlled. The transfer drive controller includes a stepper motor 87 and its driver 86. The recording control device 70 gives instructions regarding the direction and amount of movement of the magnetic head 2 to the transfer drive control device. A home position switch 6 is also provided for detecting that the magnetic head 2 has reached the home position HP, and the detection signal of this switch 6 is sent to the recording control device 7.
given to 0.

A head-loading device is provided to prevent marks from being formed on the floppy disk due to the magnetic head 2 coming into contact with the stopped video conference floppy disk 1 for a long period of time. This device is a head load solenoid 85
Under the control of the recording control device 70, the magnetic head 2 is operated only during recording or playback (when the video floppy is rotating) or only while the power is turned on. The magnetic head 2 is displaced (advance or retreat) so that it comes into contact with the video floppy 1, and at other times leaves it away from the floppy 1.

In order to improve the contact between the magnetic head 2 and the rotating video floppy 1, a regulating plate (not shown) is provided on the opposite side of the magnetic head 2 with the video floppy 1 in between. In addition, the core of Video Wars Floppy 1 includes:
A phase detector 5 that detects the leakage magnetic flux of the chucking permanent magnet and outputs a phase detection signal when the video conference floppy disk 1 reaches a predetermined angular position is nearby. The output detection signal of the phase detector 5 is waveform-shaped by a phase pulse generation circuit (waveform shaping circuit) 82 and outputted as a phase pulse PG. circuit 71
and is input to the recording gate circuit 78. phase pulse PG
will be generated once per rotation of the video floppy disk.

The disk motor 3 is driven by its driver 81. The rotational speed of the disk motor 3 is detected by a frequency generator 4 and output from this frequency generator 4.

A detection signal with a frequency proportional to the rotation speed of the motor 3 is input to the servo control circuit 80. The servo control circuit 17 controls the motor 3 based on the clock signal input from the signal processing circuit 71 and the frequency detection signal input from the detector 4.
is controlled to rotate at a constant speed (for example, 3.800 r, p, m,). Also the servo control circuit 80. The motor 3 is started and stopped in response to commands from the recording control device 70.

The still/video signal etc. amplified by the recording amplifier circuit 77 is input to a recording gate circuit 78 . and recording control device 7
When a recording command is given from 0, this gate circuit 78
opens its gate at the timing of the input phase pulse PG until the next phase pulse is input. As a result, video signals and the like are applied to the magnetic head 2, and recording of still video signals and the like onto predetermined tracks of the video floppy disk 1 is performed. In this recording, video φ floppy 1 is 1
This is done only while rotating. This is the case for field recording. In the case of frame recording, the gate circuit 78 opens its gate for two revolutions of the video floppy 1;
During the first rotation of the video floppy 1, one head 2 transfers the video signal of the first field to a certain track, and during the second rotation, the other head 2 transfers the second field to the adjacent track. A video signal of each eye is recorded.

It is also possible to reproduce video signals etc. from the video floppy disk 1 using the magnetic head 2. The FM modulated video signal etc. read from the magnetic head 2 similarly passes through a gate circuit 78 and is amplified by an amplifier circuit 77 and sent to an envelope detection circuit 8.
3 and regenerator 90. This reproduction is used for track search processing not only in the reproduction mode but also in the recording mode.

The envelope detection circuit 83 is a detection circuit that detects the envelope of the read signal of the magnetic head 2, that is, the FM modulated video signal recorded on the track of the video floppy 1, and outputs a voltage signal corresponding to the envelope. It includes an A/D (analog/digital) conversion circuit. The voltage signal representing the envelope is converted into a digital quantity by an A/D conversion circuit, and is input to the recording control device 70 into an 8-bit digital signal representing, for example, 256 quantization levels.

The envelope detection signal is used by the recording control device 70 to determine whether a track on the video floppy 1 is unrecorded or recorded (track search processing). If the level of the detected signal does not reach the predetermined threshold e level when the magnetic head 2 is moved across the track, that track is unrecorded, and if it has reached the threshold level, then The track has already been recorded.

If necessary, the envelope detection signal is also used in the recording check process. The recording check process is to check whether the recorded still/video signal has been recorded on a predetermined track using the magnetic head 2 as described above, and whether the envelope detection signal has been recorded on a predetermined track. If it is above the threshold level, it is determined that recording has taken place.

(2) Communication System FIG. 2 shows a specific example of a serial transmission line connecting the system control device IO1, the photographing control device 30, and the recording control device 70 (and the reproducing device 90).

This serial transmission line consists of 5 lines,
A serial clock signal SCK, an output signal S, an input signal S, a busy signal BUSY (READY), and a request signal (REQUEST) are transmitted on each line. Each line leading to the control device to, 30.70 (and the regenerator 90) is interconnected with a wired OR.

For example, the serial tube clock signal SCK line of the system controller IO is wired ORed with the serial clock signal line of the other controller 30.70 (and regenerator 90). The same applies to other lines.

A serial clock signal (SCK) is output from the system controller IO and is used to synchronize communicated signals. The output signal S of the system control device ■0 becomes the human power signal S of the other control devices 30, 70 (and the regenerator 90), and conversely, the output signal S of the control bag W130°70 (and the regenerator 90) is the control device The human power signal S is 10. Busy signal BLISY and request signal RE
QUEST is the shooting control device 30 and the recording control device 70
(and the regenerator 90) and given to the system controller IO. Each control device lo, 30.70 (
and regenerator 90) are assigned addresses for specifying them in communication processing.

These control devices 10.30.70 (and regenerator 9
An example of an interface circuit for communication in 0) is shown in FIG. Before explaining this circuit, the method of communication and the form of the signal S will be described with reference to FIGS. 4 and 5.

As mentioned above, in still/video Φ cameras,
Phase pulse PG every 11 rotations of video floppy 1
occurs. A still video signal for one field is recorded on the video floppy 1 between two adjacent phase pulses PG.

Therefore, the basic operation of the still video camera is performed in synchronization with the phase pulse PC (and therefore, as will be seen later, with respect to the vertical reference signal VD).

FIG. 4 shows a time chart of basic signals in the still video camera Φ system. The vertical reference signal VD and the vertical synchronization signal v5sync are generated in the signal processing circuit 71 as described above, but these signals VD,
V5ync is controlled to maintain a predetermined phase relationship and synchronize with the phase pulse PG. For example, the vertical reference signal VD is 4H from the phase pulse PG (IH is the horizontal scanning period)
After a delay, the vertical synchronization signal V5ync is generated with a delay of 7H. The period of these signals PC, VD, V5sync is vertical scanning period 1v (1/GO seconds - 16.6m5)
be equivalent to.

Communication between the control devices 10.30.70 (and the regenerator 90) also takes place with reference to the vertical reference signal VD.

On the other hand, in important processing that is performed at a timing based on the vertical reference signal VD, the phase pulse P
and a process of determining whether the rotation speed of the disk motor 3 whose rotation is controlled by the servo control circuit 80 has reached a predetermined rotation speed and whether it is maintained at that rotation speed. There is a determination process (servo lock determination process). These phase relationship determination processing and servo lock determination processing are performed by the sub CPU of the recording control device 70.
However, since these processes require extremely high precision (that is, they include measurement processes at short time intervals), the sub-CPU cannot be dedicated to these processes. is necessary. Therefore, it is preferable to avoid communication processing with the main CPU of the system control device 10 during the time period when the sub CPU is performing these processes. Generally, interrupts in communication processing are given high priority, so if the sub CPU
If an interrupt for communication occurs while the sub CPU is performing servo lock judgment processing, etc., and the sub CPU proceeds to the interrupt processing routine, there is a risk that high accuracy cannot be maintained in servo lock judgment processing, etc. It is.

Therefore, as shown in FIG. 4, the IV period starting from the vertical reference signal VD' is divided into a first half and a second half (for example, both are V/2 periods), and servo lock determination processing etc. are assigned to the first half. communication processing is limited to the latter half. Management of the first half and the second half is performed by the main CPU of the system control device IO, and as shown in FIG. 2, the system control device IO is equipped with a timer for managing the periods.

There is no need to limit the period of the first half to V/2, and it may be determined based on the balance between the time required for processing the first half and the time required for processing the second half. For example, since the time required for the servo lock determination process and the phase relationship determination process described above is about 4 ms, the first half period may be shorter if only these processes are considered.

As illustrated in Fig. 4, this still φ video
In the camera system, the following processing is performed during the first half of the IV. That is, the servo lock determination processing in the recording control device 70 described above, etc., is performed by the power switch 16. in the system control device IO. Various mode switches 11-14° Shutter release button 1
1. Message editing processing including key scan processing such as 5 and creation of commands for the control devices 30 and 70 based on this key scan processing. Data collection processing such as measurement data in other control equipment 30, 70, etc., and message editing processing based on the data collection processing.

Other processing is performed. In the second half of 1v, in addition to communication processing, each control device r11tO.

Execution of commands associated with communication at 30, 70, etc.
Other processing is performed.

As mentioned above, communication processing is limited to the latter half of 12, so it is necessary to carry out this process quickly.

By assigning the message editing process to the first half of 1v,
Since there is no need to perform processing such as message editing during the second half of the communication process, sufficient communication is possible even for a short time.

Editing of the message is performed by storing the address, command, and data to be transmitted in a first-in, first-out (FIFO) buffer in the order in which they are to be transmitted, as shown in FIG. FIG. 6 shows a telegram created when the shutter release button 15 is pressed in the system control device IO (when the signal of the switch SI is manually input). Main C of system controller lO
PU is vertical 7! The key scan process is started from the time when the quasi-signal VD rises. When it is determined through this key scanning process that the switch SL of the shutter release button 15 is turned on, the photographing control device 30 performs photometry processing for exposure control and A for focusing control.
In addition to instructing the start of the 11l distance (distance #measurement to the object) process, it is also necessary to instruct the recording control device 70 to start the disk motor 3. Therefore, in response to the ON detection of the switch Sl, the main CPU sends the address of the photographing control device 30, the command to start photometry, the address of the photographing control device 30, the command to start distance measurement, and the recording control as shown in FIG. Address of device 70.

The commands for starting the disk motor (each consisting of 8 bits) are entered into the FIFO buffer in the order in which they are to be sent.

If the above processing is completed in the first half of 1v, then in the second half of IV, the main CPU responds to the interrupt from the above timer and sends the address and command placed in the Fll)0 buffer according to the communication flow described later. The signals can be sequentially sent out to the output signal S line, and communication processing can be performed quickly.

In response to a command given from the system control device IO in this way, each control device 30, 70, etc. executes the command in the latter half of IV.

For example, when the recording control device 70 receives a disk motor start command from the system control device IO, the control device 70
The sub CPU 0 controls the motor 3 for the servo control circuit 80.
Outputs drive commands.

Needless to say, in the first half of 1v, other control devices 30, 70, etc. also collect data to be sent to the system control device 10 and edit the message containing the data into the p+po buffer.

The output signal S (input signal S1) includes any one of an address, a command, and data. That is, the signal S is sent out in one signal sending process. is made up of 8 bits and corresponds to any one of address, command, and data. Therefore, it is necessary to be able to distinguish whether the sent signal S is an address, a command, or data.

Referring to FIG. 5, in order to distinguish addresses, commands, and data from each other, a predetermined level change is applied to the signal S prior to the addresses, commands, and data being sent. or not given. When the signal S 2 includes an address, the signal S 1 once falls from the H level to the L level, rises to the H level, and then falls to the L level. Signal S if signal S contains a command. goes high and falls from the bell to the low level. When the signal S 2 contains data, the signal S 2 is kept at the H level.

In order to distinguish between such a level change of the signal S and the actual contents such as address, command or data,
Addresses, commands, and data are sent out in synchronization with serial clock signal SC'K.

An interface circuit for distinguishing whether the content of the signal S is an address, a command, or data will be explained with reference to FIG. Since the circuit shown in FIG. 3 is included in the control device 30 or 70 (or one pottery 90), the sub CPU 100 is shown, but this circuit is for the main CPU of the system control device IO. The same applies anyway. This diagram omits a signal parallel/serial (P/S) conversion circuit and serial/parallel (S/P) conversion circuit.

The serial clock signal SCK is input to the sub CPU 100 and counted by its SCK counter (or counting program), and is also input to the serial clock signal (SCK) inhibition circuit 101. This SCK
The inhibit circuit 101 is, for example, an 8-bit counter, and its output is at a low level when counting the serial clock signal SCK, and generates an output at an H level at other times. The output of the SCK inhibit circuit lot is input to the AND gate 102.

If the output of the SCK inhibition circuit lot is at H level, the output signal S (human input signal S1) passes through the AND gate 102 and is input to the flip-flops 103 and 104. Flip-flop 103 detects a rising edge of signal S 2 and sets its output Q to H level, and flip-flop 104 detects a falling edge of signal S 2 and sets its output Q to H level. these flip flops 1
The outputs Q of 03 and 104 are input to the sub CPU 100. Let these input signals be Fl and F2, respectively.

Therefore, if the signal S 2 is input and there is a change in its level, this level change is detected by flip-flop 108 or 104 or both. Then signal S
entity (address, command.

When the data) is input manually, the serial clock signal SCK is also input manually, so the output of the inhibiting circuit 101 becomes L level, the AND gate 102 is closed, and the states of the flip-flops 103 and 104 are maintained as they are.

The input serial clock signal SCK is counted by the SCK counter.

FIG. 7 shows the identification processing of the signal S by the sub CPU (and the main CPU). When the SCK counter counts 8 (step 201), the flip-flop 20
3, the level of the output signal of 104, that is, the input Fl,
The state of F2 is examined (step 202). If these human forces Fl and F2 are both at H level, (Fl
-1, F2-1), and since the signal So included a rising edge and a falling edge, it is determined that the signal S includes an address. Input F1 is at L level,
When F2 is at H level (Fl-0, F2-1)
.

Since the signal S included a falling edge, it is determined that it is a command. Input Fl.

If both F2 are at L level (Fl-0, F2-〇)
, is determined to be data.

The CPU has the same function as the interface circuit shown in Figure 3.
Of course, it is also possible to implement this using software.

(3) Communication processing Next, referring to Figure 8, the main C of the system control device IO
A communication processing procedure between the PU and the sub-CPU of the photographing control bag F1a0 and the recording control device 70 (and the playback device 90) will be explained. The main CPU has the initiative in communication processing.

As mentioned above, the timer in the system control unit IO starts timing from the time of the vertical base signal VD, and when it detects that it is in the latter half of IV,
An interrupt to that effect is given, and the communication process shown in FIG. 8 is started.

The main CPU first checks whether there is a communication request (step 211). There are 2ffiM in the communication request. One of them is, as mentioned above, the main CPU's p+po
The message sent to the sub CPU is edited in the buffer. The other is request R from the sub CPU.
The EQUEST signal is being sent (an H level signal appears on the request signal line). In the latter case, it means that there is a message (command or data) to be sent from the sub CPU to the main CPU. Requests from the sub CPU will be discussed later, but here we will first discuss requests from the main CPU to the sub CPU.
This section explains how to send commands and data to.

The main CPU reads the first address set in the FIFO and sends it out as a signal S (Sterap 212).
. As described above, this signal S is given a rising edge and a falling edge/knob prior to sending out the address.

When the sub CPU detects that it is also in the latter half of 1v (
A timer may be provided in the sub CPU, or the main CPU
A timer interrupt may be given on a specific line from the PU timer), and the signal READY must be set to H level (
Step 231). Signal S (Si) containing address
(step knob 232), the sub CPU outputs a busy signal BUSY and sets the ready signal READY to L level (step 233), and checks whether the address in the received signal matches its own address. Check (step 234). If they match, the ready signal READY is set to H level and the process proceeds to the next step (step 235).

If there is a mismatch, the self is not specified and the process returns to the start.

After sending out the address signal, the main CPU monitors the ready signal line and checks whether the line has become H level (step 213).

If a ready signal is not sent even after a certain period of time has passed after sending the address signal, it is assumed that an error has occurred, and the process returns to the start and outputs the same address signal again (step 221).

When the ready signal is input manually, the main CPU reads the next command to be sent from the FIFO buffer, includes it in the signal S with a falling edge, and outputs it (step 2).
14).

When the sub CPU receives the signal S containing the command (step 236), it generates a busy output (step 237) and executes the given command (step 238). As mentioned above, the sub CPU starts photometry,
Start the motor, etc. When the command execution is completed, the sub CPU generates a ready output (step 239).
.

When the main CPU receives an H level ready signal, if there is data to be transmitted next, it transmits that data as a signal S (steps 215 and 218).

Wait until the ready signal becomes H level again (step 2)
17).

As in the example shown in FIG. 6, if there is no data to be sent to the sub CPU, steps 218 and 217 are skipped and the process returns to the start. Then, the process of reading the next address from the FIFO buffer and sending it out in the same manner is repeated.

When data is sent from the main CPU to the sub CPU, the sub CPU receives the data (step 2).
40), Generate busy output step 241),
Process the received data (step 24)
2). When data processing is completed, a ready signal is output and the process returns to the start (step 243).

If no data is received, steps 240 to 243 are skipped.

When sending commands or data from the sub CPU to the main CPU, the sub CPU sends an H level request signal R.
Outputs EQUEST. However, as shown in FIG. 2, the request signal lines of each control device 30, 70 and regenerator 90 (the same applies to other signal lines) are connected to the same line of the system control device IO by wired OR, so the main CPU does not know which sub-CPU outputs the request signal. Therefore, the main CPU performs communication processing to confirm whether the request signal has been outputted to all the sub-CPUs and what kind of request there is. An outline of the communication processing procedure of the main CPU based on the request signal from the sub CPU is shown in FIG.

The two series of processes in FIG. 9 are actually executed by repeating the communication process shown in FIG. 8 by the number of sub CPUs.

The processing in FIG. 9 will be explained below in relation to the processing in FIG. 8. Shooting control device 30. The sub CPUs of the recording control device 70 and the reproducing device 90 are respectively sub CPU1. sub CP
U2. It is assumed to be sub CPU3.

The main CPU checks whether an H level signal appears on the request signal line (step 251.
If a request signal is input (corresponding to step 211 in FIG. (corresponding to step 212). Since the sub CPUI generates ready output (steps 235 and 213 in Figure 8), the main C
The PU sends an all-zero command (step 214 in FIG. 8). At the same time, sub CPU 1
When the UI is outputting a request signal, the main C
Since there is a command to be sent to the PU, the command is sent to the main CPU (step 244 in FIG. 8).
245). Since a line for the output signal S and a line for the human input signal SI are provided between the main CPU and the sub CPU, simultaneous bidirectional communication is possible. When the sub CPUI is not issuing a request signal, it responds to an all-zero command from the main CPU and sends a command to that effect to the main CPU. Main CPU is sub CPU
When receiving a command from I, it analyzes its contents and stores the result in memory (step 218 in FIG. 8,
219). In this way, commands are sent and received between the sub CPUI and the main CPU (step 253).
, the main CPU can know whether the sub-CPU has issued a request, and if so, the contents of the request. If the sub CPUI is not issuing a request, all zero O command from the main CPU.

You may also choose not to respond to the command. Main CP
U is an all-zero command. If there is no response from the sub CPU even after a certain period of time has passed, the sub CPU
It is determined that I has not issued a request.

If the sub CPU has not issued the request, it means that another sub CPU has issued the request, so the main CPU
The PU sends out a signal S containing the address of sub CPU 2 or sub CPU 3 and performs similar processing (steps 254 to 257). Since two or more sub-CPUs may issue requests almost simultaneously, the main CPU may proceed to steps 254 to 257 even when it learns that sub-CPU 1 has issued a request.

Once the sub CPU that issued the request is identified as described above and the contents of the request are known.

Proceed to the processing for it. If the sub CPUI has issued a request, the corresponding processing is performed (step 258).
, 259), and for other sub-CPUs, the processing corresponding to the sub-CPU is similarly performed (steps 260 to 283). For example, the sub CPU is the main CPU
In the case of a request to send data to U, sub-C
PU sends data (steps 248 and 247 in Figure 8)
), the main CPU receives the data (step 220 in FIG. 8). If the sub CPUI issues a request, the process may immediately proceed from step 253 to step 259. In this case, if the request is related to data transmission, after the command transmission/reception process shown in FIG.
219.244.245), will immediately proceed to process the transmission and reception of data (steps 216.240-24).
2° or step 246.247.220).

In this embodiment, communication between the regenerator 90 and the system controller IO is from the regenerator 90! This is only done when the quest signal is output. In FIG. 1, the serial transmission line connected to the regenerator 90, the output line for the reproduced still φ video signal, and the line for the phase pulse PG are actually bundled together to form one cable. While the reproduced still video signal is on the order of several hundred mV, the signal on the serial transmission line is, for example, on the order of 5V. Therefore, if serial communication is performed while a reproduced still video signal is being sent out, noise may occur in the reproduced still video signal.

The case where the regenerator 90 outputs a request signal to the system control device 10 and sends information is when a key switch input is made on the regenerator 90 side. For example, they are a forward switch, a reverse switch, a track number, and a designated switch. Serial communication between the regenerator 90 and the system control device IO is performed only in such limited cases, which causes problems such as constant noise in the replayed video signal and deterioration of the image quality of the replayed still images. Prevented.

Finally, I would like to discuss the overall operation of still video cameras during shooting and recording, especially the system control device.
Communication between the main CPU of O and the sub CPUs of the photographing control device 30 and the recording control device 70 will be mainly explained with reference to FIG. 1O. In this figure, loading/unloading processing of the magnetic head 2, white balance adjustment, etc. are omitted.

First switch St of shutter release button 15
When is pressed, this is detected by the main CPU of the system control device 10, and the sub CPU of the imaging control device 30 is activated.
Photometry and distance measurement commands are given to the PUI, and a motor start command is given to the sub CPU 2 of the recording control device 70. As a result, the photographing control device 30 starts photometry processing and distance measurement processing. The photometry process is performed every 1v in synchronization with the vertical reference signal VD, and if the photometry value is within the photographable range, a message indicating that the photometry value is OK is sent from the sub CPUI to the main CPU. Also, based on the distance measurement data, the imaging lens system 32
Focusing control is performed, and when focusing is performed correctly, a release OK message is sent from the sub CPUI to the main CPU. Since the recording control device 70 starts the disk motor 3, the rotational speed of the motor 3 increases. This control device 70 performs a servo lock determination process to determine whether the rotational speed of the motor 3 has reached a predetermined value.

When it is determined that the disk motor 3 is servo-locked, the sub CPU 2 of the recording control device 70 notifies the main CPU of the system control device 1O of this fact. Further, the sub CPU 2 of the recording control device 70 outputs a reset signal to the signal processing circuit 7.

The vertical reference signal VD is controlled to have the above-mentioned predetermined phase relationship with the phase pulse PG. Even after this, the recording control device 70 performs the servo lock determination process and the phase relationship determination process between VD and PG every time the vertical reference signal 4D is generated (the first half of IV) as described above. , and notifies the main CPU of the results.

The main CPU is the second shutter release button 15.
When it is detected that the switch S2 is turned on, it is determined whether the shooting conditions are satisfied based on the servo lock determination result, phase relationship determination result, and other information notified from the recording control device 70. If so, a release command (photography start command) is given to the sub CPUI of the photographing control device r1130. In response to this, the control device 3
The sub CPUI 0 determines the aperture value and shutter speed based on the last photometric value, and drives and controls the aperture 33 so that the determined aperture value is achieved. Then, when the photographing *Wi is completed, the control device 80 enters the photographing process. During this time, if the main CPU determines that the photographing conditions are no longer satisfied, the main CPU issues a photographing prohibition command to the photographing control device 30.

The photographing process in the photographing control device 30 is started by generating a shutter open signal (g TS) with a pulse width corresponding to the shutter speed determined by the sub CPUI of the control device 30. At the rising edge of this signal TS, the shutter is opened. Shutter 3 so that the front curtain of 3B runs and the rear curtain runs at the time of falling.
B is driven and the imaging device 37 is exposed. After this, a winding operation of the shutter is performed.

The shirt open signal TS is also input to the system control device 10 through a line not shown in FIG.
When U detects the falling edge of the signal TS, the recording control device 70
Give a recording start command to. In the control device 70, in the 1v or 2v period starting from the 9th signal VD,
After the still video signal read from the imaging device 37 is subjected to FM modulation, processing for recording it on the video φ floppy disk 1 is performed. What is shown in FIG. 1.theta. is an example of frame recording, and therefore the still video signals of the first field and the second field are read and written over a period of 2v.

When this recording process is completed, the control device r! 170 sub CPs
U2 notifies the main CPU of the completion of recording. Thereafter, a head transport command is given from the main CPU to the sub CPU 2, and the magnetic head 2 is moved to the next track to be recorded under the control of the sub CPU 2. When the transfer of the magnetic head is completed, the sub CPU 2 notifies the main CPU of this fact. Furthermore, when winding of the shutter is completed in the photographing control device 30, the main CPU is notified of this fact from the sub CPUUI.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the system configuration of a still video camera. FIG. 2 is a block diagram showing in more detail how the control devices are connected via serial transmission lines. FIG. 3 is a block diagram showing an interface circuit for communication. FIG. 4 is a time chart showing typical signals and basic operations in a still video φ camera system. FIG. 5 is a waveform diagram showing a serial clock signal and an output signal. FIG. 6 shows how the message is edited in the FIFO buffer. FIG. 7 is a flow chart showing a process for determining whether an output signal includes an address, a command, or data. FIG. 8 is a flow chart showing communication processing between the main CPU and sub CPU. FIG. 9 is a flowchart showing the processing of the main CPU when there is a refresh list from the sub CPU. FIG. 10 is a time chart showing the overall operation of the still Φ video camera during photographing. 1...Video floppy. 2...Magnetic head. 5... Phase detector. lO...System control device. 30... Shooting control device. 70... Recording control device. 71...Signal processing circuit. 90...Regenerator. +00...Sub CPU. 101...SCK inhibition circuit. ! 02...AND gate. 103, 104...Flip-flop. Patent applicant: Fuji Photo Film Co., Ltd. Agent
Patent attorney Satsuki Kato (1 other person) Figure 4 Figure 5

Claims (1)

[Scope of Claim] A recording/reproducing device that performs at least one of recording a predetermined signal on a rotating recording medium in synchronization with a rotational reference phase of the recording medium, and reproducing a signal from the recording medium, comprising: / A plurality of control devices are provided that share control of each part or the entire playback device, and these control devices perform given control by communicating with each other, and are related to the rotation reference phase of the recording medium. A recording/reproducing device that creates telegrams in the first half of one cycle of a signal, arranges them in the transmission order and stores them in a buffer, and performs communication including the transmission of the telegrams created in the second half of the one cycle. communication method.