JPH01213052A - Modulator - Google Patents

Abstract

PURPOSE:To obtain a modulator which can eliminate the deterioration of bit error rate of a data signal in a reception side by detecting fluctuation caused by the change of time elapsed from the initial adjustment time of a D/A conversion circuit or temperature fluctuation and automatically correcting it. CONSTITUTION:An error signal generation circuit 10 inputs signals outputted from the D/A conversion circuits 4 and 5, compares these signals with the reference signal of the inside, generates an error signal corresponding to the fluctuation of an analogue signal and inputs this signal to an address generation circuit 1. The circuit 1 makes the inputted error signal to be an address signal for correcting the fluctuation caused by the change of the the elapsed from the initial adjustment time of the output and the temperature fluctuation in the circuits 4 and 5. Then, it outputs it together with an address signal corresponding to the inputted data signal to memory circuits 2 and 3. The circuits 2 and 3 read corrected data by the address signal. That means, as the above mentioned address is inputted, the circuits 2 and 3 read the data signal which the fluctuation caused by the change of the time elapsed from the initial adjustment time occurring to the output of the circuits 4 and 5 or the temperature fluctuation is corrected.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a modulation device, and more particularly to a modulation device using a digital multilevel multiphase modulation method.

[Prior Art] In recent years, as part of carrier wave digital transmission systems, in order to effectively utilize the frequency used, in addition to multiphase phase modulation in the phase plane, so-called multilevel polyphase modulation is also applied simultaneously in the amplitude plane. The modulation method has been put into practical use.

As a practical example of this, for example, 16 (QAM (Qua
drature Amplitude Modulat
ion) method is well known.

However, although this 16QAM method increases the amount of information, on the other hand, the performance required of the circuit becomes stricter. Therefore, strict performance is also required for the modulation device constituting the 16QAM system, and in particular, characteristics against fluctuations due to changes over time from the time of initial adjustment and temperature fluctuations are important.

FIG. 3 is a block diagram of the main parts of a conventionally used 16QAM modulation device.

In the figure, 1 is an address generation circuit, 2 and 3 are memory circuits, 4 and 5 are D/A conversion circuits, 6°7 is a 0-π phase modulation circuit, 8 is a π/2 phase shift circuit, and 9 is a synthesis circuit. It is a circuit. Further, 21 is an input signal terminal for the data signal Sl+;
2 is a human power signal terminal for the data signal S12, 23 is a human power signal terminal for the data signal 52+, 24° is an input signal terminal for the data signal S22, 25 is a carrier wave signal input terminal, and 26 is a modulated wave output terminal.

Further, FIG. 4 is a diagram showing the data arrangement of modulated output in the 16QAM system (Sll, S12.S21.522).

In the figure, P and Q are coordinate axes on the phase plane.

In the above configuration, the data signal SII+S12°S
21+922 are human signal terminals 21 and 22, respectively.
It is input to the address generation circuit 1 from 0.23 and 24.

Then, the address generation circuit 1 specifies a specific address for each of these human input signals.

In this way, the input signal designated by the address generation circuit 1 specifies the address of the memory circuits 2 and 3. As a result, in the memory circuits 2 and 3, the data signals stored at the respective designated addresses are read out. At this time, the data signal stored at each address is a digital value corresponding to the correction level of nonlinear distortion by an amplifier circuit or the like in the transmission system, or a digital value for band-limiting the signal.

On the other hand, data signals stored in memory circuits 2 and 3 are input to D/A conversion circuits 4 and 5, respectively. After being converted into analog signals by D/A conversion circuits 4 and 5, the signals are input to 0-π phase modulation circuits 6 and 7.

The 0-π phase modulation circuit 6 phase-modulates a predetermined carrier signal input from the terminal 25 using the analog signal output from the D/A conversion circuit 4, and generates and outputs a P signal.

On the other hand, the 0-π phase modulation circuit 7 is a π/2 phase shift circuit 8.
A carrier wave signal whose phase is shifted by 90 degrees is input. The 0-π phase modulation circuit 7 also phase-modulates this carrier signal using the analog signal from the D/A conversion circuit 5 to generate and output a Q signal.

Further, these P signals and Q signals are manually inputted to a combining circuit 9, orthogonally combined, and outputted from a terminal 26.

Next, FIG. 5 is a diagram showing input level versus output bell characteristics (amplitude characteristics) and human level versus output phase characteristics (phase characteristics) in the 0-π phase modulation circuits 6 and 7.

As is clear from the figure, the drive level (-bI+ "It+al
, +b, ).

The figure also shows the output levels (
-b2, -a2, +a2, +1)2
) and output phase (-90 degrees, +90 degrees) are also shown.

In this way, the amplitude characteristic has linearity, but the phase characteristic outputs a value of either -90 degrees or +90 degrees with the reference voltage V0 as the boundary.

However, with such a configuration, the drive levels of the 0-π phase modulation circuits 6 and 7 will also vary due to fluctuations in the D/A conversion circuits 4 and 5, particularly temperature fluctuations.

FIG. 6 is a diagram showing the data arrangement in the phase plane of the 16QAM system. In this case, 16 white points represent normal data arrangement.

However, for example, assume that the output of the D/A conversion circuit 4 changes to + by ■.

Then, as shown in FIG. 5, the 0-π phase modulation circuit 6
The output level of changes by +ΔV. For this reason, the 16 white dots in FIG. 6 also change to the positions of black dots.

[Problems to be Solved] In the conventional modulation device described above, errors occur in the output due to changes in the D/A conversion circuit over time and temperature fluctuations, so it is difficult to reproduce the data signal reproduced at the demodulation stage on the receiving side. There was a problem that the bit error rate deteriorated.

The present invention has been made in view of the above problems, and
A modulation device that can eliminate the deterioration of the data signal hit error rate on the receiving side by detecting fluctuations due to changes over time and temperature fluctuations from the initial adjustment of the /A conversion circuit and automatically correcting them. The purpose is to provide.

[Means for Solving Problems] In order to achieve the above object, the modulation device of the present invention includes a D/A conversion circuit that converts a digital signal into an analog signal and outputs the same, and an output signal of the D/A conversion circuit and a reference. and an error signal generation circuit that generates an error signal by comparing the input data signals, and an error signal output from the error signal generation circuit when manually inputting multiple input data signals and outputting an address signal corresponding to the data signal. an address generation circuit that modifies the address signal; and a memory circuit that receives the address signal output from the address generation circuit and outputs a digital signal corresponding to the input data signal to the D/A conversion circuit. , and a modulation circuit that performs multilevel polyphase modulation on a carrier signal using a signal outputted from the memory circuit and converted into an analog signal by the D/A conversion circuit as a modulation signal.

[Example code] Hereinafter, the present invention will be explained in detail based on the drawings.

FIG. 1 is a block diagram of a modulation device according to an embodiment of the present invention. Note that parts common to or corresponding to those of the conventional example are denoted by the same reference numerals.

In the figure, 10 is an error signal generation circuit.

In the above configuration, first, the human data signal S4. .

S 12+ S 21+ 92□ are input to the address generation circuit 1 from input terminals 21, 22, 23, and 24, respectively. At this time, the error signal from the error signal generation circuit 10 is also input to the address generation circuit 1. Then, the address generation circuit 1 is controlled by this error signal, and the input data signal S7. .

A specific address is designated and output for each of S12+521+52□. A human input signal whose address is designated in the address generation circuit I reads out data signals stored at the designated addresses in the memory circuits 2 and 3, respectively. Here, the data signal stored at each address is the same as the conventional one.
This is a digital value corresponding to the correction level ζ of nonlinear distortion caused by an amplifier circuit or the like in the transmission system, or a digital value for band-limiting the signal. The data signals read from the memory circuits 2 and 3 are each D
The signals are input to /A conversion circuits 4 and 5 and converted into analog signals. Further, these analog signals are input manually to 0-π phase modulation circuits 6 and 7. Then, in the 〇-π phase modulation circuit 6, a predetermined carrier wave signal manually inputted from the terminal 25 is input to D.
/A conversion circuit 4 output analog signal is phase modulated to generate and output a P signal. Further, in the 0-π phase modulation circuit 7, the carrier wave signal whose phase has been shifted by 90 degrees is phase-modulated by the analog signal of the D/A conversion circuit 5 by the π/2 phase shift circuit 98, and a Q signal is generated.

Further, these P signals and Q signals are inputted to a combining circuit 9, orthogonally combined, and outputted from a terminal 26.

The operations of the 0-π phase modulation circuits 6 and 7, the π/2 phase shifting circuit 8, and the combining circuit 9 are the same as in the conventional example described above.

Here, for example, if the output of the D/A conversion circuit 4 fluctuates by +ΔV, the output level of the 0-π phase modulation circuit 6 also fluctuates by +ΔV, as shown in FIG. For this reason, the sixth
The 16 white dots shown in the figure should also change to the positions of black dots.

However, the analog signals output from the D/A conversion circuits 4 and 5 are input to the error signal generation circuit 10. For this reason,
The error signal generation circuit 10 outputs a predetermined signal to the address generation circuit 1 to erase this error.

Here, the operation of this error signal generation circuit 10 will be explained in more detail.

FIG. 2 is a block diagram of the error signal generation circuit.

In the figure, 11.12 is an amplifier circuit, 13 is a sampling circuit, 14.15 is an A/D conversion circuit, and 16 is a reference voltage generation circuit. Further, 27° and 28 are analog signal input terminals, 29 is a control signal input terminal, and 30 and 31 are error signal output terminals.

In the above configuration, the analog signals output from the D/A conversion circuits 4 and 5 are sent to the analog signal input terminals 27 and 28, respectively.
From there, power is supplied to amplifier circuits 11 and 12. Further, a reference voltage generated from a reference voltage generation circuit 16 is also input to the amplifier circuits 11 and 12. Therefore, the amplifier circuits 11 and 12 amplify the variation of the analog signal and output it to the sampling circuit 13.

Here, in FIG. 4, the sampling circuit 13 (S
ll, S12. S21. 522) is represented by (
0000), (0100), (1100).

The signals of only four points (1000) are extracted.

Then, the four points where the distance from the origin is the maximum where the P axis and the Q axis intersect are selected. Specifically, this is
This is done by inputting the control signal from the address generation circuit 1 to the sampling circuit 3 via the control signal input terminal 29.

In this way, four amplified analog signals are selected, and the selected analog signals are respectively input to the A/D conversion circuits 14 and 15. This A/D conversion circuit 14.1
5 generates error signals corresponding to fluctuations in the analog signal, so the respective error signals are output from the error signal output terminals 30 and 31. This error signal is then input to the address generation circuit 1.

The address generation circuit 1 uses the error signal thus input as an address signal for correcting fluctuations due to changes over time from the initial adjustment of the outputs of the D/A conversion circuits 4 and 5, and temperature fluctuations. .

Then, it is output to the memory circuits 2 and 3 together with the address signal corresponding to the input data signal.

The memory circuits 2 and 3 read the correction data using this address signal, but due to the input of the above addresses, fluctuations due to changes over time from the time of initial adjustment that occur in the output of the D/A conversion circuit 4.5 are detected. In other words, data signals corrected for temperature fluctuations are read out. As a result, the 6th
In the figure, all black circle signal points that have fluctuated by ΔV are returned to white circle signal points. Therefore, all fluctuations in the outputs of the D/A conversion circuits 4 and 5 are corrected, and the data signal SII+ 812+ 5 is reproduced at the demodulation stage on the receiving side.
The degradation of the bit error rate of 21+922 is also completely eliminated.

It should be noted that the present invention is not limited to the above embodiments, but includes various modifications within the scope of the gist. For example, in the above-mentioned embodiment, the operation of the modulation device using the 16QAM method was explained, but the present invention
It goes without saying that the present invention is not limited to the case using the AM method, but can also be effectively applied to cases using other multivalued polyphase modulation power methods.

[Effects of the Invention] As explained above, the present invention automatically corrects all the fluctuations caused by changes over time from the time of initial adjustment that occur in the D/A conversion circuit output, and the temperature fluctuations, thereby improving the performance on the receiving side. This has the advantage that it is possible to provide a modulation device that can completely eliminate deterioration in the hit error rate of the data signal reproduced in the demodulation stage.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a modulation device according to an embodiment of the present invention, FIG. 2 is a block diagram of an error signal generation circuit in the modulation device of FIG. 1, and FIG. 3 is a block diagram of a conventionally used 16QAM.
4 is a diagram showing the data arrangement of the modulated output in the 16QAM method, and FIG. 5 is a block diagram of the modulation device of the 16QAM method.
Human power level vs. output bell characteristic in a π phase modulation circuit (
FIG. 6 is a diagram showing the data arrangement in the phase plane of the 16QAM system. 1 Near address generation circuit 2.3: Memory circuit 4.5: D/A conversion circuit 6.7: O-π phase modulation circuit 8: π/2 phase shift circuit 9: Synthesis circuit 10: Error signal generation circuit

Claims (1)

[Claims] D/A that converts digital signals to analog signals and outputs them
a conversion circuit; an error signal generation circuit that compares the output signal of the D/A conversion circuit with a reference signal and generates an error signal;
When inputting multiple input data signals and outputting address signals corresponding to the data signals, an address generation circuit corrects the address signal using an error signal output from the error signal generation circuit, and an output from this address generation circuit. a memory circuit that inputs an address signal to be input and outputs a digital signal corresponding to the input data signal to the D/A conversion circuit; 1. A modulation device comprising: a modulation circuit that performs multi-level polyphase modulation on a carrier signal using a signal converted into a modulation signal as a modulation signal.