JPH01212930A - Multipoint modem system - Google Patents

Abstract

PURPOSE: To provide a reliable data MODEM communication system by achieving the high-speed and exact synchronism of a master MODEM receiver attached to a master MODEM. CONSTITUTION: A master MODEM receiver 80 is constituted by providing an analog/digital(A/D) converter 84 forming a sampling means for receiving an analog signal from a transmission line, a timing recovery circuit 98 for supplying a timing signal to the A/D converter 84, an interpolation filter 88 having an input connected to the output of the A/D converter 84 and the output of the timing recovery circuit 98, and a filter coefficient calculator 150 for calculating the coefficient of a filter for the interpolation filter 88 while a receiver means receives a training signal transmitted from one of remote MODEM through the prescribed expression of interpolation.

Description

[Detailed Description of the Invention] [Field of Industrial Application] This invention includes a master modem and a number of remote modems, and the master modem has a sampling means for receiving all analog signals from a transmission line and a timing control for the sampling means. The present invention relates to a multipoint data communication system including a modem receiver having timing recovery means for providing a signal.

[Conventional technology]

A multi-point data modem communication system of the type of this invention is disclosed in European Patent No. 0.169.548. The system's mask station polls several remote stations and its modem provides a continuous carrier signal. This signal is received by each remote modem. If the terminal identification included in the poll does not match the remote station identification, the poll is ignored. A remote station that acknowledges the data sends two types of messages: the first block of data,
or a character sequence indicating that no data is to be transmitted. A remote stage signal will use a carrier signal that is switched when sending its message by either turning the modem all on (one transmit request) before transmitting, or by turning it off after transmitting.

Once a remote station becomes active, the mask station modem senses the remote modem's carrier, derives the register timing signal, sets internal gain parameters, and establishes the transmit path for that active modem. Obtain the equalization value to compensate for.

Each modem communication channel will have a different path with different characteristics corresponding to attenuation, amplitude and delay distortion and phase degradation. Therefore, the mask station modem must compensate each communication channel individually. A communication channel between each remote master is required for reliable data transfer. request the connected modem to send a training sequence so that the master modem receiver can obtain the parameters. Therefore, the master modem will not be able to connect to the receiver operating A during the initial training sequence.
'Obtain the scillata and equalizer coefficients and store the parameters and coefficients in the memory location allocated for the defined remote modem. remembered/4
The parameter includes a meter for compensating for data timing clock deviations and an equalizer coefficient. At the beginning of a subsequent transmission, the master modem receiver nomurameter and coefficients are loaded from the prestored values in the corresponding memory locations. During subsequent transmissions from a remote modem, that modem is known to the master modem by a period and a set of frequencies. During short remote-master transmissions, each training sequence occupies a major portion of the transmission time. During training for transmission of high data rates such as 14,400 bits/min, the receiver operating parameters must be set correctly to obtain high data reliability.

[Problems to be Solved by the Invention] High-speed data communications using conventional data modem communication systems have problems with transmission accuracy and do not provide high reliability.

Accordingly, it is an object of the present invention to provide a reliable data modem communication system by achieving fast and accurate master modem receiver synchronization.

[Means for solving problems]

The present invention solves the above problems by providing a multipoint data modem communication system configured as follows.

Therefore, according to the present invention, the mask module is connected via the transmission line.
A master modem connected to multiple remote modems including a multi-mounted modem receiver, sampling means adapted to receive an analog signal from a cut-off transmission line mounted on the modem receiver, and a modem receiver attached to the modem receiver. interpolated timing recovery means mounted on the modem receiver and having an input connected to the output of the sampling means and an output of the timing recovery means; , attached to said modem receiver and calculating filter coefficients for said interpolation filter means while said receiver means is receiving a training signal transmitted by one of said remote modems according to a predetermined interpolation formula; and filter coefficient calculation means.

〔Example〕

Figure 1 shows master modem 12 (!: 3 (DIJ mode))
% fA 14, 16, 18. In practice, more or fewer remote modems may be used. Master modem 12 is a master data terminal equipment (DTE)
) connected to unit 20 and remote modem 14,1
6.18 is a remote data terminal equipment (DTE)
) connected to unit 22°24.26. Master·
Modem 12 connects each modem 14, 16 . It is connected via a four-wire telephone transmission line 28 to a branch point 30 connected to Z8. As before, 4-wire telephone line 28° 32.34.3
6 includes a transmit line pair and a receive line pair.

Data normally follow CCITT recommendations v, 33.

Using carrier frequency 1800 Hz, modulation frequency 2
400Hz (2400 bits per symbol rate) using 14.400 b/s (7 second pit) data bits.
Sent via email. The modem operates at a nominal sample clock frequency of 9600 Hz, which is four times the modulation frequency.

FIG. 2 is a block diagram of the modem transmitter of one of the modems 12, 14, 16, 18 of FIG. Digital signals from connected data terminal equipment (DTE) are sent to scrambler 52 via input line 5o. The output of scrambler 52 is connected via line 54 to the input of encoder 56. Initialization control circuit 57
is also connected to encoder 56 via line 58. Initialai! Control circuit 57 enables encoder 56 to generate a training signal. The output of encoder 56 is connected via line 59 to a low signal filter 60, whose output is connected via line 62 to a modulator 64. The output of modulator 64 is connected via line 66 to a digital-to-analog (D-A) converter 68 whose output is connected via line 7.
0 to the associated telephone transmission line.

FIG. 3 is a block diagram of master modem receiver 80 included in master modem 12 (FIG. 1). The signals received from the associated transmission line are fed via input line 82 to an analog-to-digital (A-D) converter 84 forming a digital sampling means. A/D converter 84 has an output connected via line 86 to an interpolation filter 88, the structure and operation of which will be described below. Interpolation filter 88
The output of is connected via line 90f to a bandpass filter 92, an energy on/off control circuit 94, a discrete Fourier transform (DFT) calculator 96, and a timing recovery circuit 98. The output of bandpass filter 92 is line 100
is connected to demodulator 102 via line 104, and its output is connected to line 104.
It is connected to the gain control circuit 106 via. The output of the gain control circuit 106 is connected to the equalizer 1 via the line 108t.
10 and the output of equalizer 110 is connected via line 112 to automatic phase control circuit 114. The output of automatic phase control circuit 114 is connected to decision circuit 11 via line 116.
8 and its output is connected to a descrambler 122 via line 120. The output line 124 of the descrambler 122 is connected to the data terminal unit 20 (first
(Figure).

Energy on/off control circuit 94 is connected to initialization control circuit 132 via line 130. When energy on/off control circuit 94 senses energy on line 90, it sends a signal via line 130 to initialization control circuit 132 to initiate its operation. Initialization control circuit 132 supplies control signals to gain control circuit 106, DFT calculator 96, and timing recovery circuit 98 via husbandry control lines 134, 136, and 138.

The output of DF'I' calculator 96 is connected via line 140 to a phase segment detector 142 whose output is connected to line 1.
43 to a phase-time shift converter 146. The output of phase-to-time shift converter 146 is connected via line 148 to a coefficient calculator 150 which is connected via line 152 to interpolation filter 88 to determine the coefficients of interpolation filter 88. It works like that. Timing recovery circuit 98 is connected to line 154
It is connected to the A-D converter 84 via. The master modem receiver 80 includes a receiver nomurameter storage unit 156 and an equalizer 110° DFT calculator 96 transmitted over lines 157°, 158, and 159, respectively.
and the values from the timing recovery circuit 98 are stored.

FIG. 4 is a detailed circuit diagram of timing recovery circuit 98 (FIG. 3) included in master modem controller 80. The timing recovery circuit 98 (FIG. 3) is 600 H2
Bandpass filter 160 and 3,000Hz bandpass filter 1
62 and operates as a phase-locked loop (PLL). These frequencies/”t=600Hz and f
2 = 3,000 Hz is derived from the equation below.

f 1=fc −1/2 fb −・・・−−(
1a) f z = fc + 1/2 fb
・・・・・・・・・・・・(1b) Then f. ""18
00Hz carrier frequency fb=2400Hz modulation frequency filter 160 is connected as shown in FIG.
62,164. Includes adders 166, 168 and multiglazers 170, 172, 174, 176.

Filter 162 includes delays 180, 182, adders 184 .
186 and multiplier 188, 190° 192.1
Contains 94. Multiplier 170, 172° 174.
176.188, 190, 192 and 194 are supplied with the following multiplication coefficients.

a s = -1,856 a2 == 0.960 a3 = -0,928 a4 : -0,315 as = 0.630 a a = 0.960 a 7 = 0.315 ag = 0.928 Filter 160, The first outputs 196 and 198 of 162 are connected to a multiplier 200, respectively.

The second outputs 202, 204 of filters 160, 162 are connected to multiplier 206, and multiplier 20
The 0.206 output is connected to adder 208. The output of adder 208 is connected via line 210 to output lines 210 and 214.
It is connected to a non-switch 212 that performs a 4:1 processing speed reduction between the two.

Output line 214 of switch 212 is connected to leaky interpolator circuit 216 and gate 218. The leaky interpolator circuit 216 has a delay 220 . It includes an adder 222 and multipliers 224 and 226, and is connected as shown in FIG. Multiglayer 224.22
6 is supplied with the following coefficients.

b, = 0.999 b2 = 0.001 The output 228 of leaky interpolator 216 is connected to adder 218. A leaky interdator operates as an in/taborator with a small amount of leakage in its contents and serves to provide an output signal that approaches the average input signal over a period of time. The averaging period is 1/(1-bt
) corresponding to the sample period. The amplification between input and output is bt
/(i-bl). The leaky interpolator circuit can be thought of as a low-pass filter that multiplies the sample frequency by a very low cutoff frequency of (1-bt).

Age 218 connects line 230 to summer 232, which includes an adder 234 whose output is connected to the input of delay 236, whose output is connected to the input of adder 234.
connected via. The output of Summer 234 is Adder 21
It increases or decreases when the output of 8 is non-zero (non-zero, positive or negative). The output of summer 232 is connected via line 238 to an adjustment circuit 240 which compares the output of summer 232 to a fixed threshold and via control line 244 adjusts the operation of modem clock generation circuit 242 according to the result of the comparison. do. Regulating circuit 240 is connected to line 246''f.

is connected to provide a signal that clears the summer 232 delay 236 through the summer 232. Modem clock generation circuit 24
2 controls the timing of sampling to the A/D converter 84 via line 154.

FIG. 5 is a detailed circuit diagram of interpolation filter 88 and bandpass filter 92 included in master modem receiver 80 (FIG. 3). 5stii stages 251-0 to 251 of interdelation filters
-8 stage buffer shift register 250. Input line 86 from A/D converter 84 is connected to buffer shift register stage 251-0. The outputs from the buffer shift register stages 251-0 to 251-8 are connected to respective multipliers 252-0 to 252-8, whose other inputs include L4,
A-3.

A-21A-1+AO+Al sA2 +A3
The filter coefficients of sA4 are supplied. multiplier 2
The outputs of 52-0 through 252-8 are connected to adder 254 whose output is connected to line 90. In addition to being connected to an energy on/off control circuit 94 and a timing recovery circuit 98, line 90 is connected via line 256 to the first stage of a second buffer shift register 258. The buffer shift register 258 has 32 stages 259-0 to 259
-31 and forms part of bandpass filter 92. Buffer register stages 259-0 to 259-31 are connected to respective multipliers 260-0 to 260-31 having coefficients C0 to Csl applied thereto, respectively. The values of these coefficients are selected to provide the desired bandpass characteristics of bandpass filter 92. Multiplier 260-0
The output of ~260-31 is connected to adder 262, whose output forms the output 100'i of bandpass filter 92.

Next, the operation of the above circuit will be explained. Master modem 12 (Figure 1) uRemote modem 14.16.
18i, f-Russle. Master modem 12 is remote
All modems 14, 16, 18 continuously transmit the carriers they receive. One of the remote modems 14, 16, 18 responds to the master modem by sending information back to it. Specific remote modems 14, 16.1
8 first turns on its carrier and sends a training sequence to transmit data to master modem 12. Master modem 12 detects the carrier and
The timing signal for the D converter 84 (FIG. 2), the final amplification key of the gain control circuit 106, and the equalizer coefficients for the equalizer 11o (FIG. 3) are determined.

At the beginning of the first transmission from each remote modem 14.16.18, an initial training sequence consisting of six segments SG1-S06 is transmitted as shown in Table I. The first column of table l below (
1) represents the number of symbol intervals of the respective segment) SG1% SG6, and the second column (2) represents the corresponding approximate time in milliseconds.

Each segment is defined as follows.

SC1: Segment 1: Alternative (180° phase alternative) SG
2: Segment 2: Equalizer conditional pattern SG3:
Segment 3: Structural sequence SG4: Segment 4:
Alternative (180° phase alternative) SG5: Segment 5: Equalizer conditionality? Turn SG6: Segment 6: Scrambled All Binary 1 The total number of symbol intervals in the initial training sequence is 3
534, corresponding to a total time of approximately 1472 m') seconds. segment) SGI 1sG21sG6 is CCIT
T recommendation v is a conventional training signal segment corresponding to the recommended pressure. Segment s03 contains information regarding setup conditions such as data bit rate, nature of modulation and other transmission related/'P parameters. Segment S04 is used for calculations regarding timing adjustments. Segment SG5 provides the slight readjustment of the equalizer coefficients required as a result of transmitting segment S03.

During the training sequence (initial), the master modem-receiver 30 (FIG. 3) obtains the operating parameters and equalizer coefficients, and obtains the A? Receiver for parameters and coefficients (parameter storage unit) 156
(FIG. 3) relative to the transmitting remote modem. Each subsequent transmission by the remote modem begins with a short training signal, referred to as a subsequent training segment, consisting of only one segment, as shown in Table 2 below.

Table 2 A remote modem can be identified by transmitting a set of identification frequencies in synchronization with a subsequent training sequence. Therefore, previously stored receiver parameters and coefficients are stored in the receiver no'? from the identified location in parameter storage unit 156.

A very approximate signal period (10.4617 in this example)
(seconds) is sufficient to adjust the receiver timing control.

i6[i1d Filter coefficient Ak for interpolation filter 88 (k=-4, . . . , 0. . .
, +4) is included in the coefficient calculator 150 (FIG. 3). Interpolation・
The filter 88 is based on a 9th order Lagrange interpolation equation and uses a residual time shift value P (described below) ft. Therefore, interpolation
Filter output sample s0. n is derived from the equation:

So, n=AJP)・Si, n-4+・+ Ao(P)
Si, n +A4(P)・si, n+4...
...(2) Here, Si, n = nth input sandal So, n = nth output Sansol P = residual time shift = -4, ..., O, ..., +4 and ... ...(3) The residual time shift value P is a continuous curtain P, p3.・・・
- Input line 270 (sixth line) connected to generate pg
Figure). Each storage location in the read-only memory is divided into nine adders 280-1 and 280-2 as shown in FIG.
..., 280-9 are connected to nine groups of multipliers 278-1 to 278-9, and the outputs of the adders are connected to interpolation filter multipliers 252-0 to 252, respectively. -8 (Fig. 5) output lines 282-1, 282-2. ...,
9 filter coefficient values kg t for each of 282-9
Ls #...+A4 is supplied.

As mentioned above, during the first transmission from the remote modem, the initial training sequence shown in Table I is transmitted. During this initial training sequence, a vector of complex values Vi is computed in DFT calculator 96 (FIG. 3) and stored in receiver parameter storage unit 156. In more detail, during segment S04 of the initial training sequence, the following calculations are performed.

where S, is the consecutive receiver sample, 1, and N is 1
It is 92. These two values are multiplied as follows.

v, = v, ・V* ...scream...
(6) 1 1 , 3000 1 , 600 In this equation, vti, 600 is a complex pair of vt, 6oo,
v.

is stored in the receiver parameter storage unit 156 as the receiver tZ scillata. At this point,
Leaky integrator 216 (Figure 4) delay 22
The value g formed by the content of 0 is stored in the receiver parameter storage unit 156.
is memorized.

During post-sono training, the receiver rough data is used to set the sample clock timing to match when the equalizer coefficients were stored in the receiver parameter storage unit 156. . Specifically, during subsequent training, the timing adjustment TI seconds is provided by the following equation:

T1=T, 10T3...
(7) In equation (7) above, T3 compensates for the timing deviation between the data timing clock of the associated remote modem 14.16.18 and the data timing clock of the master modem 12. represents time.

That T3 is Discrete Fourie from the halfway point.
During the extension period until the end of the rTransform calculation, it is calculated according to the following equation:

T3=6・g・(0,002/2400) ・・
. . . (8) where g is the storage nomurameter derived from the receiver parameter storage unit 156 and the factor 0.002/2400 is the modem clock generator 242 (FIG. 4) during a single period interval. ) represents the timing shift that can be applied to

Its contribution T2 is calculated from the following equation.

where vi is the vector value stored in storage unit 156 and v8 is calculated by DFT calculator 96 for all 48 samples in total during the subsequent training period. More specifically, it is first calculated as follows.

where 88 are consecutive receiver samples and N=4
It is 8. These two results are multiplied to give:

v = v ・V* ...Song...
tlls s, 3000 g, 600 ne where V is a complex pair of ■.

Using the value of vl read from s, 600 s, 600 storage unit) 156 and the calculated v8 +011, T2 is calculated in equation (9). In order to perform correct timing control, by rotating the vector product v,・i through a number of segments t,
Generate a resulting vector with a phase angle between -45° and +45°. This is phase segment detector 1
It will be held at 42.

The phase rph of the resulting vector placed between -45° and +45° is then derived according to the flowchart of FIG.
Figure 3).

FIG. 8 shows the initial value O(
zero) and 0.3927 loaded delay 290.29
2 represents a circuit for calculating the vector phase of a calculation result including 2. Also, multipliers 294, 2 are included in the circuit.
96,298,300,302゜304.306,30
8.309, an adder 312 whose output is connected to a comparator 314 and acts as a subtracter, and adders 310, 312,
313 is included.

A certain circuit element shown in FIG. 8 has the following constant values.

Age-310: do = 1 Multiglayer 296: d l = 0.31
755 Multiglayer 300: a2 = 0.2
0330 multiplier 306: d3=-1 or +1
(Output of comparator 314) Multiglayer 309: d<=0.5? A
/-F-pliers 308: d, = 0.63
602 (=2/7r) Also, the multiglayer 304 is supplied with the value vx, and the adder 312 is supplied with the value V.

vX and V are the real and imaginary parts of the vector av, ·v*. The output of the adder 312 is V, <W is the comparator 31 which supplies the output signal d3=-1 or +1 according to vy≧W.
Connected to 4.

In the flowchart of FIG. 7, the procedure begins at block 320.

Block 322 sets the following:

V=R(V,・v*) Xel! V=I(V,・v*) mts rph=0 Δrph = 0.3927 n = Q Where, Re and Im represent the real part and imaginary part, respectively, and r
ph represents the phase (in radians) of the answer vector v=(vx, v,), and n represents the counter value that determines the length of the procedure.

At block 324, the following equation is calculated:

U = F(rph) = rph+o, 31755(
rph)3+ 0.20330 (rph)5...-
・---ell) The above equation α or the action F(rph)
This is a known approximate calculation for =tan(rph). This calculation is performed using circuit elements 296.degree. 293.300, 310 (FIG. 8).

In the next block 326, the product W = Vx-U is calculated (at multiplier 304 in Figure 8). At the next block 328, a determination is made as to whether vyWW. If no, the means goes to block 330 where rph is increased by Δrph.

If yes, the procedure goes to block 332 where rph is decreased by Δrph. Block 334
, it is determined whether n ) 9. If no, the procedure goes to block 336 where n becomes n+1 and goes to block 338 where Δrph is 0.5Δrp
h (at multiglayer 309 in FIG. 8) and returns to block 324. If the decision at block 334 is yes, the procedure goes to block 340 and calculates r=(2/C)
• rph is performed (at multiplier 308 in Figure 8). The procedure then ends as indicated at block 342. In this way, the residual time shift value r is calculated.

Equation (7) defines the timing adjustment T1 as an absolute time value (in seconds). However, it is better to rewrite equation (7) as follows.

Pl=P2+P3 ・・・・・・・・・
(To) Here, P2 and P3 represent the contribution of the time shift in fractions of the sample interval, and the direct PL of the sum also represents the fraction of the sample interval. The contribution P2 is therefore the residual time shift value r calculated as above in fractions of the sample interval.
formed by. In more detail, P2=r (-0,5≦r<0.5)
・”'・'(Ll Furthermore, since P3・(1/9600)=T3, equation (8)
using P3=6・g・(0,002/2400) or P3=0
．． 048g ・・・・・・・・・
During initial or subsequent training before loading the calculated coefficients into the interpolation filter 88 (FIG. 3), the interpolation filter uses the coefficients A,=1 and A-,=A,= ...=A4=0. Therefore, the value of P is calculated as follows.

P = P l-' (if P 1) 0.19) P
=P1 (When P is 0.19) The calculation of P by the above calculation is performed by the phase-time shift converter 146 (FIG. 3).

The value of P calculated as above is used as the coefficient Ak(P) (
k=-4,...,0. ...+4 is used for calculation. But during the initial training sequence.

Compromise time shift doors are used and interpolation
Calculate filter coefficients. Application of a compromise time shift door during initial training improves subsequent training. Next, the occurrence of the compromise time shift door will be explained.

The amplitude distortion produced by interpolation filter 88 is independent of the sign of P. Therefore, the compromise time shift P* based on minimum amplitude distortion is approximately 0.25. However, interpolation filter 88 also generates delay distortion. The interpolation filter 88 has a nonlinear phase characteristic depending on the time shift value P. An experimental effort was made to determine the optimal compromise time shift P* for deterioration during subsequent training. For signal degradation at the end of the signal path through the telephone transmission line, the interpolation filter 88 and equalizer 110 were measured with a number of alternatives and an optimal compromise time shift) P''=-0,19 was determined. .

This value P"=-0,19 is used in the circuit of FIG. 6 for the calculation of the interpolation filter coefficients during the initial training sequence.

As mentioned above, application of a compromise time shift door during initial training improves its performance during subsequent training. Therefore, it was found that without the application of time shifts during initial training, the impairment in subsequent training sequences is better than 36 dB below the signal level.

At a time shift value of P=-0, 25 the failure is 39d
Better than B, compromise time shift) At P''=-0,19 the impairment is better than 41 dB.

Thus, a compromise time shift) P"=-0,19 is applied during the initial training sequence. During this initial training sequence, the equalizer coefficients are P*=-0.
, 19, taking into account the added distortion caused by the iteration filter 88. As previously discussed, these equalizer coefficients are stored in the receiver parameter storage unit 156 and accessed in response to subsequent training sequences during which residual time shifts (Pt) occur as previously described.

〔Effect of the invention〕

This master modem-receiver 80 has a very high data transmission rate (14,400 bps (bits per second)) during a very short training period (e.g. 10.4 milliseconds).
) can achieve fast and accurate synchronization. Furthermore, since the interpolation operation is applied to signal samples already received and stored in the buffer shift register 258 (Fig. 5), even signal samples received before the completion of the subsequent initialization operation need to be discarded. instead, it has the advantage of being able to contribute to faster effective operation of the bandpass filter 92.

Essentially, the time required for the master modem receiver to synchronize is reduced in proportion to its total transmit time.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a data modem communication system including a master modem and multiple remote modems; FIG. 2 is a block diagram of a remote modem transmitter; and FIG. 3 is a block diagram of a master modem receiver. Figure 4 is a partial block wiring diagram of the timing recovery circuit included in the master modem receiver; Figure 5 is a block diagram of the interpolation filter included in the master modem receiver. FIG. 6 is a partial block diagram showing the coefficient calculator for the ink and poration filter; FIG. 7 is a partial block diagram showing the calculation of the residual time shift value. flow diagram. FIG. 8 is a circuit diagram showing calculation of the residual time shift value. In the figure, 10...multipoint data modem communication system, 3
0... Branch point, 12... Master modem, 14°1
6.18...Remote modem, 22.24°26.
...Remote DTE, 20...Master DTE, 162
゜164...Delay, 166.168...Adder, 1
70°172.174,176...multiplier,
258,250... Panfa, Shift Reno Star, 25
2-0 to 252-8...multiplier, 260-0
~260-31... Multiplier, 254.262
... adder, 88 ... interpolation filter, 92 ... bandpass filter. FIG. 6

Claims (7)

[Claims] (1) A multipoint data modem communication system having a master modem connected to a plurality of remote modems via transmission lines, the modem receiver attached to the master modem; and the modem receiver attached to the master modem. a sampling means attached to the modem receiver for receiving an analog signal from a transmission line; a timing recovery means attached to the modem receiver for providing a timing signal; an input connected to the output of the sampling means and an input of the timing recovery means; interpolation filter means of said modem receiver having an output connected thereto; 1. filter coefficient calculation means for calculating filter coefficients for said interpolation filter means during reception by said receiver means of a training signal transmitted from said interpolation filter means. (2) The system according to claim 1, wherein the filter coefficient calculation means uses a Lagrange interpolation formula. (3) the modem receiver includes a plurality of first multipliers, and the interpolation filter means includes a plurality of first buffers having outputs connected to the multipliers to which the filter coefficients are supplied; 3. The system of claim 2 including a shift register stage. (4) The modem receiver includes bandpass filter means having an output connected to a data signal generating means, and an output of the interpolation filter means is connected to the bandpass filter means to generate a data signal. The system described in Section 3. (5) said modem receiver further includes a second multiplier, said bandpass filter means having a plurality of second buffer shifters having outputs connected to said second multiplier provided with bandpass filter coefficients; 5. The system of claim 4, further comprising a register stage. (6) The system according to claim 2, wherein the Lagrange interpolation equation comprises the following equation corresponding to the 9th order interpolation, A_k(P)=[(-1)^kP(P^ 2-1) (P^
2-4) (P^2-9) (P^2-16)]/[(4+
k)! (4-k)! (P-k)] Then, k=-4,・
. . , 0, . . . , +4A_k(P) represents the k-th 1 value of the coefficient of the interpolation filter, P=time shift value. (7) The filter coefficient calculation means includes a DFT calculation means for performing discrete Fourier transform (DFT) calculation;
a phase segment detector connected to the FT calculating means for detecting the phase value of the output of the DFT calculating means; and a phase segment detector connected to the output of the phase-time shift converting means for detecting the phase value of the output of the DFT calculating means;
7. The system of claim 6, further comprising phase-time shift conversion means for calculating .