JPH01212373A - Inspection of lsi mounted printed wiring board - Google Patents

Inspection of lsi mounted printed wiring board

Info

Publication number
JPH01212373A
JPH01212373A JP63036848A JP3684888A JPH01212373A JP H01212373 A JPH01212373 A JP H01212373A JP 63036848 A JP63036848 A JP 63036848A JP 3684888 A JP3684888 A JP 3684888A JP H01212373 A JPH01212373 A JP H01212373A
Authority
JP
Japan
Prior art keywords
lsi
pwb
node
terminal
printed wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63036848A
Other languages
Japanese (ja)
Inventor
Tetsuo Yoshino
吉野 哲夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP63036848A priority Critical patent/JPH01212373A/en
Publication of JPH01212373A publication Critical patent/JPH01212373A/en
Pending legal-status Critical Current

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  • Tests Of Electronic Circuits (AREA)

Abstract

PURPOSE:To efficiently detect inferiority due to the manufacturing factor on a PWB by separating the same from the internal operation of an LSI, by bringing the terminal of the LSI mounted on the PWB to a high impedance state by applying a signal thereto from the outside. CONSTITUTION:The terminal 7 of an LSI 1 is brought to a high impedance state on the basis of the signal applied to the terminal 7 by a switch group 6. Pin electronics 2 sends out an inspection pattern to the node on a PWB 8 to be inspected and detects the output value of the node to compare the same with an expected value and is connected to the node on the PWB 8 by a probe 3. When the PWB 8 is inspected, a signal for opening the switch group 6 is sent out to the terminal 7 from the pin electronics 2 to send out a pattern not according to the internal logic of the LSI 1 to the node between the LSI 1 and other circuit 5 to perform inspection. By this method, the trouble generated on the PWB 8 by a cause other than the LSI 1 can be efficiently detected.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明はLSIを搭載したプリント配線板の検査法に関
する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for inspecting a printed wiring board equipped with an LSI.

〔従来の技術〕[Conventional technology]

従来LSIを搭載したプリント板(以下PWB)の検査
にはPWBのエツジコネクタを通じて検査用のパターン
を送出し、同;ネクタの出力ピンに現われる出力をあら
かじめ用意した期待値と比較して良否を判定するボード
テスタと、PWB上のLSIその他部品の端子をプ四−
ビングする剣山状のテストフィクスチャーを有し主とし
て部品の接続、定数値等のチエツクを行なうインサーキ
ットテスタの2種のテスタが用いられていた。
Conventionally, when inspecting a printed circuit board (PWB) equipped with an LSI, a test pattern is sent through the edge connector of the PWB, and the output appearing at the output pin of the connector is compared with a pre-prepared expected value to determine pass/fail. Connect the terminals of the LSI and other parts on the PWB with the board tester.
Two types of testers have been used: an in-circuit tester that has a test fixture in the form of a swinging pin, and that mainly checks component connections, constant values, etc.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述した従来のボードテスタでLSIを搭載したPWB
を検査するにはLSIの動作を記述したライブラリを用
意し期待値を計算しなければならない。またPWBの配
線パターンのショート。
PWB equipped with LSI using the above-mentioned conventional board tester
To test this, it is necessary to prepare a library that describes the operation of the LSI and calculate the expected value. Also, a short circuit in the PWB wiring pattern.

オープンを効率よく検出するにはLSIの動作によって
得られる出カバターンでは不十分の場合が多かった。さ
らにあらかじめ検査をしであるLSIを搭載した場合も
PWBの検査のためLSIも含めて検査せざるを得す検
査時間が長くなるという欠点があった。一方インサーキ
ットテスタではテストフィクスチャーからのアナログ的
な測定は可能であるもののLSIを切り離すことができ
ないためパターンをこのフィクスチャー上のプローブよ
り送出することはできないという欠点を有していた。
In many cases, the output pattern obtained by the operation of the LSI is insufficient to efficiently detect an open circuit. Furthermore, even if a pre-inspected LSI is mounted, there is a drawback that the inspection time is increased because the LSI must also be inspected in order to inspect the PWB. On the other hand, in-circuit testers are capable of analog measurements from a test fixture, but have the disadvantage that the LSI cannot be separated, and therefore a pattern cannot be sent out from a probe on the fixture.

〔課題を解決するための手段〕[Means to solve the problem]

本発明のPWB検査法は、パターンを送出、受信する機
能を有し、PWB上の任意のノードをプロービングする
ことのできる複数本のプローブを有スるテストフィクス
チャーを用い、端子の一部またはすべてを外部より与え
られた信号に従ってハイインピーダンス状態とすること
のできるLSIを搭載したPWBを検査する時、LSI
の端子をハイインピーダンスとしてプローブをあてて、
検査のための論理信号列を加えている。
The PWB inspection method of the present invention uses a test fixture that has a function of transmitting and receiving patterns and has multiple probes capable of probing any node on the PWB. When inspecting a PWB equipped with an LSI that can put everything into a high-impedance state according to externally applied signals, the LSI
Apply a probe to the terminal as high impedance,
A logic signal string for inspection is added.

〔実施例〕〔Example〕

次に、図面を参照して本発明をより詳細に説明する。 Next, the present invention will be explained in more detail with reference to the drawings.

第1図は本発明の第1の実施例である。ここで1は端子
7に加えられた信号によってスイッチ群6により端子な
ハイインピーダンス状態とすることのできるLSIであ
る。また2は検査しようとするPWB8上のノードに検
査パターンを送出し、またノードの出力値を検出し期待
値と比較するピンエレクトロニクスである。このピンエ
レクトロニクスはプローブ3によってPWB上のノード
に接続される。5はPWB上の他の回路、4はエツジコ
ネクタに接続されたピンエレクトロニクスである。ここ
でPWB8を検査する場合にピンエレクトロニクス2か
らLSIIの端子7に対してスイッチ群6をオープンす
る信号を送出することによりLSIの内部論理によらぬ
パターンをLSllとその他の回路5との間のノードに
送出、また検出できる。これによりPWB上にLSI以
外の原因で生じた故障を効率よく検出できることになる
。第2図は本発明の第2の実施例である。本実施例では
LSIIIの端子のうち一部にスイッチ群16を設けで
ある。LSIの入力端子にはスイッチ群を設けなくても
ピンエレクトロニクス12より駆動することが可能であ
ることの応用例である。
FIG. 1 shows a first embodiment of the invention. Here, reference numeral 1 denotes an LSI that can be brought into a terminal high impedance state by a switch group 6 in response to a signal applied to a terminal 7. Further, 2 is a pin electronics that sends a test pattern to the node on the PWB 8 to be tested, and also detects the output value of the node and compares it with the expected value. This pin electronics is connected by probe 3 to a node on the PWB. 5 is other circuitry on the PWB, and 4 is pin electronics connected to the edge connector. When inspecting the PWB 8, by sending a signal to open the switch group 6 from the pin electronics 2 to the terminal 7 of the LSII, a pattern that is not based on the internal logic of the LSI can be detected between the LSII and other circuits 5. Can be sent to and detected by nodes. This makes it possible to efficiently detect failures that occur on the PWB due to causes other than the LSI. FIG. 2 shows a second embodiment of the invention. In this embodiment, a switch group 16 is provided at some of the terminals of the LSIII. This is an application example showing that the input terminal of an LSI can be driven by the pin electronics 12 without providing a switch group.

なお本検査法はプリント配線板のみでなくHIC等にも
応用可能であることは論をまたない。
It goes without saying that this inspection method can be applied not only to printed wiring boards but also to HICs and the like.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、本発明はPWB上に搭載したLS
Iの端子を外部から信号を与えてハイインピーダンス状
態とできるように構成し、これらLSIの端子をふくむ
PWB上のノードにプロービングできる複数本のプロー
ブを有するテストフィクチャーを用いこのテストフィク
スチャーとPWBのエツジコネクタ等から検査パターン
を送出結論を検出比較することによりPWB上の製造要
因による不良をLSIの内部動作と切り離し効率よく検
出できる効果がある。
As explained above, the present invention provides an LS mounted on a PWB.
The terminals of I are configured so that they can be brought into a high impedance state by applying external signals, and a test fixture is used that has multiple probes capable of probing nodes on the PWB including these LSI terminals. By sending test patterns from edge connectors, etc., and detecting and comparing the conclusions, defects caused by manufacturing factors on the PWB can be separated from the internal operation of the LSI and detected efficiently.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の第1の実施例を示す平面図、第2図は
本発明の第2の実施例を示す平面図である。 1・・・・・・端子をハイインピーダンス状態とする機
能をそなえたLSL 2・・川・プローブに信号を送出
、検出比較するピンエレクトロニクス、3・・・・・・
フa−−1,4・・・・・・エツジコネクタ用ピンエレ
クトロニクス、5・・・・・・その他のPWB上の回路
、6・・・・・・LSI内部のスイッチ群、7・・・・
・・LSIをハイインピーダンス状態にする信号の入力
端子、訃・・・・・検査するPWB、11・川・・端子
の一部なハイインピーダンス状態とする機能をそなえた
LSI。 12・・・・・・プローブ用ピンエレクトロニクス、1
3・・・・・・プローブ、14・・・・・・エツジコネ
クタ用ピンエレクトロニクス、15・・・・・・その他
の回路、16・・・・・・LSI内部のスイッチ群、1
7・川・・LSIをハイインピーダンスとする入力端子
、18・旧・・検査するPWB。 代理人 弁理士  内 原   音
FIG. 1 is a plan view showing a first embodiment of the invention, and FIG. 2 is a plan view showing a second embodiment of the invention. 1... LSL with a function to put the terminal in a high impedance state 2... Pin electronics that sends signals to the river/probe, detects and compares, 3...
F-1, 4...Pin electronics for edge connector, 5...Other circuits on PWB, 6...Switch group inside LSI, 7...・
...An input terminal for a signal that puts the LSI in a high-impedance state; ...PWB to be inspected; 12...Pin electronics for probe, 1
3...Probe, 14...Pin electronics for edge connector, 15...Other circuits, 16...Switch group inside LSI, 1
7. River: Input terminal that makes the LSI high impedance. 18. Old: PWB to be inspected. Agent Patent Attorney Oto Uchihara

Claims (1)

【特許請求の範囲】[Claims] 定められた論理信号列を送出しまた受信する機能を持ち
プリント配線板上の任意のノードをプロービングするこ
とのできる複数本のプローブを持つ試験装置を用い、外
部より与えられた信号により入出力端子の一部または全
部をハイインピーダンス状態にすることのできるLSI
を搭載したプリント配線板を検査する時に前記LSIの
入出力端子をハイインピーダンスとし、前記プローブに
より論理信号列を送受することを特徴とするLSI搭載
プリント配線板の検査法。
Using a test device with multiple probes that has the function of sending and receiving a prescribed logical signal sequence and can probe any node on a printed wiring board, input/output terminals are detected by externally applied signals. LSI that can put part or all of the device into a high-impedance state
A method for inspecting a printed wiring board mounted with an LSI, characterized in that when inspecting a printed wiring board mounted with an LSI, input/output terminals of the LSI are set to high impedance, and a logic signal train is transmitted and received by the probe.
JP63036848A 1988-02-19 1988-02-19 Inspection of lsi mounted printed wiring board Pending JPH01212373A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63036848A JPH01212373A (en) 1988-02-19 1988-02-19 Inspection of lsi mounted printed wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63036848A JPH01212373A (en) 1988-02-19 1988-02-19 Inspection of lsi mounted printed wiring board

Publications (1)

Publication Number Publication Date
JPH01212373A true JPH01212373A (en) 1989-08-25

Family

ID=12481182

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63036848A Pending JPH01212373A (en) 1988-02-19 1988-02-19 Inspection of lsi mounted printed wiring board

Country Status (1)

Country Link
JP (1) JPH01212373A (en)

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