JPH01212114A - Pulse generating circuit - Google Patents

Pulse generating circuit

Info

Publication number
JPH01212114A
JPH01212114A JP63036711A JP3671188A JPH01212114A JP H01212114 A JPH01212114 A JP H01212114A JP 63036711 A JP63036711 A JP 63036711A JP 3671188 A JP3671188 A JP 3671188A JP H01212114 A JPH01212114 A JP H01212114A
Authority
JP
Japan
Prior art keywords
pulse
output
operation
charging
discharging
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP63036711A
Inventor
Fumio Miyaji
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP63036711A priority Critical patent/JPH01212114A/en
Priority claimed from US07/312,865 external-priority patent/US5054000A/en
Publication of JPH01212114A publication Critical patent/JPH01212114A/en
Application status is Granted legal-status Critical

Links

Abstract

PURPOSE: To execute the pulse output of an arbitrary pulse width by providing a latch circuit to be set by a pulse input and to be reset by a reset pulse from a charging and discharging circuit.
CONSTITUTION: A latch circuit 1 is set by the input pulse and the rising (falling) of the pulse is generated by the output. The input pulse is simultaneously supplied to a charging and discharging circuit 2 as well and charging operation, discharging operation or operation to couple those operation is executed. Then, the output level is changed according to the respective operation. Since the output level causes the threshold voltages of the R terminal of the latch circuit 1 to cross, reset operation is executed in the latch circuit 1 and the output pulse rises (falls). Thus, the width of the output pulse is determined by the charging and discharging characteristic of the charging and discharging circuit 2. Thus, the output pulse of the arbitrary pulse width can be generated.
COPYRIGHT: (C)1989,JPO&Japio
JP63036711A 1988-02-19 1988-02-19 Pulse generating circuit Granted JPH01212114A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63036711A JPH01212114A (en) 1988-02-19 1988-02-19 Pulse generating circuit

Applications Claiming Priority (7)

Application Number Priority Date Filing Date Title
JP63036711A JPH01212114A (en) 1988-02-19 1988-02-19 Pulse generating circuit
US07/312,865 US5054000A (en) 1988-02-19 1989-02-17 Static random access memory device having a high speed read-out and flash-clear functions
DE1989627552 DE68927552D1 (en) 1988-02-19 1989-02-20 storage devices
DE1989627552 DE68927552T2 (en) 1988-02-19 1989-02-20 storage devices
EP19890301639 EP0331322A3 (en) 1988-02-19 1989-02-20 Memory devices
EP93202350A EP0574094B1 (en) 1988-02-19 1989-02-20 Memory devices
US07/636,578 US5047985A (en) 1988-02-19 1991-01-02 Static random access memory device having a high speed read-out and precharging arrangement

Publications (1)

Publication Number Publication Date
JPH01212114A true JPH01212114A (en) 1989-08-25

Family

ID=12477347

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63036711A Granted JPH01212114A (en) 1988-02-19 1988-02-19 Pulse generating circuit

Country Status (1)

Country Link
JP (1) JPH01212114A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4844457U (en) * 1971-09-30 1973-06-09

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4844457U (en) * 1971-09-30 1973-06-09

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