JPH01212114A - Pulse generating circuit - Google Patents

Abstract

PURPOSE:To execute the pulse output of an arbitrary pulse width by providing a latch circuit to be set by a pulse input and to be reset by a reset pulse from a charging and discharging circuit. CONSTITUTION:A latch circuit 1 is set by the input pulse and the rising (falling) of the pulse is generated by the output. The input pulse is simultaneously supplied to a charging and discharging circuit 2 as well and charging operation, discharging operation or operation to couple those operation is executed. Then, the output level is changed according to the respective operation. Since the output level causes the threshold voltages of the R terminal of the latch circuit 1 to cross, reset operation is executed in the latch circuit 1 and the output pulse rises (falls). Thus, the width of the output pulse is determined by the charging and discharging characteristic of the charging and discharging circuit 2. Thus, the output pulse of the arbitrary pulse width can be generated.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a pulse generation circuit formed as a part of a semiconductor integrated circuit device, such as a memory device, a microcomputer,
The present invention relates to a pulse generation circuit that can be used in various other LSIs.

[Summary of the invention]

The present invention provides a pulse generation circuit that converts the pulse width and outputs a pulse with a required long pulse width, and has a launch circuit that is set by a pulse input and reset by a reset pulse from a charging/discharging circuit. This makes it possible to output pulses with arbitrary pulse widths.

[Conventional technology]

Generally, in a semiconductor integrated circuit device, various pulses are generated to operate the circuit. Circuits that generate a required internal clock are known.

Further, in such a semiconductor integrated circuit device, a circuit as shown in FIG. 7 is known as a circuit for increasing the pulse width to a required length.

The pulse generation circuit shown in FIG. 7 has an inverter row 71 consisting of six inverters connected in series, and has a two-man powered NAND circuit 72 at the output section. and one input terminal of the NAND circuit 72, and the output of the inverter array 71 is input to the other input terminal of the NAND circuit 72. This circuit can generate an output pulse by adding the delay time t4 caused by the inverter array 71 to the input pulse.

[Problem to be solved by the invention]

However, in the pulse generating circuit as shown in FIG. 7, a problem as shown in FIG. 8 or 9 occurs. Note that in FIG. 8.9, waveform P1 represents the level of P1 in the circuit of FIG. 7.

First, the problem shown in FIG. 8 is the generation of spike pulses Sp. That is, it is assumed that an input pulse with a pulse width t0 is input to the circuit shown in FIG. "H level" (high level) may occur, and as a result, a spike pulse Sp is generated. Therefore, in relation to the input pulse, it is not possible to obtain a very large delay time t4.

Furthermore, the problem shown in FIG. 9 is that the generated pulse width T,
Regarding, since t4≦t0 is a condition that does not generate the spike pulse Sp, the pulse width T of the output pulse is
To ”to + Lm ≦2t.

Therefore, the pulse width T0 of the maximum output pulse is only twice the pulse width t0 of the input pulse.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a pulse generation circuit that generates an output pulse having a predetermined pulse width.

[Means to solve the problem]

The pulse generating circuit of the present invention for achieving the above-mentioned object will be described with reference to FIG. The latch circuit 1 is characterized in that it has a charge/discharge circuit 2 to which an input is input, and that the latch circuit 1 is reset by charging or discharging the charge/discharge circuit 2.

Here, the latch circuit 1 is a circuit that is set and reset, and can be constituted by, for example, a NAND circuit, a NOR circuit, or the like. The charging/discharging circuit 2 can be configured by, for example, a combination of switches, capacitors, resistors, etc., and charging or discharging characteristics can be determined by each of these elements. Various devices such as PMO3, NMO3, 0MO3, bipolar, etc. can be used as elements constituting each of the above circuits.

[Effect]

In the pulse generation circuit of the present invention, the pulse width of the output pulse is determined by the set timing and the reset timing, and since the reset is performed by charging or discharging the charging/discharging circuit, the characteristics of the charging or discharging It is possible to set an arbitrary pulse width according to the

〔Example〕

Preferred embodiments of the present invention will be described with reference to the drawings.

First Embodiment The pulse generating circuit of the first embodiment has a basic configuration as shown in FIG.

This pulse generation circuit includes a latch circuit 1 and a charge/discharge circuit 2.
It consists of The input pulse is supplied to the S (set) terminal of the latch circuit 1 and also to the charge/discharge circuit 2. The output of this charging/discharging circuit 2 is supplied to the R (reset) terminal of the latch circuit 1 as a reset signal.

Then, the output pulse is taken out from the latch circuit 1.

Here, to describe its operation, the latch circuit 1 is set by an input pulse, and a rising (falling) pulse occurs at the output. The input pulse is simultaneously supplied to the charging/discharging circuit 2, and a charging operation, a discharging operation, or a combination thereof is performed, and the output level changes according to each of the above operations.

When the output level crosses the dark value voltage of the R terminal of the latch circuit 1, a reset operation is performed in the launch circuit 1, and the output pulse falls (rises).

In this manner, in the pulse generating circuit of this embodiment, the width of the output pulse is determined by the charging and discharging characteristics of the charging and discharging circuit 2. Therefore, output pulses with arbitrary pulse widths can be generated.

Second Embodiment In this embodiment, as shown in FIG.
and PMO3) constitute a charging/discharging circuit with a transistor 13,
This is an example in which an SR latch circuit is configured with two NAND circuits 11 and 12 each powered by two people, and the input pulse is negative logic.

In its configuration, an input terminal 14 to which a negative logic input pulse is supplied is connected to a PMO3) transistor 13 of a charging/discharging circuit, and is also connected to an S terminal of a NAND circuit 11 constituting a latch circuit. The output terminal of this NAND circuit 11 is connected to the first output terminal 15 of the pulse generating circuit, and the other NAND circuit 12 constituting the latch circuit.
Connect to the input terminal of The output terminal of the NAND circuit 12 is connected to the second output terminal 16 of the pulse generating circuit, and the output terminal of the NAND circuit 12 is connected to the second output terminal 16 of the pulse generating circuit.
Connect to the input terminal of circuit 11.

The charging/discharging circuit is composed of the PMO3I transistor 13, a resistor R3, and a capacitor C3. The gate of the PMO3) transistor 13 is connected to the input terminal 14,
The source is connected to power supply voltage Vcc. This PMO3l
- The drain of the transistor 13 is connected to each terminal of the resistor R1 and the capacitor C, and is also connected to the R terminal of the NAND circuit 12. The above resistance R1 and capacitance C are:
They are connected in parallel, and terminals not connected to the PMO3) transistor 13 are commonly supplied with a ground voltage GND.

The operation of the pulse generator of this embodiment having such a circuit configuration will be explained with reference to FIG.

First, initially, the voltage at point P2 in FIG.
At this time, both of the two input terminals of the NAND circuit 11 are set at the "H" level, and the level of the first output terminal 15 (first output) is at the 1L" level.

Next, time 1. The input pulse (“L” level) is input to the input terminal 14.Then, the output of the NAND circuit 11 becomes H.
Also, the input pulse is simultaneously applied to the gate of the PMO3) transistor 13, and the PMO3) transistor 13 is turned on.The voltage at the 22 points changes from the 'L' level to the above capacitor C3. The voltage gradually changes and approaches the "H" level, which is approximately the power supply voltage Vcc. Then, the output of the NAND circuit 12 becomes II HII when the voltage at 22 points crosses the input dark value voltage.
level changes to "L" level.

Next, at time 1° after T1 time has elapsed from time t, the level of the input pulse changes from the @L" level to the "H" level. In the NAND circuit 11, one input of the above NA
The output of the ND circuit 12 is already at the "L" level,
The logic does not change depending on changes in the input pulse. Due to the level change of the input pulse, PMO3I-transistor 13
switches from on to off. Then, point P2 is disconnected from the power supply voltage Vcc, and is connected to the capacitor C1 and the resistor R.

This causes discharge to begin.

The discharge by this capacitor CI and resistor R8 progresses, and at time t□, the threshold voltage V of the R terminal of the NAND circuit 12 increases as described above.
Where the potentials of the points intersect, that is, NAND circuit 1
When the reset signal is supplied to 2, the NAND
The output of the circuit 12 changes from "L" level to "H" level. Therefore, the output level of the second output terminal 16 is
At this time, it changes to @H Rubel. Since the output of this NAND circuit 12 is also input to the NAND circuit 11, both of the two input terminals of the NAND circuit 11 are "
The output level of the NAND circuit 11 is “H” level.
Changes to L” level.

In this way, in the pulse generating circuit of this embodiment, the time T2 from time t1 to time t2 becomes the pulse width of the output pulse, and it is possible to set an arbitrary pulse width that does not depend on the pulse width T+ of the input pulse.

For example, even if the manual pulse width T1 is about 10 nsec, it is possible to make the output pulse width T2 about 1 sec. Further, as described above, the length of time T2 is determined by the discharge characteristics (time constant) of the capacitor C1 and resistor R3. Therefore, by selecting the size, impurity concentration, dielectric material, etc. of capacitor C3 and resistor R3,
The pulse width T2 of the output pulse can be adjusted arbitrarily.

In addition, both positive and negative pulses can be obtained without adding a gate circuit, and the number of elements can be significantly reduced compared to a system using an inverter array.

Third Embodiment This embodiment is a modification of the pulse generation circuit of the second embodiment, and corresponds to the case where the input pulse is positive logic, and has the configuration shown in FIG. The operation shown in FIG. 5 is performed.

First, as shown in FIG. 4, its configuration is similar to that of the pulse generating circuit of the second embodiment, and the NAND circuit 11. NAN
The D circuit 12 constitutes an RS latch circuit, and the PMOSI-run raster 13. A charging/discharging circuit is configured by the capacitor C and the resistor R1. These RS latch circuits and charging/discharging circuits are the same as those in the second embodiment, and their explanations will be omitted using the same reference numerals.

An inverter 20 is connected to the input terminal 14, and the output of the inverter 20 is connected to the PMO.
It is connected to the gate of the S transistor 13, and the N
Connect to the S terminal of the AND circuit 11.

The pulse generating circuit of the third embodiment operates as shown in FIG. That is, if a positive logic pulse is input to the input terminal 14, by inverting that pulse with the inverter 20, a signal shown at level P in FIG. 5 is obtained. The level of this P is
This corresponds to the input level (input pulse applied to the input terminal 14) of the second embodiment, and therefore, even in the case of positive logic, it is not possible to operate exactly the same as in the second embodiment. It becomes possible.

Other Embodiments Referring to FIG. 6, a pulse generation circuit will be described in which the pulse generation circuit according to the present invention is used as a part of a memory circuit and used as a timing generation circuit of a memory device that employs an auto power down method. do. Although a detailed description of the circuit configuration will be omitted, it is assumed that the circuit configuration has the circuit configurations of the first to third embodiments or other circuit configurations according to the present invention.

FIG. 6 is a time chart of an SRAM, for example, in which the address signal (a), the word line potential (bl, the data output signal (C1), the output pulse (dl) of the ATD circuit (address transition detection circuit), and the auto power down signal (Each signal waveform of el is shown.

At time t, the address signal (al transitions, and at time tl
! The potential of the word line (bl rises, and then data reading is performed at time t+s. Potential peak of the word line)
Among these, the solid line is the waveform of a memory circuit that does not employ the auto power down method, and since it remains at the "H" level, current flows to the memory cell and sense amplifier, which is disadvantageous in terms of power consumption, etc.

Therefore, after the data is determined, the potential (bl) of the word line is lowered as shown by the dotted line, and for this purpose, the pulse width of the output pulse fd of the ATD circuit is extended using the pulse generation circuit of this embodiment. , the potential peak of the word line) falls at a timing t2°.

That is, the output pulse (d) of the ATD circuit is input to the pulse generation circuit of this example, and the SR clutch path is operated to change the auto power down signal tel from the "L" level to the "H" level. .

Subsequently, the output pulse fdl of the ATD circuit changes to the L" level, for example, a discharging operation starts, and after a time period determined by the time constant of the charging/discharging circuit has elapsed, the time t2
At ゜, the auto power down signal tel changes from “H level to 1”.
Changes to L Lebel. Then, the auto power down signal (the potential of the word line using el as a trigger)
Drop down as per the dotted line. Thereafter, within one cycle, power consumption in the memory cells and sense amplifiers is reduced, and overall power consumption can be suppressed.

In particular, when the pulse generation circuit of this embodiment is used in an SRAM, the resistance formed in the same process as the high resistance element of the memory cell can be used as the resistance (R1) of the charging/discharging circuit.
It can be used for many purposes, and it is also good to have a large capacity.

Further, as another embodiment, the present invention can be used as a timer circuit of a microcomputer, and can generate various pulse widths for basic taro clocks, etc. Also,
It can also be applied to a flash clear mechanism for video RAM, etc., and can also be used as an initialization circuit for setting time during initialization.

Note that the charging/discharging circuit in the above-mentioned embodiment has a mechanism that is reset mainly by discharging, but it may also be a mechanism that resets by charging.
A NOR circuit, etc., which is limited to an AND circuit, may also be used. Also,
The pulse generating circuit of the present invention is not limited to the above-mentioned embodiments, and various modifications and applications can be made without departing from the gist thereof.

〔Effect of the invention〕

The pulse generation circuit of the present invention can expand the pulse width independent of the input pulse width by the charging/discharging characteristics of the charging/discharging circuit, and the pulse width of the output pulse can be
It can be arbitrarily adjusted depending on the size of the resistor and capacitor to be formed. Furthermore, by using the pulse generating circuit of the present invention, the overall circuit configuration can be simplified, and positive and negative pulses can be obtained simultaneously. Further, it is possible to apply the present invention to various semiconductor integrated circuit devices.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the basic configuration of the pulse generating circuit of the present invention, FIG. 2 is a circuit diagram of an example of the pulse generating circuit of the present invention, and FIG. 3 is a waveform diagram of the circuit of FIG. FIG. 4 is a circuit diagram of another example of the pulse generating circuit of the present invention, FIG. 5 is a waveform diagram of the circuit of FIG. 4, and FIG. 6 is a diagram of the pulse generating circuit of the present invention when applied to a memory device. Waveform diagram, 7th
The figure is a circuit diagram showing an example of a conventional pulse generating circuit, and FIGS. 8 and 9 are waveform diagrams for explaining problems with the conventional pulse generating circuit. 1... Latch circuit 2... Charge/discharge circuit 11. 12... NAND circuit 13... PMO 3) Transistor C1... Capacity R,... Resistance Patent applicant Sony Corporation Representative Patent attorney Small Akira Be (2 others) Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 (a) 1 Figure 6 Figure 7 Figure 8 Figure 9

Claims (1)

[Claims] A pulse generating circuit comprising a latch circuit that is set by a pulse input and outputs a predetermined pulse, and a charge/discharge circuit to which the pulse input is input, and the latch circuit is reset by charging or discharging the charge/discharge circuit. .