JPH01211126A - Data driving type data processor - Google Patents

Abstract

PURPOSE:To cope with the data set of the arbitrary number of data by rearranging respective data of the data set composed of plural data with the same address information and the sequence information added respectively as an identifier to a prescribed sequence, executing the firing processing and giving the end symbol of final data. CONSTITUTION:The sequence information composed of the sequence number of respective data and the prescribed end symbol of the end in the same data set is prepared and added to the packet in plural data sets having the same address information by a sequence information setting means of an instruction executing means EXE of a data driving type data processor. Respective data of the data set are stored into a cue memory Q, and the data added when the same data as the sequence information are read when respective are stored are outputted. For the data of the set having the same address information read from a memory Q by a firing control means FC, the coincidence of each sequence information is detected and a prescribed processing is executed.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a data-driven data processing device, and more specifically, to a data processing device that is capable of processing data sets such as array data more efficiently. The present invention relates to a data processing device.

[Conventional technology]

Generally, a data-driven data processing device is a so-called non-Neumann type computer that executes a data flow graph in which the flow of data is indicated by arcs and instructions are indicated by nodes connected to the arcs as a program.

In such a data-driven data processing device, data packets containing data to be processed and destination information (indicating the connection destination of an arc) are transferred between various processing elements, specifically, data processing circuits. In the meantime, destination information is changed according to the data flow graph, data is duplicated, or commands (
Four arithmetic operations, etc.) are executed.

The destination information corresponds to the storage address of the instruction to be executed on the data, and by changing the attachment of the destination information, it is possible to apply various instructions to the same data. That is, the destination indicated by the destination information means an instruction node on the data flow graph, and the change of destination information means the connection of arcs.

Each processing element is configured to perform predetermined processing on data as soon as it arrives, and the timing at which data arrives at each processing element is not determined in advance. Therefore, in arithmetic processing, such as a binary operation, which can only be executed when two pieces of data are available as bare data, a bearing mechanism is required to detect the arrival of two pieces of data together with the waiting values. Such a mechanism, the so-called firing mechanism, is, for example, a data flow type processor μP072 that performs a wait using destination information as an identifier.
81 (NEC Corporation) is disclosed on page 196 of "Nikkei Electronics" published on April 9, 1984.

[Problem to be solved by the invention]

By the way, in the conventional data-driven data processing device as described above, when performing arithmetic processing between data sets such as array data that is made up of multiple data in one unit, all data contained in the data set is Even though the same instruction is executed in each data set, each data must be matched with corresponding data in other data sets.

Due to these circumstances, in a waiting mechanism (firing mechanism) based only on destination information, such as that of the conventional data-driven data processing device as described above, multiple pairs of data having the same destination information exist at the same time. Processing according to the program is not guaranteed.

For this reason, for example, each data in a data set should have different destination information, or synchronization should be used to process the next data after completing the processing of one data for each data with the same destination information. The need for control arises.

However, in the former case, it becomes necessary to store instructions for all data in the data set, reducing memory efficiency. Furthermore, it is applicable only to arithmetic processing on a data set for which the number of data is known in advance.

On the other hand, in the latter case, synchronous control is required for arithmetic processing of each data that could normally be executed asynchronously, which makes the most important feature of a data-driven data processing device meaningless and increases the hardware scale. , data processing efficiency also decreases.

Furthermore, in either case, the focus is on processing each piece of data in a data set individually, and the perspective of centrally managing the data set is lacking, so processing is far from efficient.

Due to the above circumstances, for example, it is possible to provide order information to each data in a data set consisting of a plurality of data having the same destination information, and to perform firing control using this order information as an identifier for each data. Conceivable. However, in this case, the following new problems may arise.

Specifically, the firing control means performs firing control using a waiting memory corresponding to destination information included in the arrived data packet. Therefore, since each data in a data set having the same destination information performs firing control using the same area of the waiting memory, for example, when the nth data arrives at the firing control means, the previous one If the firing detection of the (n-1)th data has not been completed, the nth data once passes through the firing control means, goes around the ring-shaped network of the data processing device, and then arrives at the firing control means again.

On the other hand, during this time, there is a possibility that the next (n+1)th data will occupy the area of the waiting memory, but if this possibility becomes reality, the waiting order of firing detection will be changed. For this reason, for example, in a data flow program that performs operations on a data set and single data, as shown in Figure 20, the single data shown on the right side will remain in the n+1st position until the nth operation is completed. is not generated, so the (n+1)th element cannot fire forever.

The present invention aims to solve the problems encountered when handling data sets in conventional data-driven data processing devices.

[Means to solve the problem]

The data-driven data processing device of the present invention includes order information setting means for adding a sequence number and a suffix symbol of the last data to data of each element of a data set composed of a plurality of data having the same destination information. and firing control means for processing each data of the data set having the same destination information in a predetermined order by matching the order information using the order information added by the order information setting means as an identifier.

The present invention detects, as a pair of processing targets, two data packets whose destination information matches each other by a firing control means from among data packets including data to be processed and destination information indicating the destination of the data; In a data-driven data processing device that performs predetermined processing on data included in both data packets, each data packet in a data set consisting of multiple pieces of data having the same destination information is an order information setting means for generating and adding order information consisting of an order number indicating the order and a suffix indicating the last order within the same data set; and an order information setting means for storing each data of the data set; data storage means for adding and outputting the same order information as the order information when each data was stored when reading each data; A firing order is configured to detect the matching of order information of each data of the data set having destination information and execute a predetermined process, and to execute the detection of the match of the order information according to the predetermined order. It is characterized by having a setting means.

[Effect]

In the data-driven data processing device of the present invention, each piece of data in a data set consisting of a plurality of pieces of data is stored in a predetermined manner using the same destination information and the order information added to each piece of data as an identifier. It is possible to perform firing processing by rearranging the data in order, and by adding a suffix symbol to the last data, it is possible to handle a data set with an arbitrary number of data.

[Embodiments of the invention]

FIG. 1 shows an outline of a data flow computer system as an example of a system using the data-driven data processing device of the present invention.

The system shown in the figure uses a ring network RN, which is a ring-shaped transfer path that transfers data packets (consisting of a combination of control information in addition to original data values), which is the basic unit of data within the system. , a network interface N which itself forms part of the ring network RN and controls the input and output of data packets.
IF, NIF, NIFI...N [via Fn,
Old host interface, data storage device D? l, data flow computing devices C1 to DFCn are connected;
A host calculation [HC] is further connected to the host interface H1.

The system's data flow calculation devices C1 to DFCn and network interfaces NIFI to NIFn, respectively, operate as a data-driven data processing device with a ring shape inside, and process data described by a data flow graph. Executes a driven-(data flow) program.

Specifically, first, from the host computer HC, host interface H1, network interface NIF,
A program is downloaded to the data flow computing device Kano Ci via the ring network RN and the network interface NIFi (i is 1 to n), and then along the same route, a start packet, which is a data packet that starts the execution of the program, is downloaded to the data flow. When the program is input to the computing device DFci, execution of the program starts, and when the execution of the program is finished, a termination packet, which is a data packet indicating the end of the execution, is sent from the data flow computer DFci to the network interface NIFi, the ring network RN, It is output to the host computer HC via the network interface NIF and host interface old.

FIG. 2 shows a schematic configuration of the data-driven data processing device of the present invention. In the device shown in the figure, Q is a queue memory, PM
is a program storage means, and NIF is ne.

network interface, FC is firing control means, EXE
is an instruction execution means, and each processing element is connected in a ring shape. Note that 1 to 5 and 30, 40, and 50 are data lines.

An outline of the operation of this data processing apparatus will be explained using FIG. The program (data flow graph) loaded from the host computer HC is stored in the program storage means PM. When the start packet arrives at the program storage means PM via each element, ie, the network interface NIF, the firing control means PC1, the instruction execution means EXE, and the queue memory Q, execution of the program is started. During the execution of a program, the control information of packets input to the program storage means PM is reassigned according to this data flow graph, or data packets are copied according to the same data flow graph.

A selection is made at the network interface NIF as to whether the packet output from the program storage means PM is output to the outside or transferred to the firing control means FC.

The firing control means FC mainly performs firing control processing that detects a left operand and a right operand of a binary operation instruction or the like as a data pair, and outputs the two operands as a pair. The left operand is output on output line 5 and the right operand is output on output line 50.

The command execution means EXE applies a command specified by the control information of the arrived packet to the arrived packet and outputs the command. Both of these elements, the ignition control means pc,
In the instruction execution means EXE, packets are not delayed, but in the network interface NIF, when a packet is input from the outside, when an output cannot be output even if an attempt is made, and when data duplication processing is performed in the program storage means PM. becomes busy. In these cases, subsequent data packets must be stopped and wait for the busy state to be released. Cue memory Q
has a bumper function to temporarily store data and make it wait in such cases.

The program is executed as data packets circulate while each processing element performs the above-described processing. Further, when a plurality of data packets exist inside the data processing device, pipeline type processing can be performed in which different processing is simultaneously performed on each data packet in different processing elements. Therefore, this data processing device can be said to be a ring-shaped pipeline type data processing device.

FIGS. 3 and 4 show a more detailed structure of the data-driven data processing apparatus of the present invention, and FIGS. 5 to 8 show the structure of a data packet processor applicable to this data processing apparatus.

FIG. 5 shows a load packet for downloading data to a predetermined memory inside the data processing device, and FIG. 6 shows a dump packet for dumping (reading) data from a predetermined memory inside the data processing device. Figures 7 and 8
The figure shows an execution packet that is processed during program execution, and when a pair of left and right operands are detected in the firing control means FC and the two operands are output as a pair, the configuration shown in FIG. Become.

Data packets will be explained below based on these figures.

All data packets have a two-word structure, and the first and second words are identified by a header identifier H. Each data packet consists of a data value and other information (control information). Of the control information, fl and fO are bucket 1-i6 identifiers and are defined as shown in Figure 10. Identifies the packet.

The module numbers are host interface old, data storage device DM, and each data flow calculation device 0FCI.

This is a number that identifies each processing module such as DFC2...DFCn, and each module has its own number, so that only data packets having its own module number are input.

The target memory number is a number that specifies the target memory at the time of loading or dumping, and is defined as shown in FIG.

The selection code defines the route by which data packets are processed within the data processing device, and each code value has a meaning as shown in FIG. 12. That is, according to the diagrams in both figures, for example, the start packet is (S2SISO)
- It holds a selection code addressed to the program storage means H called "000", and when this is changed to (S2SISO) = "101" in the means PM,
(52SISO) - “The packet holding 101° is processed in the firing control means FC, and the firing control means F
When C finishes processing, it sends the selection code (S2S, 5
o) -001" is output. This packet is then processed by the instruction execution means EXE,
When the instruction execution means EXE completes the processing, it outputs a packet with the selection code changed to (52SI 5o)="000", so that the packet is processed again in the program storage means H.

In this way, each processing element processes only the packet holding the predetermined selection code shown in FIG. 12, and passes other packets without doing anything, and each processing element The program execution process progresses as the selection code is updated for the next processing element.

In addition, the node number is a number that identifies each node in the data flow graph, and the environment number is a number that identifies each node in the data flow graph.For example, when multiple users of this data processing device simultaneously execute the same program loaded on this data processing device, This is a number to identify each user.

In addition, the sequence number is a number that identifies the sequence relationship of each data packet when processing written in the same program is performed on multiple data packets that have a mutual sequence relationship and have the same node number and environment number. , and E is a tail flag that becomes 1'' only when it is the last data packet among a plurality of data packets having an order relationship.

The combination of the node number, environment number, and order code is called a tag, and two packets with matching tags are detected as the left and right operands of a binary operation.

L/R is a flag that distinguishes between left and right operands, and becomes "1" when it is a left operand.

CY, Ov are calculation flags that are stored as the result of calculation,
CY is a carry flag, and Ov is an overflow flag.

TF is a truth flag stored by executing a condition judgment instruction, and becomes "1" when the judgment result is true, and becomes "0" when the judgment result is false.

Next, the detailed operation of this data processing apparatus will be explained based on FIGS. 3 and 4.

The data-driven data processing device shown in FIGS. 3 and 4 has a configuration in which a plurality of registers are connected in a ring shape through various circuits, and a common signal is supplied to each register. In synchronization with a clock signal (not shown), subsequent data is launched (retained) in each register, and at the same time, the data that was being held up to that point or the data that was being held up to that point is subjected to predetermined processing. The resulting data is latched into the register at the previous stage, thereby transmitting the data sequentially. In other words, multiple pieces of data held in each register on the register ring are shifted all at once toward the previous stage in synchronization with a clock signal, and predetermined processing is performed at each stage during the time until the next clock signal. By repeating the process, a circular pipeline type process is performed. The operation of each processing element will be explained below.

(1) When the first word of the data packet arrives on the queue memory Q data line 1, the header identification signal 101 changes to high level, and in response to this, the F
The IFO control circuit 102 outputs a write signal 105 and sends the arrived data packets to the FIF in the order of the first word and the second word.
Write to O memory 103. The FIFO control circuit 102 has a function of constantly storing the number of data packets staying in the FIFO memory 103. If the number of data packets staying in the FIFO memory 103 is not zero and waiting is not requested by the wait request signal 204, the read signal 104 is output and the earliest data packet written in the FIFO memory 103 is read. The written data packet is read out in the order of the first word and the second word, and is output to the data line 2. When the number of data packets staying in the FIFO memory 103 is zero and when waiting is requested by the wait request signal 204, the read signal 104 is prohibited, reading from the FIFO memo January 03 is prohibited, and the FIFO memory 103 Only writing to is allowed.

(ii) When a data packet arrives at the program storage means concave data line 2, control information 202 is input to the program memory control circuit 201, and the address is stored in the address register 210 if it is a load (dump) packet or if it is an execution packet. The node number is latched via the address information line 211 and is stored in register R1.
The first word of the packet is latched. The output of address register 210 becomes the address to program memory 203. If the control information indicates loading to the program memory 203, the data value of the second word of the packet is output from the register R1 at the next timing, and the write signal 20
8 via data line 212 to program memory 2
Written to 03. Control information is stored in the program memory 20
3, the read signal 207 causes the program memory 203 to be read via the data line 212.
The data value is read from and stored in the second word of the packet.

A connection structure of a data flow graph (program) and constant data values used during execution of the program are loaded into the program memory 203 by the load packet in a format as shown in FIG. 9.

Module number, selection code in Figure 9,
The left and right flags and the node number are control information to be newly added to the packet arriving at the program storage means gate. In addition, a constant flag indicating that a constant data value is stored, and a copy flag indicating that multiple processing of data packets is to be performed are stored.

Returning to FIG. 3 again, the packet that arrived at the program storage means PM is an execution packet (selection code (52S+So)) to be processed by this program storage means PM.
= “000”), then PRO-Ak memory control circuit 2
01 reads the contents of the program memory 203 using the node number held in the address register 210 as an address, and reads the module number, selection code, left/right flag, and node number fields in the first word of the packet as shown in FIG. The second word of the packet is replaced with new control information, and the data value of the second word of the packet is output as is.

At this time, if the copy flag in the flag information 206 (constant flag, copy flag) read from the program memory 203 and input to the program memory control circuit 201 is "0°, processing for the arrived packet ends. If the copy flag is “1” and the constant flag is “
0'', the queue memory Q is requested to wait by the wait request signal 204, the address register 210 is incremented, the program memory 203 is read, the control information is replaced with new control information read from the program memory 203, and the packet is processed. At the same time, new flag information is input to the program memory control circuit 201, and if the newly read constant flag is "0", it is input as the data value of the second word of the packet to be output. The data value held by the packet is output as is, and if the newly read constant flag is "1", the address register 210 is further incremented and the data value is stored in the program memory 20.
3, and outputs this constant data value as the second word data value of the packet to be output.

This operation is repeated while the queue memory Q is kept in the waiting state until the newly read copy flag becomes "0". This is the packet duplication process.

However, if a wait is requested by the wait request signal 302 during the copy process, the copy process is interrupted by incrementing the address register 210 and stopping the supply of the clock signal to the register R1 via the register control line 209.

Further, if a wait is requested by the wait request signal 302 at a time other than the duplication process, the clock signal to the register R1 is stopped, the output of data from the program storage means PM is stopped, and the wait request signal 204 is queued. Output to memory Q.

By such a chain of wait request signals, the present data processing apparatus realizes a configuration in which the queue memory Q is concentrated and held in one place.

(iii) Network interface NIF In network interface NIF, load/
The load packet is erased in the dump control circuit 307 (the header identifier is cleared to '0''), and the module number of the dump packet is updated to the number destined for the host computer HC (for example, [l112 town] = "000"). There are four types of packets that arrive at this interface NIP: (al Packet transferred from data line 3 to data line 4 (internal passing packet) (bl Transferred from data line 3 to data line 4o) Packets transferred (output packets) Tel Packets transferred from the data line 30 to the data line 4 (input packets) (d) Packets transferred from the data line 30 to the data line 40 (external passing packets). Of these, internal passing packets and input packets hold the module numbers set as the numbers of this data processing device, and output packets and external passing packets hold other module numbers.

The input/output control circuit 301 receives control information 303 and 304 from data lines 3 and 3o, respectively. Under the control of this input/output control circuit 301, ■ When internal passing packets and external passing packets arrive at the data lines 3 and 30 at the same time, the internal passing packets pass through registers R2 and R3, and The packet passes through registers R4 and R5 without stopping.

■ When an output packet, an input packet, and an input packet arrive at data line 3.30 at the same time, the output packet is output without stopping via registers R2 and R6, and the input packet is stopped via registers R4 and R7. It is entered without doing anything.

■ When internal passing packets and input packets arrive at data lines 3 and 30 at the same time, registers R2 and R3
, R6 is output to the control signal line 305, and a wait is requested by the wait request signal 302. The packet is input without stopping via R7, and then the inhibit signal and wait request signal are canceled and the internal passing packet passes.

■ When output packets and external passing packets arrive at data lines 3 and 30 at the same time, registers R2 and R3
, R6 is outputted to the control signal line 305, and a wait is requested by the wait request signal 302, and external passing packets are passed through registers R4 and R5. The packet passes through without stopping, and then the prohibition signal and wait request signal are released and the output packet is output.

■ Packets that do not arrive at the data line 3.30 at the same time are transferred along a predetermined route without stopping.

(iv) Firing control means FC When a load (dump) packet arrives, the address is latched into the address tag register 402 via the address information line 401 and output to the address line 419.

The pair generation control circuit 411 receives packet control information 409, outputs a control signal group 410, and outputs a control signal group 410 to the data line 41.
7. Data memo IJ4 via any of the 408
05, the data is loaded into either the tag memory 406 or the sorting memory 407 (one of them is dumped).

A predetermined field of the tag memory 406 functions as a flag memory that stores a presence flag that becomes "1" when waiting data exists. This existence.

In the initial state, the presence flag is cleared to "0" over all addresses of the tag memory 406 by the load flag. Further, the contents of the sorting memory 407 are also cleared across all addresses.

When a firing control execution packet with (S2S+Sa)=“101” arrives, some fields of the packet's tag are loaded into the address tag register (ATR) 402 and output to the address line 419. The existence flag 412 is read out using this as an address.

On the other hand, the remaining field containing the sequence number in the tag of the packet is latched in a data tag register (DTR) 403, and a data tag 418 containing the sequence number is output, and the second word of the packet is output on the data line 417. The data value is output. If the presence flag read here is "0", the data value is written to the data memory 405, the data tag is written to the tag memory 406, and the data value is written to the tag memory 406.
The existence flag of 06 is updated to 1, and the packet update circuit 42
1, the packet is erased. This allows the device to wait for the arrival of the packet from the other party.

If the read existence flag is "1", it indicates that the data value and tag data of the packet that may become a pair have already been stored, and at this time, the sequence number of the arrived packet is included. Tag data 418 and tag memory 40
The tag data read from 6 is compared by a comparator 414. As a result, when the match signal 413 is output, it means that a pair of left and right operands has been detected, and the data value of the arrived packet is transferred to the register R via the data line 404.
9, the data value read from the data memory 405 is sent to RIO via the data line 416 to the registers R11 and R12.
are latched respectively.

Here, if the left/right flag L/R bit of the arrived packet is "l#", the outputs of registers R9 and R12 are valid, and if the L/R bit of the arrived packet is "0", the outputs of registers RIO and R11 are valid. Output becomes valid.

That is, the data value of the left operand is always on the data line 5.
The data values of the right operands are output to the data lines 50, respectively. Also, at this time, the selection code in the packet update circuit 421 is ("2 SI So ) = "0
01”.

When a sorting execution packet with (S2 SI SO) = "111" arrives, the comparator 414 compares the data read from the sorting memory 407 with the sequence number in the tag of the arrived packet.

If the two do not match, the arrived packet is passed through to the data line 5 as is. If the two match, the selection code of the arrived packet is sent to [S251So
) - is updated to "001" and output, and the tail flag of the further arriving packet is set to 0.

', the sorting control circuit 415 adds "1" to the previous value and writes it to the sorting memory 407 via the sequence number line 420, and when the last flag is "1", it writes "0". Write.

Here, the firing process and sorting process by the firing control section FC will be explained with reference to FIGS. 18 and 19.

FIG. 19 is a block diagram showing a more detailed configuration of the sorting control circuit 415.

This sorting control circuit 415 has a sorting memory update circuit 4150 for updating the contents of the sorting memory 407 and a sorting memory initialization circuit 415I for initializing the sorting memory 407 as main components.

Specifically, the sorting memory update circuit 4150 can be configured by combining several adders 74F283 manufactured by Fairchild Corporation, for example.

The sorting control circuit 415 controls the sorting memory 4
Sorting memory write signal 4 given to 07
152 instructs writing, and the sequence number update signal 4153 given to itself instructs update,
Furthermore, only when the end symbol of the input packet is "0", indicating that it is not the end, the value obtained by adding "1" to the sequence number of the input packet is stored in the sorting memory 4.
Write to 07. Also, the sorting memory write signal 4
152 instructs writing and the last symbol of the input packet is "l", that is, it is the last data, "0" is written into the sorting memory 407. In other cases, the sorting memory update circuit 4150 does not update the sorting memory 407.

FIG. 18 is a block diagram showing a more detailed configuration of the pair generation control circuit 411.

The pair generation control circuit 411 includes a firing control logic circuit 4110 that generates a signal that controls the waiting of left and right packets of a binary instruction and a signal that controls sorting processing;
4 A register control logic circuit 4 that generates a signal that controls the selection of the output of each register R9 to R12 shown in FIG.
111, and D-flip-flops 4112, 4113, 4114 for delaying and adjusting the timing of each signal.
It is composed of etc.

As mentioned above, the register control logic circuit 4111 has R9-
A register control signal is generated and output so as to control the output of each register of R12.

The firing control logic circuit 411O has a selection code (S
2SISO) When an execution packet holding = "101" arrives, if the presence flag indicates "θ", a data memory write signal, tag memory write signal, flag memory write signal, and packet erase signal are output, and the flag is Output 'l'' as the memory write value.

As a result, the data value and data tag of the input packet are written into the data memory 405 and the tag memory 406, respectively, and the packet is erased. Furthermore, the existence flag 412 is rewritten to "1" in the flag memory to wait for the arrival of the other party's packet.

The selection code is (S2Ss So) -'10
If an execution packet of 1'' arrives, the existence flag is set to 4.
12 is "1" and the tag match signal indicates a match, the firing control logic circuit 4110 outputs a data memory read signal, a flag memory write signal 1 firing signal, and further outputs a flag memory write value as a flag memory write value. Outputs “0”. As a result, the left and right data are output as a data pair, and the selection code (S2S, So) = “0
01'' and then outputs it as a fired packet to be processed by the instruction execution unit EXE.

When the selection code (S2SISO) = “111” packet 7) arrives, the comparator 41 is activated by the comparison control signal.
4, the sequence number held by the input packet is compared with the contents of the sorting memory 407. As a result of this comparison, if the two match, "01" is output from the firing control logic circuit 41 as a sorting memory write signal, a sequence number update signal, and a destination information update signal, and the contents of the sorting memory 407 are updated. At the same time, the selection code of the arriving packet is (52St So
) is updated to “001”, and the instruction actual hill section Il! output to be processed in xE.

If the comparison results do not match, no control signal is output, and the arrived packet is output as is.

As is clear from the above explanation, the selection code (
Each time a set of packets holding S2SISO)-111'' arrives at the firing control unit FC, the selection code is rewritten in ascending order of the order information held by each, no matter what order they arrive. Therefore, the processing in the instruction execution unit EXE and the program storage unit is executed in ascending order of the sequence numbers.In other words, the arriving packets are rearranged.

When an execution packet with selection code (S2SISO) = “011” arrives, the existence flag is set to “0”.
'', the comparison circuit control signal causes the comparator 414 to compare the sequence number held by the packet and the sorting memory 4.
The contents of 07 are compared. As a result, if a match is detected, the firing control logic circuit 4110 outputs a data memory write signal, a tag memory write signal 1 flag memory write signal, and a packet erase signal, and further outputs "1" as the flag memory write value. Output.

As a result, the data value and data tag of the input packet are written to the data memory 405 and the tag memory 406, respectively, the packet is erased, and the value "1" is written to the presence flag to wait for the arrival of the other packet. It will be in a state of matching.

An execution packet with selection code (S2SISo) = “011” arrives, and at this time, the existence flag is “
1'', the comparison circuit control signal causes the comparator 414 to compare the data tag containing the sequence number of the arriving packet with the contents of the tag memory.

As a result, if the tag match signal indicates a match, the firing control logic circuit 4110 outputs a data memory write signal, a flag memory write signal, a sorting memory write signal,
It outputs a sequence number update signal, further outputs "0" as a flag memory value and "0" as a destination information update signal.As a result, the data pair of left and right data has the selection code updated and then the instruction is executed. The sorting control circuit 41
5, the sorting memory 407 is updated.

As is clear from the above explanation, the selection code (
Even if the presence flag is "0", a packet having S2SISO)="011" will pass through without being stored in the waiting memory, that is, the data memory 405, unless the sequence number is a predetermined value.

Further, since the sequence number memory, that is, the sorting memory 407 is updated only when two packets to be paired are detected and the data pair is output, each data of the data set is sorted in ascending order of the sequence information in the firing control unit FC. It will only be fired according to the following.

In this manner, the firing control unit PC of the device of the present invention can simultaneously perform firing detection and rearrangement of binary data.

(v) Instruction Execution Unit EXE When a load (dump) packet arrives at the instruction code memory 510, the address value is latched in the address register 534 and sent to the instruction code memory 5 via the data line 512.
A data value is loaded into the instruction code memory 510 (the data value read from the instruction code memory 510 is dumped).

When a load (dump) packet arrives at the local memory 505, the multiplexer 503 selects the address information line 502, outputs the address value held in the first word of the packet to the address line 504, and outputs the address value held in the first word of the packet to the data line 5.
The second word of the packet is loaded into the local memory 505 (the data value read from the local memory 505 is dumped) via the second word 07.

Before executing the program, the instruction code memory 510 is loaded with instruction codes corresponding to each node number in the program to be executed using a load packet, and when the instruction code memory 510 is referred to by the node number, the corresponding instruction code is loaded. The code is now read out.

The selection code (
The execution packet/node that holds ="001" contains a 1-operand instruction packet (such as a unary operation instruction) and a 2-operand instruction packet (such as a binary operation instruction).
There is. When the execution bucket y) arrives, the node number is latched in the address register 534, and the corresponding instruction code 513 is read from the instruction code memory 510.

The instruction code 513 is decoded by the decoder 511, and a control signal group 514 corresponding to the type of instruction is output. The control signal group 514 includes registers R14 and R16°R.
1 of the arriving packets in the order of lB, R20, and R22.
It is transferred in parallel with the word entry and used as a control signal in each processing element.

Types of instructions include (al instruction to read from or write to the local memory 505, (bl unary or binary operation instruction, (cl shift instruction, (d) condition judgment instruction, (61 control information update) There is a compound instruction that combines some of the instructions, (n(al~(dl).

The control signal group 514 is divided into a control signal group A to control signal group E corresponding to each of the above commands (al to (el), and each control is performed independently.
(It is possible to execute various compound instructions such as fl.

If reading or writing from the local memory is specified by the control signal group A, the address information line 501 is selected in the multiplexer 503 and the left operand data value of the second word of the packet becomes the address of the local memory 505. For further reading, the buffer 509
The data is read from the local memory 505 and stored in the left data value field of the second word of the packet that has arrived via the data line 507. In the case of writing, the left operand data value of the packet arriving via the data line 508 is written to the local memory 505.

If arithmetic processing is designated by control signal group B, arithmetic logic units (ALUI) 515. Arithmetic logic unit (ALU2)
At 51B, specified arithmetic/logical operations are performed in the order of lower data and upper data of the operand data.

At this time, the lower data value of the left operand data value is input via the data line 526, the lower data value of the right operand data value is input via the data line 527, and the operation result data value is input to the data line 528. The lower data value within is output.

Further, the upper data value of the left operand data values is inputted via the data line 529, and the upper data value of the right operand data values is inputted via the data line 530.
The upper data value of the calculation result data values is output to the data line 531.

If a shift is specified by the control signal group C, a predetermined data shift process is executed in the shifter 517 under the control of the control signal 523, and the zero determination unit 518 determines whether the left operand data value is always zero or not. A determination is made whether or not.

If a condition determination process is specified by the control signal group, the condition determination section 519' performs the specified condition determination under the control of the control signal 524, and outputs the result (true or false).

If the control processing is specified by the control signal group, the control processing section 520 performs the following under the control of the control signal 525.
The specified control processing (updating the node number, updating the sequence number, erasing packet 7, etc.) is performed.

Hereinafter, with reference to FIGS. 13 to 17, the condition determination processing executed by the condition determination processing section 519 and the control processing section 5
The control processing executed by 20 will be explained in more detail.

13th t! l is the condition determination processing section 519 and the control processing section 5
20 is a block diagram showing the detailed configuration of 20. FIG.

The truth/false flag setting circuit 5191 and the sequence number reading circuit 5192 in the figure both receive one of two input systems.

It is composed of a multiplexer that selectively outputs according to a 1-bit control signal. Also, the suffix symbol setting circuit 520
1 is composed of an OR gate operated by two people.

As shown in FIG. 14, the condition determination circuit 5193 is composed of an eight-manpower multiplexer. This condition judgment circuit 5
193, the truth flag of the right operand packet in the case of a two-manpower instruction, various operation flags (zero flag, sign bit, carry flag, overflow flag) resulting from the operation, and the final symbol of the input packet, etc. are input to the input terminal 10+. It~I5. It is given to T6.

Among the control signal group 514 outputted according to the instruction code in the decoder 511 shown in FIG. Then, the second word is input to each processing element while being held in register R19. Then, in accordance with this group of control signals and E, each processing element, that is, each component of the condition processing section 519 and the control processing section 520, executes a predetermined process corresponding to the instruction code.

In the condition determination circuit 5193, as shown in FIG.
) is processed according to the value of , and the judgment result is true (
"DE" or false (00") is output.

The node number update circuit 5202 is composed of an adder as shown in FIG. This node number update circuit 520
2, "1" is input to the carry human power Co only when the control signal E3 is "0" and the judgment result by the above-mentioned condition judgment circuit 5193 shows the true value ("1"). . As a result, the node number of the packet is incremented by 1 and output.

In addition, the signal of the judgment result of the condition judgment circuit 5193 is also given to the truth/false flag setting circuit 5191 as a control signal D2, and when this control signal D2 is 0'', the truth/false flag is set to the truth/false flag in the truth/false flag setting circuit 5191. The judgment result (true or false) is set and output.By the combination of processing in these processing elements, for example, only when the input packet is the last data packet in the data set,
Conditional branching instructions such as updating and outputting node numbers, or conditional judgment instructions that set the truth flag to a true value (“1”) and output it only when the input bucket is the last data in the data set. etc. are executed.

Next, as shown in FIG. 17, the sequence number update circuit 5203 is an adder, and the sequence information initialization circuit 5204 is an
It is composed of D gate. Sequence number update circuit 520
3 executes a sequence number update command to increment the sequence number by 1 under the control of the control signal E1. The order information initialization circuit 5204 executes the order information initialization command to clear the order number and the end number to "0" under the control of the control signal E2. Furthermore, in the suffix setting circuit 5201, a suffix setting command for setting the suffix "l" is executed under the control of the control signal E4.

By executing a data-driven program that combines these various instructions, a data set of data that is sequentially numbered starting from 0 and has order information that retains a final symbol only in the last data is generated. becomes possible.

The generation of such a data set can be executed dynamically by program execution, so the generation interval between each element can be freely set by appropriately inserting other execution instructions between the processes that generate data for each element. It can be adjusted to Such a data set may be stored in a local memory 5 as shown in FIG. 4, for example.
It is generated by being read from a data storage circuit such as 05.

Further, in the sequence number reading circuit 5192 in FIG. 13, a sequence number read command for reading the sequence number held in the input packet as the second word of the packet is executed under the control of the control signal E5. By executing such an instruction,
The data of each element of the dataset is sorted according to its order number.
For example, it becomes possible to write to a data storage circuit such as local memory 505 shown in FIG.

As described above, the packet for which the predetermined process has been executed in the instruction execution unit EXE has the selection code (S2SISoll=″00
0'' (destination is program storage unit PM) and output.

〔Effect of the invention〕

As detailed above (according to the data-driven data processing device of the present invention), the data of each element is managed with order information and arranged in a predetermined order while the same destination information is attached to the entire data set. For example, operations on a data set and single data as shown in Fig. 20,
For example, processing such as obtaining the sum of all element data of array data can be executed according to the program, and furthermore, the efficiency of set data processing such as reading out a data set in a predetermined order, processing it, and writing it again can be improved. improves.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the system configuration of a data flow calculator incorporating the data-driven data processing device of the present invention, and FIG. 2 is a block diagram showing the general configuration of the data-driven data processing device of the present invention. FIGS. 3 and 4 are block diagrams showing detailed configurations of the data-driven data processing apparatus of the present invention, and FIG. 6, 7, and 8 are schematic diagrams showing the structure of a data packet used in the data-driven data processing device of the present invention, and FIG. 9 is a program storage of the data-driven data processing device of the present invention. FIG. 10, FIG. 11 and FIG. 12 are schematic diagrams showing the code comparison, FIG. 13 is a block diagram showing the detailed configuration of the condition judgment processing section and the control processing section, and FIG. Figure 14 is a circuit diagram of the condition determination circuit, Figure 15 is a schematic diagram showing code comparison of the condition determination circuit, and Figure 1
Figure 6 is a circuit diagram showing the configuration of the node number update circuit, No. 17
18 is a block diagram showing the configuration of the pair generation control circuit, FIG. 19 is a block diagram showing the configuration of the sorting control circuit, and FIG. The figure is a schematic diagram showing an example of a data flow program processed by the apparatus of the present invention. PM...Program storage means NIF...Network interface FC...Fire control means E
XE... Instruction execution means Q... Queue memory 40
5... Data memory 407... Sorting memory 411... Pair generation control circuit 414... Comparator 415... Sorting control circuit 505... Local memory 520... Order information setting means 4
110... Firing control logic circuit 4150... Sorting memory initialization circuit 4151... Sorting memory initialization circuit 5201... End symbol setting circuit 5202... Node number update circuit 5203.
...Sequence number update circuit 5204...Sequence information initialization circuit Applicant Sanyo Electric Co., Ltd. Agent Patent attorney Noboru Kono Mistake 1 Figure Al Figure 2 Figure 9 Figure 10 Figure 12 Figure 15 16 Figure

Claims (1)

[Scope of Claims] 1. Among data packets containing data to be processed and destination information indicating the destination of the data, two data packets whose destination information matches are selected as a pair of processing objects by firing control means. For each data packet in a data set consisting of multiple pieces of data having the same destination information, , an order information setting means for generating and adding order information consisting of a sequence number indicating the order of each data and a suffix indicating the last order within the same data set; and each data of the data set. and a data storage means for adding and outputting the same order information as the order information when each data was stored, when reading each data, the firing control means A predetermined process is executed by detecting the coincidence of order information of each data of the read data set having the same destination information, and detecting the coincidence of the order information is executed according to the predetermined order. 1. A data-driven data processing device, comprising firing order setting means for setting the firing order. 2. The firing order setting means includes: an order information storage means for storing a sequence number; a waiting storage means for storing destination information and data included in a data packet; and order information included in an arrived data packet and the order. a comparison means for comparing the order information stored in the information storage means; and a reservation memory control means for writing the data of the data packet in the reservation storage means when the comparison result by the comparison means matches. , when a match is detected by the firing control means, a sequence number storage means updating means for updating the contents of the sequence information storage means according to a predetermined order; and a comparison result by the firing control means coincide; 2. The data-driven data processing apparatus according to claim 1, further comprising sequence number storage means initialization means for initializing the contents of said sequence information storage means when sequence information included in a data packet is a final symbol.