JPH01209832A - Data transmission system - Google Patents

Abstract

PURPOSE:To start the transmission of each terminal equipment without almost any wait time by allowing terminal equipments selecting one of clocks being the shift of a reference clock deviated by an optional phase each to apply data transmission/reception. CONSTITUTION:A reference clock is given in parallel with a transmission line L of plural terminal equipments from a generator CG. Terminal equipments A-C, P1, P2, M generate (n-1) sets of clocks deviating the reference clock by an optional phase based on the reference clock to provide n-set of clocks in total. One of the n-set of clocks is selected and fed to a serial transmitter CC. Thus, each terminal equipment applies time division transmission synchronously with the selected clock from the serial transmitter CC to apply transmission/reception between terminal equipments selecting the clock or the same phase.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data transmission system that allows multiple data transmissions between multiple terminals simultaneously.

[Prior Art] Generally, when data is transmitted between multiple terminals using a serial transmission device, the transfer speed depends on the message processing time of the software at each terminal and the performance factor of the serial transmission device and transmission line. It is known that it can be determined.

Conventionally, the data transmission method used was a CPU transmission method in which the CPU performed all message processing and other work, and a DMA (direct transmission method) between the CPU and a serial transmission device.
A DMA transmission system is known in which a memory access (memory access) controller is provided to store data to be transmitted and received in a memory and transmit the data all at once.

[Problem to be solved by the invention] However, in the former method, if the terminal device processes messages only by the CPU, the CPU must also perform tasks other than message processing, so it is difficult to increase the transfer speed. However, errors such as overruns and underruns occur, making it impossible to increase the transfer speed. Therefore, when this CPU transmission method is applied to transmission between a large number of terminals, there is a problem in that the waiting time becomes too long if, for example, transmission requests from each terminal are concentrated in a short period of time.

For example, eight electronic cash registers A-
H and two printers p1. p2 and hard disk device M
Assuming a system in which the printers are connected via a transmission line, first the cash register A is connected to the printer P.
A transmission request is issued to L, and then the data is sequentially transferred from cash register B to printer P2, from cash register C to hard disk device M, and then from cash register A to printer P2.
When transmission requests are issued one after another to the hard disk drive M at the timing shown in FIG. 6, the start of transmission between the next cash register B and the printer P2 will have to wait for T1 hours after sending the transmission request. , and furthermore, the start of transmission between the next cash register C and hard disk device M will have to wait for T2 hours after sending the transmission request, and furthermore, the start of transmission between the next cash register A and hard disk device M will be delayed until the transmission request is sent. The user will have to wait for T3 hours after sending the message.

As described above, the conventional CPU transmission processing system has the disadvantage that when transmission requests are concentrated, it takes a long time before transmission starts.

In addition, the latter method can increase the transmission speed and shorten the waiting time, making it suitable for transmission between many terminals, but it requires a DMA controller and associated memory capacity for each terminal. There was a problem in that the cost was quite high and it could not be realized at a low cost.

Therefore, the present invention aims to improve economical efficiency by using a CPU transmission method, and provides data transmission that allows each terminal to start transmission with almost no waiting time even if transmission requests are concentrated in a short period of time. The aim is to provide a method.

[Means and effects for solving the problem] The present invention provides a reference clock to the transmission line in parallel when transmitting data between a plurality of terminals via a transmission line, and each terminal also receives the reference clock. Then, create (n-1) clocks by shifting the reference clock by a certain phase to have a total of n clocks, select one of the n clocks, and supply it to the serial transmission device. As a result, data is time-divisionally transmitted in synchronization with the clock selected from the serial transmission device, thereby transmitting and receiving data between terminals that have selected clocks of the same phase.

Therefore, by time-divisionally transmitting data in synchronization with n clocks, data can be transmitted substantially simultaneously between 0 sets of terminals via the same transmission line.

[Example] Embodiments of the present invention will be described below with reference to the drawings.

As shown in FIG. 1, the terminals include, for example, three cash registers A, B, and C, and two printers pl, pz, and 1.
Two disk devices M are connected via a transmission line L. Further, an external transmission control device CC connected to the modem MD is connected to the transmission line L.

Also, a clock generator CG that generates a reference clock
A reference clock from the clock generator CG is transmitted to each of the cash registers A, B, and C, each printer P11P2, the disk device M, and the external transmission control device via a line 1 arranged in parallel with the transmission line L. C
They are supplied to C.

Each cash register A, B, C, each printer PI
, P2, the disk device M, and the external transmission control device CC are each provided with a transmission interface shown in FIG.

This transmission interface takes in the reference clock TlxC from the line 1 via the buffer 1 and supplies it to the first two-man AND gate 2 and the second three-man AND gate 3.

Further, the reference clock TIXC is passed through the D-type flip-flop 4 to generate a clock 'r2xc whose phase is shifted by 9011 points from that clock, and the clock T2XC is applied to the second two-man gate 5 and the third three-man gate 5. gate 6
is supplied to.

Further, the reference clock T1×C is passed through an inverter circuit 7 to a clock whose phase is 180° out of phase with the reference clock T1×C.
r3xc and supplies the clock T3xC to the third two-person gate 8 and the fourth three-person gate 9.

Furthermore, the clock T2XC obtained through the above-mentioned flip-flop 4 is passed through the inverter circuit 10 to generate a clock T4XC whose phase is 180'' out of phase with the clock T2XC, and the clock T4XC is transferred to the fourth two-manual AND gate 1.
1 and the first three-manpower AND gate 12.

Each of the above two-person and game) 2.5.8.11 and each 3
Human power and game) 12, 3, 6.9 also has CPU (
(not shown) signal T,1! ,.

T2. , ,T2. , , T, and □ are respectively input.

The reference clock TIXC from the buffer 1 is also supplied to a timing signal generation circuit 13, which generates two types of timing signals,
One of them is supplied to the T input terminal of the above-mentioned flip-flop 4 and also to the D input terminal of another D-type flip-flop 14, and further via the inverter circuit 15 to the D Supplied to the input terminal. Another timing signal is also supplied to the T input terminal of each flip-flop 14,16.

and supplying the output of the one D-type flip-flop 14 to the first and third three-way gates]2.6;
The output of the other D-type flip-flop 16 is supplied to the second and fourth triple gates 3.9.

The outputs of the two-person AND gates 2, 5, 8.11 are sent to the serial transmission device 18 via an OR circuit 17 as signals TXC, R.
It is supplied as XC.

Further, the outputs of the three-man-powered AND gates) 12, 3.6°9 are supplied to the two-man-powered AND gate 20 via an OR circuit 19. This AND gate 20 receives a signal T from the CPU.
xDBN is input.

The output of the AND gate 20 is supplied via a delay circuit 21 to a gate buffer 22 as its gate control signal.

The buffer 22 controls the transmission of data from the data transmission terminal TXD of the serial transmission device 18 to the transmission line L.

Note that data from the transmission line L is inputted to the data receiving terminal RXD of the serial transmission device 18 via the buffer 23.

Data from the buffer 23 is also input to the D input terminals of four D-type flip-flops 24, 25, 26, and 27. T of each of the flip-flops 24 to 27
The input terminal has the clock Tl xC, T2
3 xC and T4 xC are respectively supplied.

The outputs from the flip-flops 24 to 27 are output as signals T, C8, 'r2cs, T3C3°T4C8 via timer circuits 28, 29 and 30°31, respectively, and are supplied to the CPU.

In such a configuration, when the reference clocks T and XC shown in FIG. 3(a) are inputted from line l through buffer 1, the D-type flip-flop 4 outputs ), the clock T2XC whose phase is shifted by 90° is outputted, the inverter circuit 7 outputs the clock T3xc whose phase is shifted by 180° as shown in (c) of FIG. A clock T4XC whose phase is shifted by 270'' is output as shown in (d) of the figure.

When the signal TIEN from the CPU goes from low level to high level, the first three-man-powered AND gate 12 outputs a high level signal for a predetermined period within the high level of clock T4×C, as shown in FIG. 3(e). A signal is output.

Similarly, when the signal Tzgs from the CPU goes from a low level to a high level, the second three-man AND gate 3 outputs a high level for a predetermined period within the high level of the reference clock T1XC, as shown in FIG. 3(f). When the signal 73EN changes from low level to high level, the third three-person gate 6 outputs the signal (g in FIG. 3).
), a signal that is at high level for a predetermined period within the high level of clock T2XC is output, and further signal T4I! When N goes from low level to high level, the fourth
As shown in FIG. 3(h), the three-man AND gate 9 outputs a signal that remains at a high level for a predetermined period within the high level of the clock T3×C.

Thus the signal T, EN4 T4. , the timing at which the gate of the AND gate 20 opens differs depending on which one of them is selected.

The signal from the AND gate 20 is then delayed by a time t as shown in FIG. 3(i) by a delay circuit 21. Therefore, the signals from each of the above-mentioned three manual AND games) 12, 3, and 6.9 are delayed by a time t in the delay circuit 21 and sent to the buffer 2.
2 as a gate control signal.

By doing this, data is transmitted from the serial transmission device 18 to the transmission line L for a period (T/4-t) with respect to the period T of the reference clock. Note that by providing the time t here, there is no possibility that the outputs of the drivers of each terminal will collide. This transmission is repeated every cycle T of the reference clock, making it possible to transmit data of a desired length. The transmission line for the remaining 3/4 XT is vacant. Therefore, up to three types of data can be transmitted during the remaining 3/4XT period.

In this way, one transmission line L can be used to control data transmission between four sets of terminals almost simultaneously, and even if transmission requests are concentrated, each terminal has almost no waiting time. This means that the machine can start transmitting data.

Also, from the transmission line L through the buffer 23 (
When data as shown in j) is received, the -type flip-flops 24, 25, 26, and 27 each clock T1X.
Since data is sampled at the rising edge of C-T4×C, each timer circuit 28 to 31 outputs
k) High-level signals T, CS, 'r2cs, 'r, cs, and 'r4cs are output at the timings shown in (1), (m), and (n), and which clocks TIXC to T
It can be determined whether data transmission is being performed using 4×C.

Note that the period TW during which each of the timer circuits 28 to 31 outputs a high level is set to a time longer than the maximum value of the interval at which data 0, that is, a low level appears on the transmission line L in one set of transmissions.

Therefore, when transmitting data, the CPU determines whether each of the four channels is busy using signals TLC3-T4C8 as shown in Figure 4, and if there is an empty channel, it specifies that channel. T(T1~
T4) Turn on XCEN and set it to high level. Then, if there is data to be sent, it starts transmission, and when the transmission is finished, TxC
I! Return N to 0FFL low level. Also, if there is received data and the data was sent to itself, it starts transmission with the other party.

By controlling the data transmission in this way, for example, a transmission request is first generated from the cash register A to the printer Pl, and then successively from the cash register B to the printer P2, from the cash register C to the disk device M, and then from the cash register C to the disk device M. Even if transmission requests are generated one after another from the cash register A to the disk device M at the timing shown in FIG. 5, data transmission can be started immediately at the timing when each transmission request occurs.

Moreover, since there is no need for a DMA controller or large memory capacity, costs can be reduced and economical efficiency can be improved.

[Effects of the Invention] As detailed above, according to the present invention, economical efficiency is improved by using the CPU transmission method, and even if transmission requests are concentrated in a short period of time, there is almost no waiting time. Accordingly, it is possible to provide a data transmission method that allows each terminal to start transmission without any delay.

[Brief explanation of the drawing]

The figures show an embodiment of the present invention. Fig. 1 is an overall circuit block diagram, Fig. 2 is a circuit diagram of the transmission interface of each terminal, and Fig. 3 shows input/output waveforms of each part of the circuit diagram. Figure 4 is a flowchart showing the data transmission process; Figure 5 is a waveform diagram showing the data transmission process;
Figure 6 shows the relationship between a transmission request and the start of data transmission.
The figure is a diagram showing the relationship between a transmission request and the start of data transmission in the related art. A, B, C...Cash register, Pll P2
. . . printer, M . . . disk device, 18 . . . serial transmission device. Applicant's agent Patent attorney Takehiko Suzue Figure 4

Claims (1)

[Claims] When data is transmitted between multiple terminals via a transmission line, a reference clock is applied to the transmission line in parallel, and each terminal shifts its reference clock by a certain phase based on the reference clock. n-1) clocks to have a total of n clocks, and by selecting one of the n clocks and supplying it to the serial transmission device, the serial transmission device can transmit the selected clock to the serial transmission device. A data transmission method characterized by time-division data transmission in synchronization, thereby allowing data to be sent and received between terminals that have selected clocks of the same phase.