JPH01208026A - Over-sampling a/d converter - Google Patents

Abstract

PURPOSE:To perform conversion with high accuracy by performing noise suppression with a high gain in a wide band area by inserting a digital integrator which supplies a count result to a quantizer after digital integration at just before the quantizer in a loop. CONSTITUTION:The differential voltage of output voltages from an analog signal input terminal Ai and a D/A conversion circuit 1 for feedback is integrated by an analog integrator 2, and an integration voltage is added on a VCO circuit 3. The VCO circuit 3 oscillates in proportion to the integration voltage, and the number of output waveforms of the VCO circuit is counted at a counter circuit 4. Offset addition and gain control are applied on a count value at a D/D conversion circuit 5, and a result is integrated by the digital integrator 6. Digital integration output is quantized to a digital signal with low resolution of around one bit at a digital quantizer 7, and is fed back at the D/A conversion circuit 1, thereby, a feedback loop is constituted. In such a way, the conversion with high accuracy can be performed by performing the noise suppression with the high gain in the wide band area.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention provides a high-precision, wide-strip oversampling A/
This relates to a D converter.

[Conventional technology]

First, the principle of the oversampling A10 converter will be explained.

To sample an analog signal, according to Nyquist's theorem, the sampling frequency f8 is twice the signal band fmw.
The original signal can be reproduced using . Further, quantization noise generated when the analog signal sampled at f3 is digitized is distributed in the band of DC-f,/2. In a typical A/D converter, f is set to about twice fllW. In contrast, an oversampling A/D converter sets f to a very high frequency with respect to flW, and D
Among the quantization noise widely distributed in C-f,/'2, components outside the signal band are removed by a digital filter, thereby significantly reducing the quantization noise. The higher the sampling frequency f, the greater the effect of reducing quantization noise, and high-precision conversion characteristics complementary to a high-resolution A/D converter can be realized with quantization accuracy of a low resolution of about 1 bit.

Next, the principle of the Δ-Σ type oversampling A/D converter will be explained. Oversampling A/D converter called Δ-Σ type (Reference: T.

&iisaws, J.E., Iwerssn, L.
, J., Loporearo, and J., G., Ru.
eh, ”Single Chip per Chan
n@ICodecwith Flltera Util
izing Delta-Sigma Modulat
ion, IEEE J, 5old-8tate C
1 rcuits.

vol, 5C-16, NIIL4, August
1981. ) is an integrator, quantizer (voltage comparator)
, a feedback D/A conversion circuit forms a feedback loop, integrates the difference between the output of the D/A conversion circuit that feeds back the quantized signal, and the input signal, and the quantizer quantizes this integral value. As a result, the quantization noise is suppressed by the gain of the integrator, the noise level at low frequencies is greatly reduced, and the noise distribution is shifted to a high frequency range. S for fs when quantization noise has the same spectral distribution as random noise
The improvement effect of /H is 3 dB/octave, but in a Δ-Σ type oversampling A/'D converter that suppresses quantization noise with one integrator, double integration with two 9 dB/octave integrators is required. The shape is 15dB/octave and higher S/'N'l'! You can get sex.

The transfer characteristics of the Δ-Σ type oversampling A/'D converter are as follows. FIG. 13 shows the configuration of a Δ-Σ type A/'D converter including one integrator in the feedback loop. The digital output Do of the Δ-Σ type A/D converter is expressed as the following equation in a certain low frequency region of the signal band.

However, Ha is the analog integrator transfer characteristic, and v and a are quantization noise. (2) It is distributed as white noise, but since Hl has a large gain at low frequencies, it is clear that the noise level in the signal band is greatly suppressed. However, if the amplifier gain used in this analog integrator is low, the amount of noise suppression is limited and the operating speed of the circuit is limited by the amplifier band, so the sampling frequency f8 is limited by the amplifier band.

FIG. 14 shows the dependence of S on the input level of the single integral Δ-Σ type A/D converter. Characteristic evaluation was performed by setting the simulation conditions to a sampling frequency f s =256 MHz and a signal band ' m w =4 MHz %. When the amplifier gain is ideal and when the amplifier gain is 2
The case of 0 dB is shown. Amplifier gain is 20d
In case B, the S/N deterioration is significant, indicating that an amplifier with a large gain is required.

Another conventional technology is the voltage controlled oscillator (VoltageC).
An A/D converter using a controlled α mcillator (hereinafter referred to as a VCO circuit) will be described.

FIG. 15 is a block diagram thereof, and the oscillation frequency of the 700 circuit is determined by the following equation.

fv=α(vtv+β)・Surface curve・Curve C2) However, each specification is as shown in Figures 16 to 18, where fv is the VCO circuit oscillation frequency, vlv is the VCO input voltage, α is the sensitivity, and β is the offset. . Also, oscillation sensitivity α='Yl/vlNG
'9m is the VCO oscillation frequency range, ■□. is the input voltage range. Since the VCO circuit does not operate at a negative oscillation frequency, an offset voltage v1 is applied to the input signal and only the positive region is used. The output waveform of a VCO circuit varies depending on the circuit configuration, but generally the phase advance speed increases in proportion to the input voltage, and a pulse is output every time the phase advances by 2π. The period tv of the output pulse is expressed by the following formula: % The configuration of the VCO counting type A/D converter is shown in FIG. 18, and the operating waveform is shown in FIG. 19. The VCO counting type A/D converter has a sample/hold (S/H) circuit, VC.

circuit, counter circuit, and D added as necessary
This is a conventional A/D converter that converts an analog signal into a digital signal at a low sampling frequency f that is 2 to 4 times the signal band. A digital count value proportional to the input voltage is obtained by counting the number of output pulses of the VCO circuit, which oscillates in proportion to the input voltage, by resetting the 700 circuit and the counter circuit every sampling period. Therefore, an S/H circuit is required to keep the input voltage constant during the sampling period.

The transfer equation of the VCO counting type A/D converter can be obtained from the following equation.

First, the counter circuit output N of the VCO counting type A/D converter
c is determined by the following formula.

Ne"(Tm'q)/lv=α(Vtv+β)/"
s Vqe-(4) where TI is the sampling period, t9 is the time error not counted, and tv is the VCO
The circuit oscillation period is V, and e=tq/lv is the quantization error. The D/D conversion circuit converts the counter circuit output into the necessary digital output, Do=Ka(Ne-Kb)
It has the characteristics of As Kb=αβ/f m, D
When the C component is removed, the digital output of the vCO counting type A/D converter. becomes as shown below.

D, = (αVlv/ f vr - Vqe )
``...e) Oscillation sensitivity α'' When fV II/VRNG is substituted, 'VB is the VCO oscillation frequency range, V engineering. is the input voltage range, and Vqe is the VCO quantization noise.

As is clear from the above equation, the noise voltage ratio NjI for the input voltage range is determined by the following equation.

NR knee (7) fv.

When f is set to twice 9fi+w in the signal band, all the quantization noise exists in the signal band, so the S/″N ratio is determined by the above formula. For example, fs=8MH, L1
' v m =512 MT (N in z = 1/64, which is a resolution equivalent to 6 bits.

[Problem to be solved by the invention]

As explained above, in the conventional Δ-Σ type oversampling A/D converter, the conversion accuracy depends on the height of the sampling frequency f and the magnitude of the gain of the analog integrator that suppresses quantization noise. It will improve proportionately. However, the bandwidth and gain of the amplifier used in the analog integrator are limited by device characteristics, the upper limit of the sampling frequency f is determined by the amplifier band ζ, and the amount of suppression of quantization noise is determined by the amplifier gain. Furthermore, since high gain and wideband amplifier characteristics are generally not compatible, a high-precision VD converter is ideal for wideband signals! There was a problem with not being able to read.

Also, even in a counting type A/D converter using 760 circuits, 7
Conversion accuracy improves in proportion to the oscillation frequency range of the 60 circuit, but even if high-speed CMOS devices are used, the oscillation frequency range is only about 500MHz, making it impossible to obtain a high-precision A/D converter with wideband signals. There was a problem.

[Means to solve the problem]

The feature of this output ψJ is that in the conventional Δ-Σ type oversampling A/D converter, the quantization noise is suppressed by the gain of the analog integrator using an amplifier.
By inserting a circuit with a digital integration function into the 60 circuit, we have achieved the same quantization noise suppression effect as when an ideal integrator is used in the 760 circuit and the counter circuit.

[Effect]

The digital integrator suppresses quantization noise.

〔Example〕

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a block diagram of main parts of FIG. 1, and FIG. 3 is a waveform diagram of each part in FIG. 2. In the figure, analog signal input terminal A4
The differential voltage between the output voltage of the feedback D/A conversion circuit 1 and the output voltage of the feedback D/A conversion circuit 1 is integrated by an analog integrator 2, and the integrated voltage is applied to the VCO circuit 3, and the VCO circuit 3 oscillates in proportion to the integrated voltage. The number of VCO circuit output waveforms is counted by a counter circuit 4,
A digital/digital (D/D) conversion circuit 5 performs offset addition and gain adjustment to the counted value, and the digital integrator 6 integrates the counted value. Since the output of the digital integrator is expressed as a multi-bit digital value, it is quantized into a low-resolution digital signal of about 1 bit by the digital quantizer T, which is then R-returned by the D/A converter circuit 1 and sent to the feedback loop. It consists of The bypass path of the digital integrator 6 has a function of advancing the phase in a high frequency range in order to stabilize feedback looseness. Depending on the transfer characteristics of the analog integrator 2 and digital integrator 6, stable operation may occur even if the bypass path is omitted. Further, the digital filter 8 removes out-of-band noise of the digital quantizer cuff to obtain a digital output AD0. The sampling CLK(f,) is supplied to a counter circuit 4 and a digital filter 8, and the counter circuit 4 counts the number of pulses of the VCO circuit output at a period of sampling frequency f. Further, the VCO circuit 3 continuously oscillates independently of the sampling clock.

The vCO circuit 3 is a V-F converter whose oscillation frequency changes depending on the input voltage. (1k) The phase of the output pulse of the VCO circuit 3 advances in proportion to the input voltage, and can be considered as a circuit that converts information on the voltage axis into phase information on the time axis. The pulses of the VCO output are counted by the counter circuit 4 and the accumulated value becomes the integral of the input voltage, and the VCO circuit 3 and the counter circuit 4 can realize an integrator. Further, the value counted by the counter circuit 4 of the number of pulses output from the vCO circuit in a constant period is a value proportional to the input voltage value, and the VCO circuit 3 and the counter circuit 4 can realize a quantizer.

The transfer characteristics of the VCO circuit 3 and the counter circuit 4 are as follows. The counter circuit 4 is a circuit that counts the number of pulses output from the VCO circuit during a sampling period. FIG. 2 shows the configuration of the counter circuit, and FIG. 4 shows waveform diagrams of various parts. V
The input voltage is converted into phase information in the CO circuit 3, but since the counter circuit 4 operates at the rising or falling edge of the vCo output pulse, the phase information between the VCO output pulses is truncated and becomes a quantization error. Become. This quantization error is VC
By causing the O circuit to oscillate continuously without resetting it at the sampling frequency f, it is held as phase information and counted in the next cycle. Therefore, the quantization noise can be reduced by using one integrator and six J-Σ type oversampling A/D.
It is suppressed in the same way as the converter. Further, a digital/digital (D/D) conversion circuit 5 provided at the next stage of the counter circuit 4 has a transfer characteristic capable of correcting the sensitivity α and offset β of the vCO circuit 3. The D/D conversion circuit 4 can be omitted depending on the circuit to be applied. The count value Nc of the counter circuit 4 is calculated from the sum of t, Z, which remained uncounted in the previous sampling period, and the bling period T, and tq, which remained uncounted in the current sampling period.
The subtracted time represents how many times the oscillation period tv of the VCO circuit 3 is. Therefore, Nc calculated by counting the vCO circuit output is expressed by the following equation.

However, fl is the sampling frequency, "qe=t q/
Let l y represent the quantization noise. Also, from equation (2), 1
/1v=fv=α(vlv+β).

The result of counting the VCO circuit output by the counter circuit 4 is DC.
Although it includes an offset, the DC component may be removed when considering the transfer characteristics of the signal component. Therefore, assuming that the DC offset is canceled in the D/D conversion circuit 5, the D/D conversion circuit output Dv is expressed as in the following equation.

αβ/'5-Kb) Kb=αβ/f, then Dv=Ka(Ne-Kb)=Ka(T-Viv-(1-
Z)Vqe) (9) When the overall gain of the VCO circuit 3 and the D/D conversion circuit 5 is Gv, Dv is obtained by the following equation.

By substituting α=fV l/VING, the following equation is obtained.

However, Gv=αKa/fs. From the above formula, VCO
The signal transmission sampling model of circuit 3+counter circuit 4 is as shown in FIG. The quantization noise v and c have differential characteristics (
1-Z) and is suppressed to an extremely small level at low frequencies. Also, v
It is also clear from the above equation that the quantization noise can be reduced if the co oscillation frequency range fv+s is large.

The overall transfer equation of the A/D converter is as follows. FIG. 5 shows the A/'D converter shown in FIG. 1 replaced during the signal transmission sampling period, and reference numeral 9 denotes a VCO circuit 3. v consisting of a counter circuit 4 and a D/D conversion circuit 5
This is the coH conversion part. The digital output D0 of the υ A/D converter is expressed by the following equation.

In the low frequency region of the signal band, Ha, Hd >>
1, so it can be approximated as follows.

Do=Vin (1-Z-') ”Vqc+
v, d...
), we get the following equation.

However, Ha is the analog integrator transfer characteristic, and fil is the VC
O oscillation frequency range, V-0 is VCO input voltage range, v,
c is the quantization noise of the counter circuit, Hd is the digital integrator transfer characteristic, and "qd is the quantization noise of the digital quantizer. Vqes"ld is distributed as white noise, but H, and the differential characteristic (1- Z), the low frequency noise level is greatly suppressed.

If fvl is thick, vqc will be at a lower level than v and d, so the noise level is almost determined by the terms v and d.

This quantization noise suppression characteristic corresponds to the case where the amplifier gain of one analog integrator of a conventional Δ-Σ type A/D converter is infinite. Only fvm changes depending on the characteristics of the VCO circuit, and the quantization noise suppression characteristics are not affected. therefore,
High-precision conversion is possible even with a wide band.

Next, the characteristics of this converter will be explained. The simulation conditions are sampling frequency r's = 256MH,
, the signal band ' m w =4 MHz, and the results of characteristic evaluation are shown in FIG. - The condensation noise level is suppressed at low frequencies with a slope of approximately 40 dB/decade. This slope matches the frequency characteristic of the differential characteristic (1-z-1)2. Further, FIG. 7 shows the dependence of the S/N ratio on the input level. In the conventional VCO counting type,
f□=512MH, 6 when using L vco circuit
It had S, /N characteristics equivalent to that of a bit, but 70
It can be said that the S/N characteristic equivalent to 8 bits or more is obtained with the 0 circuit, and the conversion efficiency is improved by about 12 dB or more.

9. The case where the amplifier gain of the analog integrator is 20 dB is shown in the figure, but the conventional Δ-Σ type A shown by the symbol C
/D converter, S/N deterioration is smaller, 20d
Even when using a low gain amplifier of B, the S/N is equivalent to 8 bits.
% property is obtained.

FIG. 8 is a block diagram showing another embodiment, and is an example in which the subtraction circuit and integrator of the input section are constructed by an RC type integrator 10. Since the RC type integrator 10 can add input signals using the virtual ground point of the amplifier, two input resistors are prepared to add the input voltage and the output voltage of the feedback D/A conversion circuit. . At this time, the polarity is reversed in the integrator, so
The polarity of the input is also reversed. To restore the polarity, simply invert the polarity at the digital filter.

FIG. 9 is a block diagram showing another embodiment, in which the input section subtraction circuit and integrator are switched capacitor type integrator 1.
This is an example configured with 1. In the switched capacitor integrator 11, it is also possible to add input signals by using the virtual ground point of the amplifier, so two input circuits are prepared.
The input voltage and the feedback D/A conversion circuit output voltage are added.

FIG. 10 is a block diagram showing another embodiment, in which the analog integrator 2 of FIG. 1 is omitted and the voltage difference between the input and the feedback D/A conversion circuit output is input to the VCO circuit 3. In this case, the loop gain is reduced and the quantization noise suppression effect is reduced, but the scale of the analog circuit can be significantly reduced.

FIG. 11 is a block diagram showing another embodiment, in which the output signal of the digital quantizer is input to the digital filter 8 and the feedback D/A conversion circuit 1, and the digital integrator input signal is input to the digital quantizer. The result of subtracting the output signal is input to the digital integrator. Feedback to the digital integrator input in this manner is similar to providing a bypass path to the digital integrator, and is similar to providing a bypass path for the digital integrator.
There is a thick force effect to maintain good loop stability when using multiple integrators.

FIG. 12 is a block diagram showing another embodiment.
The digital integrator of the quantizer 12 obtains a sum signal of the input signal and the delay circuit output, inputs this sum signal to the digital quantizer, and further delays the result of subtracting the digital quantizer output from this sum signal. It is configured to be input to the circuit (Z-').

When using an integrator circuit using one delay circuit, the digital 1 quantizer output is fed back to the delay circuit input instead of being fed back to the digital integrator input as shown in Figure 11. has the effect of stabilizing the loop.

In this way, the conventional Δ-Σ type oversampling A/
In the D converter, the sampling frequency is limited by the amplifier band of the analog integrator, and the amount of quantization noise suppression is limited by the gain.
High accuracy could not be obtained over a wide band. However, in the present invention, even if the VCO circuit is operated at high speed, the quantization noise suppression effect does not deteriorate, and a high sampling frequency can be set without deteriorating accuracy, so that high accuracy can be obtained over a wide band.

In addition, in a multiplication type A/D converter using a conventional VCO circuit, all quantization noise is included in the signal band, so 70
The conversion accuracy is determined only by the quantization noise level that is proportional to the size of the signal band flW 'sw/'vm with respect to the oscillation frequency range f□ of the zero circuit. Therefore, the improvement effect of conversion accuracy by increasing fvl is 6dB10at
, is. On the other hand, in the present invention, quantization noise is suppressed in the low frequency range, and high-level out-of-band noise distributed in the high frequency range is also removed, so the conversion accuracy improvement effect by increasing fvB is 15 dB/' c.

It is getting higher. Therefore, as fvl increases, the difference in conversion accuracy between the present invention and the conventional type increases, and the present invention has higher conversion efficiency.

Depending on the field of application, it also has the following effects. Conventionally, oversampling A/D converters for wideband signals such as video signals have been difficult to implement because the sampling frequency is extremely high. Therefore, A
/D converters I and SI are the mainstream of high-speed to useful converters. However, oversampling A/D converters have a small analog circuit scale and are highly compatible with digital filters, etc., and by making them into LSIs using microprocesses, high-speed A/D converters can be made smaller and more economical. has a big effect.

Video signal processing requires precision of 8 bits or more, but conventional systems have a precision of about 6 to 7 bits. However, with the oversampling A/D converter of the present invention, high precision equivalent to or more than 8 bits can be obtained in the video signal band.

This eliminates the need for high-precision analog filters and high-precision sample/hold (S/H) circuits, which were required in conventional flash-type A/D converters, allowing for further downsizing and economicalization. be.

〔Effect of the invention〕

As explained above, this invention has the following effects because a digital integrator is inserted into the vCO loop.

A(1)
Compared to the conventional oversampling A/D converter that suppresses quantization noise using analog separator gain, which is limited by amplifier characteristics, the 700 circuit enables broadband and high-gain noise suppression. Conversion can be achieved.

(2) Since the conversion efficiency is higher than that of a counting type A/D converter using a conventional VCO circuit, highly accurate conversion can be achieved even if the same VCO circuit is used.

(3) V co circuit, analog integrator, feedback D/
All circuits except the A conversion circuit are digital circuits, and
Since the 700 circuit can be easily realized using only transistors like a digital circuit, it can be easily fabricated into a 1-chip LSI using a general-purpose LSI process. Therefore, miniaturization and economicalization can be achieved by using LSI.

(4) Since the scale of the analog circuit is small, it has excellent power supply noise resistance and low power consumption.

(5) Since high-precision elements are not required and high-precision conversion can be obtained without adjustment, manufacturing costs required for trimming etc. can be reduced.

[Brief explanation of the drawing]

Figure 1 is a block diagram showing an embodiment of the present invention, Figure 2 is a block diagram of the main parts of Figure 1, Figure 3 is a waveform diagram of each part of the circuit shown in Figure 2, and Figure 4 is a VCO circuit. A diagram showing a signal transmission sampling model of a combination of counter circuits, FIG. 5 is a diagram in which the A/D conversion circuit shown in FIG. 1 is replaced with a signal transmission sampling model, and FIG. 6 is a graph showing simulation evaluation. FIG. 7 is a graph of S/N ratio input level dependence; FIGS. 8 to 12 are block diagrams showing other embodiments; FIG. 13 is a block diagram showing a conventional example;
Fig. 14 is a graph showing its characteristics, Fig. 15 is a block diagram showing another example of the conventional device, and Figs. 16 to 18 are VC
A diagram showing the characteristics of the O circuit, and FIG. 19 is a diagram showing the operating waveforms of the counter circuit. 1...D/A conversion circuit, 2...analog integrator, 3...VCO circuit, 4...counter circuit, 5
...D/D conversion circuit, 6...Digital integrator, 7...Digital quantizer, 8...Fist digital filter, 9Φ...vCO Mencius conversion unit, 10...・
RC type integrator, 11...Switched capacitor type integrator"15.12...Fist integrator/quantizer. Patent applicant: Nippon Telegraph and Telephone Corporation Agent: Masaki Yamakawa (and one other person)S /N
(dB) Input (dB) 2 S/N (dB)

Claims (2)

[Claims] (1) Integrate the analog signal input to the analog input terminal, count the output of the voltage controlled oscillation circuit whose oscillation frequency is controlled by the integrated output using the sampling clock, and send the count result to the quantizer. Therefore, in an oversampling A/D converter that quantizes and then converts it into an analog signal and adds it to the input signal, a digital integrator that digitally integrates the count result and then supplies it to the quantizer is connected to the quantizer in the loop. Oversampling A/
D converter. (2) The oversampling A/D converter according to claim 1, further comprising a loop for negative feedback of the quantizer output to the digital integrator input.