JPH01205566A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent crosstalks of signal charges generated by light incidence in a photodiode and to obtain a high-quality image screen without blooming or smear by forming a separation area of the form of a very deep groove surrounding the periphery of the photodiode. CONSTITUTION:A cylindrical first groove 40 is formed on a first silicon layer 11 from the upper surface. An insulating film 41 is adhered on the sidewall of the groove, and further silicon 42 is buried. A second silicon layer 13 is formed on the first silicon layer 11 including over the first groove 1. A cylindrical second groove 43 reaching the first groove 40 from this upper surface is formed. An insulating film 44 is adhered on this sidewall, and silicon 45 is buried inside it. A third silicon layer 13 is formed on these, and a third groove 46 reaching the second groove 43 except some part of it is formed. An insulating film 47 is formed on the sidewall, and silicon 48 is buried. A photoelectrical conversion element is formed in the surrounded area inside the third groove, and a signal transfer part is formed adjacent to the portion in which the third groove is not formed.

Description

Detailed Description of the Invention (AJ Industrial Field of Application) The present invention relates to a solid-state imaging device and a groove-type capacitor, which are equipped with a plurality of photoelectric conversion elements and a signal transfer element that extracts and transfers @-charges from these photoelectric conversion elements. The present invention relates to a method of manufacturing a semiconductor device.

(B) Conventional technology In the above-mentioned solid-state imaging device, when a signal charge generated in one photoelectric conversion element enters an adjacent photoelectric conversion element or a surrounding signal transfer element, the resolution deteriorates. , blooming and smear phenomena appear on the imaging screen.

In order to suppress this, according to a technique disclosed in Japanese Patent Application Laid-Open No. 60-233851, a deep and narrow groove is provided surrounding the photoelectric conversion element, and the walls of this groove are covered with an insulating film. At the same time, a groove-shaped isolation region with a dielectric material buried therein is provided.

On the other hand, the trench type capacitor is manufactured by Nikkei Electronics (19
As seen in ``Prototype production of 4 Mbit peripheral CMOS dynamic RAM using groove-type transistor cells'' (published in 1986, 7, 14), a groove is formed in a semiconductor substrate, and a multilayer It has a structure in which electrodes such as crystalline silicon are embedded.

['M Problems to be Solved by the Invention As described above, it is preferable that the depth of the groove-shaped isolation region and the groove of the groove-type capacitor in the solid-state imaging device be as deep as possible.

For example, in a solid-state imaging device, if a separation region with a depth of 5 μm is formed and light with a wavelength of 700 μm is incident on silicon, the amount of light absorbed in the silicon at a depth of 5 μm from the silicon surface is equal to the amount of incident light. The remaining 30% of the light is absorbed in silicon at a depth of 5 μm or more. Signal charges generated by light absorption in silicon with a depth of 5 μm or more diffuse and move laterally without being hindered by the separation region, causing crosstalk that invades adjacent photoelectric conversion elements and signal transfer parts. do. That is, even if a separation region is formed, unless the separation region is deep, the occurrence of crosstalk cannot be suppressed.

On the other hand, in a trench type capacitor, if the depth of the trench is shallow, a large capacitance cannot be obtained. In capacitors, deep trenches are formed in silicon in order to obtain large capacitance.

(2) Means for Solving the Problems A first feature of the present invention is a method for manufacturing a semiconductor device comprising a plurality of photoelectric conversion elements and a signal transfer section that transfers signal charges from these photoelectric conversion elements. , a step of forming a first silicon layer on a silicon substrate, a step of forming a cylindrical first groove from an upper surface in the first silicon layer, and depositing an insulating film on a side wall of the first groove; a step of embedding silicon or a light shielding material in a first groove; and a step of forming a second silicon layer on the first silicon layer including above the first groove;
forming a cylindrical second groove connected to the first groove from the upper surface in the second silicon layer; depositing an insulating film on the sidewalls of the second groove; a step of embedding a light shielding material; a step of forming the second trench and depositing an insulating film on the sidewall of the third trench; and a step of embedding silicon or a light shielding material in the third trench; forming the photoelectric conversion element in a region surrounded by the third groove, and forming the signal transfer section adjacent to a portion where the third groove is not formed. .

Furthermore, a second feature of the present invention is a method for manufacturing a semiconductor device including a semiconductor substrate and an electrode embedded in a trench formed in the semiconductor substrate via an insulating film, the method comprising: forming a groove and forming an insulating film on the inner surface of the first groove; embedding a conductive material in the first groove; and forming a silicon layer on the silicon substrate including the first groove. forming a second groove connected to the first groove from the top surface in the silicon layer, forming an insulating film on the sidewalls of the second groove, and filling the second groove with a conductive material. and,
It is to include.

(1 Actual flow side FIG. 1 is a plan view of an interline solid-state imaging device manufactured by applying the manufacturing method that is the first feature of the present invention.
Figure 2 is a sectional view taken along line 1-1' in the same figure, and Figure 3 is a 1-1' cross-sectional view in Figure 1.
1-1' line sectional views are shown respectively.

In Fig. 1, (1) (1)... are photodiodes arranged in rows and columns, (2) (2)... are photodiodes for one column arranged in the column direction (1) (1). )
These vertical transfer CODs are vertical transfer CODs (202) arranged closely in association with each of the vertical transfer CODs (202)...
has transfer parts equal to the number of photodiodes (1) (1) . . . in a part. (3) is vertical transfer c C
D (2) (2) Horizontal transfer CO placed at the end of...
It is D. Although not shown in the figure, the portions other than the photodiodes (1), (1), . . . are covered with a light shielding film.

In Figures 2 and 3, αO is a p-type silicon substrate, 01) is a p-type first silicon layer formed by epitaxial growth on a p+ type silicon substrate aQ, and 0z is a first silicon layer (fixed on 111). p formed by phase growth
0J is the second silicon layer (p-type third silicon layer grown in solid phase on lz, (14) is the third
There is an n+ type region formed in the silicon layer 03, and the n+ type region is formed in the silicon layer 03.
The type region 04) forms a P-n junction type photodiode (1) together with the second silicon layer 12 and the first silicon layer (11).
) (1)... Fully formed. 05) is an n- region formed in the third silicon layer (13) along with the n+ type region 04.
The n-type buried channel region 06) is a p-type transfer gate region formed between one side of the n-type buried channel region (1,5+) and the n+-type region 04, and Q71 is the n-type buried channel region 09 p formed adjacent to the other side of
The + type stop region aa is an insulating film formed to cover the surface of the third silicon layer IJ, and 19) is an n- type buried channel region 0ω, a p-type transfer gate region σ6) and a p+ type, sandwiching the insulating film 08). The transfer electrode (1) is formed above the insulating film 011, and
91, and the n-type buried channel region σG of the portion covered with the light shielding film
One transfer section of the vertical transfer COD (2) is formed by the transfer electrode 09) and the like.

Furthermore, (22a) (22b) id 7 The isolation region (22a) surrounding the odd diode (1) and arranged between the photodiode (1) and the vertical transfer COD (2) is Immediately below the p++ transfer gate region 06), isolation regions (22b) are formed from the first silicon layer (1 to 2) to the second silicon layer 021, and the isolation regions (22b) arranged in other parts are formed from the first silicon layer (11) to the 2 silicon layer 02 to the surface of the third silicon layer t13).

FIGS. 4 to 9 are cross-sectional views showing the solid-state imaging device having such a structure according to manufacturing steps. Note that these FIGS. 4 to 9 are drawings corresponding to FIG. 2.

In the process shown in FIG. 4, p++ silicon substrate 0.0
A P-type first silicon layer (11) with a thickness of 5 μm is placed on the surface of the
is formed. Next, the first groove (4
0a) (40b) is Reactj-ve construction
It is formed by the Ktchj-ng) method. Furthermore, the first
Silicon oxide films (aa) (ab) with a thickness of 0.2 μm are formed on the side walls of the grooves (4C1a) (40b).

In the process shown in FIG. 5, the first groove (4Oa) (40
b) Amorphous silicon was placed inside the chamber at 550°C (
7) P CV D (Pla8] 11a Enhanc
edChemj-cal Vapor Deposit,
tion), and this amorphous silicon is
cD S P E (5olid Ph
By performing single crystallization using the ase Epi, taxi) method, single crystal silica: ly (42a) (42b) is embedded in the first grooves (40a) (40'b).

Note that the silicon layer formed on the first silicon layer (11) in this step is removed by selective etching.

In the step shown in FIG. 6, p-type amorphous silicon with a thickness of 57 zm is deposited on the first silicon layer (11) and the first grooves (40a) (40b) by PCVD at 550°C. By forming this amorphous silicon into a single crystal using the SPE method under conditions of 600°C, a thickness of 5.
A p-type second silicon layer O2 having a thickness of μm is formed.

In the step shown in FIG. 7, the first groove (40a) (40
b) Ic serial second groove (43a) (0'b) is R work E
After forming the silicon oxide film (2) on the second silicon layer 02) by the method and further forming the silicon oxide film (2) on the side walls of the second grooves (43a) (41b), the second grooves (43a) and (41b) are formed in the same manner as the process shown in FIG. (
43a) (43b) with single crystal silicon (45a) (45
b) is buried.

Through the steps up to FIG. 7, the first groove (,1oa), the second groove (Oa), and the silicon oxide film (,ua) (44a) are formed.
Separation regions (22a) made of single crystal silicon (42a) (4!5a) are formed.

In the step shown in FIG. 8, a p-type third silicon layer (with a thickness of 0.4 μm) is formed on the second silicon layer 0z and the second grooves (43a) (ob) in the same manner as in the step shown in FIG. 1,
3) is formed.

In the process shown in FIG.
f3b) is formed by the P construction E method, and a groove of '@3 (
After the silicon oxide film (47b) is formed on the side wall of the third groove (46b), the third groove (46b) is formed in the same manner as the step shown in FIG.
1)) Single crystal silicon (, 1sb) is buried in (1)).

In this way, the first groove (40b), the second groove (43b),
Third groove (46b), silicon oxide film (4), b) (4
4b) (47b) and single crystal silicon (42b) (4
5'b) (48'b) is formed.

Finally, as shown in FIG.
b) The third silicon layer (11Kn type region 0
4), an n-type buried channel region 05) is also formed in the third silicon layer 0J across the isolation region (22a),
Furthermore, a P-type transfer gate region (16) and a p+-type stop region 0'71 are formed, and the solid-state imaging device shown in FIG. 2 is completed.

In the solid-state imaging device manufactured in this manner, when a pulse voltage is applied to the transfer electrode (1g) while the photodiode (1) is irradiated with light and a charge is generated, the photodiode (1) The signal charge of vertical transfer CCD
After being read in (2), it is transferred downward in FIG. 1 by vertical transfer C0D (2).

At this time, the charges generated in the photodiode (1) in the third silicon layer 03) move only to the n-type buried channel region 05) of the adjacent vertical transfer COD (2). , adjacent photodiode (
It does not flow into 1). In addition, charges generated in the second silicon layer Gz and the first silicon layer can move to the upper third silicon layer (via 131 to the n-type buried channel region 05 of the adjacent vertical transfer C0D (2)). , due to the presence of the isolation regions (22a) and (22b), it does not move laterally and enter the unwanted vertical transfer COD (2) or the adjacent photodiode (1).

In this way, the third silicon layer 03), the second silicon layer a
, z, and the undesired lateral movement of charges generated in the first silicon layer ffl+ extends to a depth of approximately 10 to 11 μm from the surface of the third silicon layer 09, which is the light incident surface. It is blocked in the separation regions (22a) (22'b). Since 91% of the incident light is absorbed up to this depth of 10 to 11 μm, the separation region (22a)
(22b) will block almost all charge crosstalk.

Note that the remaining 9% of the incident light reaches the p+ type silicon substrate αO and generates a charge, but the p++ type silicon substrate 00
Since the charge generated in 2 has an extremely short lifespan, it disappears quickly, and virtually no crosstalk occurs.

As another example, the single crystal sheets U = + 7 (42a) (45a
) (42bX45b) Instead of (48b), a light shielding material (for example, W, MO, etc., or a silicide thereof) may be used. In this case, even if light enters the photodiode (1) from an oblique direction, this incident light will be transmitted to the separation region (22a) (2).
2b) will not be incident on the adjacent photodiode (1), thereby preventing crosstalk of the incident light.

Incidentally, if the process shown in FIG. 7 is performed a plurality of times, it is possible to form a groove-shaped separation region with a depth greater than that of this embodiment, and the effect of blocking the lateral movement of charges is improved.

Next, FIGS. 10 to 13 are cross-sectional views showing each manufacturing process when manufacturing a trench type capacitor by the manufacturing method that is the feature of '@2 of the present invention.

In the step shown in FIG. 10, a first groove 61) with a depth of about 5 μm is formed in the p-type silicon substrate ring by RIE method, and a 0.2 μm thick silicon layer is formed on the inner surface of the first groove 1). An oxide film 62 is formed.

In the step shown in FIG. 11, conductive polycrystalline silicon (T) is buried inside the first trench tIp by the PCVD method.

In the process shown in FIG. 12, the silicon substrate
5 μm thick p-type amorphous silicon is placed on top of the groove of
A p-type silicon layer with a thickness of 5 μm is formed by forming the amorphous silicon using the POVD method at 50°C and single-crystalizing the amorphous silicon using the SPE method at 600°C. .

In the step shown in FIG. 13, a second trench connected to the first trench Gυ is formed in the silicon layer by RIE, and a silicon oxide film (4) is formed on the sidewall of the second trench. Ru. Thereafter, six pieces of conductive polycrystalline silicon are buried in the second clean can in the same manner as in the process shown in FIG.

In this way, a groove type capacitor with a depth of about 10 μm is formed, but by repeating the steps shown in FIG. 13, a deeper (in other words, a larger capacitance) groove type capacitor can be formed.

()l Effects of the Invention According to the present invention, it is possible to form an extremely deep groove-shaped isolation region surrounding the photodiode, which is unprecedented, so that the cross-section of signal charges generated in the photodiode due to light incidence is prevented. No talk occurs, so a high-quality imaged screen without blooming or smear can be obtained.

Furthermore, a very deep trench type capacitor can be formed, and a capacitor with a large capacity can be obtained in a small area.

[Brief explanation of the drawing]

FIG. 1 is a plan view showing an interline solid-state imaging device manufactured by applying the present invention, and FIG. 2 is an I-1'
3 is a sectional view taken along line I-1' in FIG. 1, FIGS. 4 to 9 are sectional views showing each step of the manufacturing method according to the first feature of the present invention, and FIGS. FIG. 13 is a cross-sectional view showing each step of the manufacturing method according to the second feature of the present invention. (1)...Photodiode, (2)...Vertical transfer CCD, 00...p+ type silicon substrate, 0@1 silicon layer, 12...2nd silicon layer, (IJ... Third silicon layer, (22a) (22b)...separation region,
■...Silicon substrate, 61)...First groove,)
...polycrystalline silicon, (foundation)...silicon layer, Zeng...
・@2 groove, 671...polycrystalline silicon. -C 1 Ward 0 Ri1 r) -
1 ○ne d C

Claims (2)

[Claims] (1) A method for manufacturing a semiconductor device including a plurality of photoelectric conversion elements and a signal transfer section that transfers signal charges from these photoelectric conversion elements, which includes the steps of forming a first silicon layer on a silicon substrate; forming a cylindrical first groove from the upper surface in the first silicon layer; depositing an insulating film on the sidewall of the first groove; embedding silicon or a light shielding material in the first groove; forming a second silicon layer on the first silicon layer including over the first groove; and forming a cylindrical second groove continuous with the first groove from the upper surface in the second silicon layer;
a step of depositing an insulating film on the side wall of the second groove;
a step of embedding silicon or a light shielding material in the groove; a step of forming a third silicon layer on the second silicon layer including over the second groove; a step of forming a continuous third groove except for a part thereof, and depositing an insulating film on the side wall of the third groove; a step of embedding silicon or a light shielding material in the third groove;
forming the photoelectric conversion element in a region surrounded by the groove, and forming the signal transfer section adjacent to a portion where the third groove is not formed. Method of manufacturing the device. (2) A method for manufacturing a semiconductor device including a semiconductor substrate and an electrode buried in a groove formed in the semiconductor substrate via an insulating film, the method comprising: forming a first groove in a silicon substrate; a step of forming an insulating film on the inner surface of the groove; a step of embedding a conductive material in the first groove; a step of forming a silicon layer on the silicon substrate including the first groove; forming a second groove connected to the first groove from the top surface;
a step of forming an insulating film on the side wall of the second trench;
A method of manufacturing a semiconductor device, comprising the step of embedding a conductive material in a groove.