JPH01200663A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To obtain a semiconductor storage device whose operation margin is wide, whose access time is short and whose manufacture is easy by a method wherein bit-line pairs are composed of different wiring layers and whose which have been crossed at the middle point and those which have been crossed two times at 1/4 and 1/3 points are arranged alternately. CONSTITUTION:Aluminum wires as indicated by (A) and polycide wires as indicated by (B) are used as bit lines; they are crossed mutually at the 1/2 point of their length; a first bit-line pair composed of a bit line 3a continued from polycide aluminum and a bit line 3b continued from aluminum polycide is constituted; similarly, two each of said wires are crossed at the 1/4 point and the 1/3 point of their length; a second bit-line pair composed of a bit line 3c continued from aluminum polycide aluminum and a bit line 3d continued from polycide aluminum polycide is constituted; the first bit-line pair and the second bit-line pair are arranged alternately. Because the adjacent bit lines are composed of different wire materials and are situated in different wiring layers in this manner, a capacitance value between the lines is small; in addition, because a half of the length of the bit line is constituted by the wire material whose resistance value is low, a read-out signal can be transmitted at high speed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device using a bit line pair in a bit line portion, and hereinafter, a MOS type dynamic memory device.
This will be explained using random access memory (DRAM) as an example.

[Conventional technology]

Figure 3 shows a DRAM using the conventional folded bit line method.
1 is a conceptual configuration diagram of the memory array section of the memory array section. In the figure, 1 is a memory row decoder, 2 is a word line selected by the row decoder 1, 3 is a bit line that intersects the word line 2, and 4 is a word vA2 and a bit line. A memory cell 5 provided at a required intersection with the line 3 is a sense amplifier (abbreviated as a sense amplifier) that reads the contents of the memory cell 4 via the bit line 3.
(including an active restore circuit). In the figure, Cff1l is the parasitic capacitance between the bit lines 3, and C3° is the ground capacitance of the bit lines 3.

256 kbit gusset (7) DRAM tech, bit v
Aluminum has generally been widely used as the wiring material for A3, but with the advent of IMbit, polycide bit lines have become mainstream. The reason is that when the memory capacity reaches Mbit, the bit line pitch becomes 4 μm.
As shown below, in the case of aluminum wiring, the film thickness cannot be reduced to less than about 1 μm considering the wiring resistance of the peripheral circuit and the electromigration resistor, so the above-mentioned parasitic capacitance* Cms increases rapidly. This is because the operating margin is significantly impaired due to signal interference between the bit lines. Since polycide can be made as thin as 0.3 μm, the bit line width can be narrowed and the bit line spacing can be widened.At the Mbit level, the line-to-line parasitic capacitance C1l is small (capacitance to ground C8゜(3% or less)
, the above problem does not occur. However, polycide has a wiring resistance higher than that of aluminum (up to 10" times), which causes a delay in access time. This will be briefly explained using FIG.

FIG. 4 is a diagram showing the timing of operation waveforms when reading from a general RAM. During the precharge period, the bit line 3 is precharged and equalized. As shown in (a), at time t. The potential of word vA2 rises, and ti stored in the storage capacitor of memory cell 4 is read out to bit line 3.

This read signal propagates through the bit line 3 and begins to reach the node of the sense amplifier 5 at time 1, as shown in (bl), and after reaching the node completely, the sense amplifier 5 reaches the node at time t2, as shown in (C). The activation signal rises, which causes (
As shown in b), the bit line 3 at the low (“L”) level is lowered to the ■83 level, and then the bit line 3 at the high H”) level is lowered to the ■c
It is raised to c.

Here, t0 to 1. The time required for the read signal from the memory cell 4 located farthest from the sense amplifier 5 to reach the sense amplifier 5 is determined by the resistance of the bit line 3, and in the case of a polycide bit line, this time is determined by the access time. The proportion of the total time is about one-fourth, and this proportion is expected to increase as the degree of integration increases.

Here, the parasitic capacitance CI between the bit lines mentioned earlier! Let me explain a little more about the problem of signal interference caused by +. As shown in FIG. 4(a), after raising the potential of the word line 2, when "H" level information is read from the memory cells 4 to all the bit lines 3, the reference level bit line is Since it is sandwiched between bit lines of llH and R levels, it receives noise from the adjacent bit line due to the parasitic capacitance Cl1ll between the focus lines, and the potential rises slightly.
The bit line at “H” level also receives the reaction and becomes the original “H” level bit line.
Therefore, the read potential difference between the 3 pairs of bit lines becomes smaller, and the read margin decreases.This means that even if "L" level information is read out to all bit lines 3, happen.

[Problem to be solved by the invention]

Since the conventional DRAM is configured as described above, there is a problem that the capacitance between the bit lines greatly impairs the operating characteristics or increases the access time.

This invention was made to solve the above-mentioned problems, and has a low inter-bit line capacitance, low bit line resistance, and is not affected by noise from adjacent bit lines.
That is, the object is to obtain a high-speed semiconductor memory device with good operating characteristics.

[Means to solve the problem]

A semiconductor memory device according to the present invention has a first line made of a first line material that has a low resistance but cannot be made very thin, and a second line material that has a relatively high resistance but can be made thin. A first bit line pair is formed by arranging the second bit line pair and electrically connecting the two lines to intersect with each other at a point half the length of the first bit line pair. /4
A second bit line pair is arranged alternately with a second bit line pair configured by electrically connecting the above two lines so that they intersect with each other at the point 3/4 and the point 3/4.

[Effect]

In the bit lines of the semiconductor memory device according to the present invention, adjacent bit lines are made of different line materials and are located in different wiring layers.
The line capacitance is small, each bit line in each bit line pair receives the same amount of noise from the adjacent bit line, and half of the bit line length is made of the first line material with low resistance. Therefore, the transmission of read signals is faster than with bit lines that are all made of general second line material, and since the capacitance and resistance of each bit line in the bit line pair are exactly the same, malfunction of the sense amplifier is prevented. Does not occur.

〔Example〕

FIG. 1 (al is a schematic plan view showing the bit line part of one embodiment of the present invention, FIG. 1(b) is a schematic cross-sectional view of I++-I++ cotton, and FIG. 3 is a conventional example. The same reference numerals indicate equivalent parts. In this embodiment, as shown in the figure, an aluminum wire indicated by A and a polycide line indicated by A are used as the bit lines, and they are cross-connected to each other at a point 1/2 of the length. do,
The first bit line pair consists of a bit line L'A3a that is continuous with polycide-aluminum and a bit line 3b that is continuous with aluminum-polycide.
Cross-connect the above two lines at the 4 and 3/4 points,
A second bit line pair is formed of a bit line H3c that continues from aluminum to polycide, and a bit line 3d that continues from polycide to aluminum, and a bit line 3d that continues from polycide to aluminum, and the first and second bit line pairs are arranged alternately. be. Although polycide and aluminum may be used as they are to bridge the cross-connections, aluminum and polycide may be connected using another wiring layer.

In FIG. 1(a), each bit "fLIA3a, 3b
, 3c, and 3d, half of their total length L/2 is made of aluminum and L/2 is made of polycide, so the total resistance from the sense amplifier to the farthest end is the same for any bit line, and this resistance The value is about half of the total length of polycide.

In addition, the bit line spacing (jtcsm, ground capacitance C1°) of each bit line is equal, and in particular, adjacent bit lines are
As shown in 1, since they are in different wiring layers, the distance between the lines is long, and therefore C1@ becomes extremely small. Further, as is clear from FIG. 1(a), the amount of noise received by each bit line of the ζ bit line pair from the adjacent bit line is completely equal. Furthermore, since the wiring pitch between aluminum and polycide is twice the bit line pitch, patterning during production is also facilitated.

Although aluminum and polycide are used as the wiring materials for the bit lines in the above embodiments, the present invention is not limited thereto, and other wiring materials may be used. In addition, there is a slight difference in the total bit line resistance between the first bit line pair that crosses once and the second bit line pair that crosses twice due to the resistance at the intersection (contact resistance, etc.). There is a risk of hurting margins. To prevent this, the first bit line pair having a midpoint crossing P has a "pseudo crossing" (indicated by Q) at the sense amplifier end of the bit line as in the other embodiment shown in FIG. ) may be provided.

〔Effect of the invention〕

As described above, according to the present invention, bit line pairs are formed using different wiring layers, such as one that intersects at the midpoint, and one that intersects at the midpoint.
Since the points that intersect twice are arranged alternately, it is possible to obtain a semiconductor memory device that has a wide operating margin, short access time, and is easy to manufacture.

[Brief explanation of the drawing]

FIG. 1(a) shows a dynamic R according to an embodiment of the present invention.
FIG. 1(b) is a schematic plan view showing the bit line portion of the AM, FIG. 3 is a conceptual block diagram of a memory array section of a conventional dynamic RAM, and FIG. 4 is a timing diagram illustrating a read operation of a general dynamic RAM. In the figure, 2 is a word line; 3a and 3b are a first bit line pair, 3c and 3d are a second bit line pair, 4 is a memory cell, 5 is a sense amplifier, A is an aluminum line portion, and the opening is a polycide line portion. Symbols indicate the same or equivalent parts.

Claims (1)

[Claims] (1) A device having a plurality of bit line pairs each having complementary bit lines arranged adjacent to each other, a plurality of word lines intersecting the bit line pairs, and memory cells provided at required locations at the intersections, The bit line pairs are arranged every other bit in the first and second layers, and the first line is made of a first line material that has a low resistance but cannot be made very thin, and the first line is made of a first line material that has a relatively high resistance but cannot be made thin. a second wire formed of a second wire material that can be formed, the first and second wires being cut midway along their lengths and cross-connected to each other; and a second bit line pair formed by cutting the first and second lines at 1/4 and 3/4 points of their lengths and cross-connecting them to each other at the respective points. A semiconductor memory device characterized by being arranged alternately.