JPH01196916A - Logic circuit having set/reset output - Google Patents

Abstract

PURPOSE:To obtain a set and rest function for an output with simple circuit constitution by providing a high voltage terminal, a low voltage terminal, and a changeover circuit switching a voltage from a high voltage and a low voltage both to a high voltage terminal and a low voltage terminal. CONSTITUTION:The changeover circuit 9 switching a voltage from a high voltage and a low voltage both to a high voltage terminal X and a low voltage terminal Y for a logic circuit. Thus, the circuit acts like a substantial logic circuit when a high voltage is applied to the high voltage terminal X for high voltage of the logic circuit and a low voltage is applied to the low voltage terminal X for low voltage of the logic circuit by the switching circuit 9. When a high voltage is applied to both the terminals X, Y by the switching circuit 9, the output goes to a high level and a set output is obtained, and when a low voltage is applied to both the terminals X, Y by the switching circuit 9, the output goes to a low level and a rest output is obtained. Thus, the circuit is simplified, the chip area is less and the function of the clocked inverter and the switching of set/reset are attained by applying the circuit to, e.g., a clocked inverter.

Description

[Detailed Description of the Invention] (Technical Field) The present invention provides a set output and a reset output function in addition to the original logic output as an output signal in various logic circuits such as inverters, ORs, ANDs, and clocked inverters. It is related to logic circuits.

(Prior Art) In order to provide a logic circuit with set output and reset output functions, a set/reset circuit is generally provided on the input side.

For example, FIG. 3 shows a circuit in which a set/reset function is added to a clocked inverter.

1 is the target clocked inverter, and 2 is the previous stage clocked inverter. In clocked inverter 1, PMO is connected between power supply terminal Vcc and ground terminal GND.
C consisting of S transistor 3 and NMOS transistor 4
A MOS innovator is configured, and a PMOS transistor 5 and an NMOS transistor 6 are connected to the inverter, and both MOS transistors 5 and 6 operate in synchronization with a clock signal CK.

The input terminal of the CMOS inverter made up of a PMOS transistor 3 and an NMOS transistor 4 is connected to the output terminal of the clocked inverter 2 at the previous stage, and further connected to an 0M08 circuit made up of a PMOS transistor 7 and an NMOS transistor 8. , MOS transistors 7 and 8 are connected to RES by selector circuit 9a, respectively.
ET signal.

A SET signal is applied.

The functions of this clocked inverter are as follows: SET signal, R
Table 1 shows the results depending on the ESET signal.

Table 1 However, when setting or resetting the function of clocked inverter 1, both MOS transistors 5 and 6 of clocked inverter 2 in the previous stage are turned off, and the output of clocked inverter 2 is placed in a high impedance state. Must be.

Also, when connecting clocked inverters in multiple stages,
Each clocked inverter must be provided with a set/reset circuit, making the circuit complex and requiring a large chip area.

Such problems are not limited to clocked inverters.
The same applies to circuits in which the inverter is replaced with a NAND circuit, NOR circuit, etc., and other logic circuits.

(Objective) An object of the present invention is to provide a logic circuit that can add set and reset functions to an output with a simple circuit configuration.

(Structure) In the present invention, a switching circuit for switching between high voltage and low voltage is provided for both the high voltage terminal and the low voltage terminal of the logic circuit.

If a high voltage is applied to the high voltage terminal of the logic circuit by a switching circuit and a low voltage is applied to the low voltage terminal, the logic circuit functions as an original logic circuit.

When a high voltage is applied to both terminals by the switching circuit, the output becomes a high level and becomes a set output, and when a low voltage is applied to both terminals by the switching circuit, the output becomes a low level and becomes a reset output.

Examples will be specifically described below.

For comparison with FIG. 3, FIG. 1 shows an embodiment in which the present invention is applied to a clocked inverter.

1 is the same clocked inverter as in FIG. X is a high voltage terminal, and ■ is a low voltage terminal.

High voltage terminal X should not be directly connected to power supply terminal Vcc.
An inverter 10 having an input signal A can switch the potential of the high voltage terminal X to Vcc or GND.
Connect to the output terminal of

Do not connect the low voltage terminal Y directly to the ground terminal GND.
An inverter 11 having an input signal B can switch the potential of the low voltage terminal Y to VCC or GND.
Connect to the output terminal of

Input signal A to inverter 10 and input signal B to inverter 11 are controlled by selector circuit 9 .

An example of the selector circuit 9 is shown in FIG.

NOR circuit 12, inverter 13 and NAND circuit 14
three input signals II, I2 . Input signal A of inverter 10 and input signal B of inverter 11 can be created by the combination of I3.

Returning to Figure 1, when using this circuit as a clocked inverter, signal A=L, signal B=H.
Terminal X for high voltage is Vcc, terminal Y for low voltage is G
Connected to ND.

When setting the output to H, both signals A and B are set to L, and the potentials of both terminals X and Y are set to vCC. In this case, the output becomes H regardless of whether the input signal IN is H or L.

Also, when resetting the output to L, use signal A.

Both terminals B are set to H, and the potentials of both terminals X and Y are set to GND. In this case, the output will be low regardless of whether the input signal IN is high or low.

Table 2 summarizes the functions of the circuit shown in FIG.

FIG. 4 of Table 2 shows an example in which a plurality of circuits C each including one clocked inverter of FIG. 1 are connected to form a multi-bit circuit.

1-1 to 1-n are clocked inverters, respectively. High voltage terminal X is for each clocked inverter 1-1
-1-n are commonly connected, and the low voltage terminal Y is also commonly connected to each clocked inverter 1-1 to 1-n. Signals from selector 9 are applied to commonly connected terminals X and Y, respectively, via inverters 10 and 11. Terminals X of all clocked inverters 1-1 to l-n can be connected simply by controlling signals A and B by selector 9.

The potential of Y can be controlled.

In this manner, when the clocked inverter of this embodiment is used, only one set of inverters 10 and 11 is required as a switching circuit for switching the terminal potentials of a plurality of clocked inverters between Vcc and GND.

On the other hand, FIG. 5 shows a case where a plurality of circuits each including one conventional clocked inverter shown in FIG. 3 are connected. In this case, one reset circuit including a PMOS transistor 7 and an NMO transistor 8 is provided for each clocked inverter 1-1 to 1-n, as shown by symbols 15-1 to 15-n. each is required. Therefore, one circuit configuration becomes complicated and requires a large chip area.

Although the embodiment shows an example in which the present invention is applied to a clocked inverter, it can be similarly applied to other logic circuits.

(Effects) In the present invention, a switching circuit for switching between high voltage and low voltage is provided for both the high voltage terminal and the low voltage terminal of the logic circuit. It is possible to switch between functions and set/reset.

When setting or resetting the output of the logic circuit of the present invention, the output of the previous stage does not have to be in a high impedance state, making it easier to use.

When such logic circuits are connected in multiple stages, only one set of switching circuits is required, which simplifies the circuit and reduces the chip area.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram showing one embodiment, Fig. 2 is a circuit diagram showing a selector circuit in the same embodiment, Fig. 3 is a circuit diagram showing a conventional clocked inverter with a set/reset function, and Fig. 4 5 is a circuit diagram showing an example in which one embodiment is connected in multiple stages, and FIG. 5 is a circuit diagram showing an example in which the conventional circuit shown in FIG. 3 is connected in multiple stages. ■・・・Clocked inverter, 9・・・・・・
- Selector circuit, 10.11... Inverter, X... High voltage supply terminal, Y... Low voltage supply terminal.

Claims (1)

[Claims] (1) A logic circuit with a set/reset output in which both the high voltage terminal and low voltage terminal of the logic circuit are provided with a switching circuit that switches between high voltage and low voltage.